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65 #ifndef __INCmvPciUtilsh
66 #define __INCmvPciUtilsh
69 This module only support scanning of Header type 00h of pci devices
70 There is no suppotr for Header type 01h of pci devices ( PCI bridges )
74 #include "mvSysHwConfig.h"
75 #include "pci-if/mvPciIf.h"
76 #include "pci/mvPciRegs.h"
80 /* PCI base address low bar mask */
81 #define PCI_ERROR_CODE 0xffffffff
83 #define PCI_BRIDGE_CLASS 0x6
84 #define P2P_BRIDGE_SUB_CLASS_CODE 0x4
87 #define P2P_BUSSES_NUM 0x18
88 #define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C
89 #define P2P_MEM_BASE_LIMIT 0x20
90 #define P2P_PREF_MEM_BASE_LIMIT 0x24
91 #define P2P_PREF_BASE_UPPER_32 0x28
92 #define P2P_PREF_LIMIT_UPPER_32 0x2C
93 #define P2P_IO_BASE_LIMIT_UPPER_16 0x30
94 #define P2P_EXP_ROM 0x38
96 /* P2P_BUSSES_NUM (PBM) */
98 #define PBM_PRIME_BUS_NUM_OFFS 0
99 #define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS)
101 #define PBM_SEC_BUS_NUM_OFFS 8
102 #define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS)
104 #define PBM_SUB_BUS_NUM_OFFS 16
105 #define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS)
107 #define PBM_SEC_LAT_TMR_OFFS 24
108 #define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS)
110 /* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */
112 #define PIBLSS_IO_BASE_OFFS 0
113 #define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS)
115 #define PIBLSS_ADD_CAP_OFFS 0
116 #define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS)
117 #define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS)
118 #define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS)
120 #define PIBLSS_LOW_ADDR_OFFS 0
121 #define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS)
123 #define PIBLSS_HIGH_ADDR_OFFS 12
124 #define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS)
126 #define PIBLSS_IO_LIMIT_OFFS 8
127 #define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS)
129 #define PIBLSS_SEC_STATUS_OFFS 16
130 #define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS)
133 /* P2P_MEM_BASE_LIMIT (PMBL)*/
135 #define PMBL_MEM_BASE_OFFS 0
136 #define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS)
138 #define PMBL_MEM_LIMIT_OFFS 16
139 #define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS)
142 #define PMBL_LOW_ADDR_OFFS 0
143 #define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS)
145 #define PMBL_HIGH_ADDR_OFFS 20
146 #define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS)
149 /* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */
151 #define PRMBL_PREF_MEM_BASE_OFFS 0
152 #define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS)
154 #define PRMBL_PREF_MEM_LIMIT_OFFS 16
155 #define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<<PRMBL_PREF_MEM_LIMIT_OFFS)
157 #define PRMBL_LOW_ADDR_OFFS 0
158 #define PRMBL_LOW_ADDR_MASK (0xFFFFF << PRMBL_LOW_ADDR_OFFS)
160 #define PRMBL_HIGH_ADDR_OFFS 20
161 #define PRMBL_HIGH_ADDR_MASK (0xFFF << PRMBL_HIGH_ADDR_OFFS)
163 #define PRMBL_ADD_CAP_OFFS 0
164 #define PRMBL_ADD_CAP_MASK (0xf << PRMBL_ADD_CAP_OFFS)
165 #define PRMBL_ADD_CAP_32BIT (0x0 << PRMBL_ADD_CAP_OFFS)
166 #define PRMBL_ADD_CAP_64BIT (0x1 << PRMBL_ADD_CAP_OFFS)
168 /* P2P_IO_BASE_LIMIT_UPPER_16 (PIBLU) */
170 #define PRBU_IO_UPP_BASE_OFFS 0
171 #define PRBU_IO_UPP_BASE_MASK (0xffff << PRBU_IO_UPP_BASE_OFFS)
173 #define PRBU_IO_UPP_LIMIT_OFFS 16
174 #define PRBU_IO_UPP_LIMIT_MASK (0xffff << PRBU_IO_UPP_LIMIT_OFFS)
179 typedef enum _mvPciBarMapping
186 typedef enum _mvPciBarType
192 typedef enum _mvPciIntPin
200 typedef enum _mvPciHeader
203 MV_PCI_PCI2PCI_BRIDGE
209 typedef struct _pciBar
216 /* The 'barBaseAddr' is a 64-bit variable
217 that will contain the TOTAL base address
218 value achived by combining both the 'barBaseLow'
219 and the 'barBaseHigh' parameters as follows:
223 barBaseHigh barBaseLow */
225 /* The 'barSize' is a 64-bit variable
226 that will contain the TOTAL size achived
227 by combining both the 'barSizeLow' and
228 the 'barSizeHigh' parameters as follows:
232 barSizeHigh barSizeLow
234 NOTE: The total size described above
235 is AFTER the size calculation as
236 described in PCI spec rev2.2 */
238 MV_BOOL isPrefetchable
;
239 MV_PCI_BAR_TYPE barType
;
240 MV_PCI_BAR_MAPPING barMapping
;
245 /* Device information structure */
246 typedef struct _mvPciDevice
248 /* Device specific information */
249 MV_U32 busNumber
; /* Pci agent bus number */
250 MV_U32 deviceNum
; /* Pci agent device number */
251 MV_U32 function
; /* Pci agent function number */
253 MV_U32 venID
; /* Pci agent Vendor ID */
254 MV_U32 deviceID
; /* Pci agent Device ID */
256 MV_BOOL isFastB2BCapable
; /* Capability of Fast Back to Back
258 MV_BOOL isCapListSupport
; /* Support of Capability list */
259 MV_BOOL is66MHZCapable
; /* 66MHZ support */
261 MV_U32 baseClassCode
; /* Pci agent base Class Code */
262 MV_U32 subClassCode
; /* Pci agent sub Class Code */
263 MV_U32 progIf
; /* Pci agent Programing interface */
266 PCI_BAR pciBar
[6]; /* Pci agent bar list */
268 MV_U32 p2pPrimBusNum
; /* P2P Primary Bus number*/
269 MV_U32 p2pSecBusNum
; /* P2P Secondary Bus Number*/
270 MV_U32 p2pSubBusNum
; /* P2P Subordinate bus Number */
271 MV_U32 p2pSecLatencyTimer
; /* P2P Econdary Latency Timer*/
272 MV_U32 p2pIObase
; /* P2P IO Base */
273 MV_U32 p2pIOLimit
; /* P2P IO Linit */
275 MV_U32 p2pSecStatus
; /* P2P Secondary Status */
276 MV_U32 p2pMemBase
; /* P2P Memory Space */
277 MV_U32 p2pMemLimit
; /* P2P Memory Limit*/
278 MV_U32 p2pPrefMemBase
; /* P2P Prefetchable Mem Base*/
279 MV_U32 p2pPrefMemLimit
; /* P2P Prefetchable Memory Limit*/
281 MV_U32 p2pPrefBaseUpper32Bits
;/* P2P Prefetchable upper 32 bits*/
282 MV_U32 p2pPrefLimitUpper32Bits
;/* P2P prefetchable limit upper 32*/
285 MV_U32 pciCacheLine
; /* Pci agent cache line */
286 MV_U32 pciLatencyTimer
; /* Pci agent Latency timer */
287 MV_PCI_HEADER pciHeader
; /* Pci agent header type*/
288 MV_BOOL isMultiFunction
; /* Multi function support */
289 MV_BOOL isBISTCapable
; /* Self test capable */
291 MV_U32 subSysID
; /* Sub System ID */
292 MV_U32 subSysVenID
; /* Sub System Vendor ID */
294 MV_BOOL isExpRom
; /* Expantion Rom support */
295 MV_U32 expRomAddr
; /* Expantion Rom pointer */
297 MV_U32 capListPointer
; /* Capability list pointer */
299 MV_U32 irqLine
; /* IRQ line */
300 MV_PCI_INT_PIN intPin
; /* Interrupt pin */
301 MV_U32 minGrant
; /* Minimum grant*/
302 MV_U32 maxLatency
; /* Maximum latency*/
304 MV_U32 funtionsNum
; /* pci agent total functions number */
307 MV_U8 type
[60]; /* class name of the pci agent */
312 /* PCI gloabl functions */
313 MV_STATUS
mvPciClassNameGet(MV_U32 classCode
, MV_8
*pType
);
316 /* Performs a full scan on both PCIs and returns all possible details on the
317 agents found on the bus. */
318 MV_STATUS
mvPciScan(MV_U32 pciIf
,
319 MV_PCI_DEVICE
*pPciAgents
,
320 MV_U32
*pPciAgentsNum
);
323 #endif /* #ifndef __INCmvPciUtilsh */