2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2005 Wu Qi Ming infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
27 #include <asm/bootinfo.h>
29 #include <asm/ifxmips/ifxmips.h>
30 #include <asm/ifxmips/ifxmips_irq.h>
31 #include <asm/irq_cpu.h>
33 void ifxmips_disable_irq(unsigned int irq_nr
)
36 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
38 irq_nr
-= INT_NUM_IRQ0
;
39 for (i
= 0; i
<= 4; i
++) {
40 if (irq_nr
< INT_NUM_IM_OFFSET
) {
41 ifxmips_w32(ifxmips_r32(ifxmips_ier
) & ~(1 << irq_nr
),
45 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
46 irq_nr
-= INT_NUM_IM_OFFSET
;
49 EXPORT_SYMBOL(ifxmips_disable_irq
);
51 void ifxmips_mask_and_ack_irq(unsigned int irq_nr
)
54 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
55 u32
*ifxmips_isr
= IFXMIPS_ICU_IM0_ISR
;
57 irq_nr
-= INT_NUM_IRQ0
;
58 for (i
= 0; i
<= 4; i
++) {
59 if (irq_nr
< INT_NUM_IM_OFFSET
) {
60 ifxmips_w32(ifxmips_r32(ifxmips_ier
) & ~(1 << irq_nr
),
62 ifxmips_w32((1 << irq_nr
), ifxmips_isr
);
65 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
66 ifxmips_isr
+= IFXMIPS_ICU_OFFSET
;
67 irq_nr
-= INT_NUM_IM_OFFSET
;
70 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq
);
72 void ifxmips_enable_irq(unsigned int irq_nr
)
75 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
77 irq_nr
-= INT_NUM_IRQ0
;
78 for (i
= 0; i
<= 4; i
++) {
79 if (irq_nr
< INT_NUM_IM_OFFSET
) {
80 ifxmips_w32(ifxmips_r32(ifxmips_ier
) | (1 << irq_nr
),
84 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
85 irq_nr
-= INT_NUM_IM_OFFSET
;
88 EXPORT_SYMBOL(ifxmips_enable_irq
);
90 static unsigned int ifxmips_startup_irq(unsigned int irq
)
92 ifxmips_enable_irq(irq
);
96 static void ifxmips_end_irq(unsigned int irq
)
98 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
99 ifxmips_enable_irq(irq
);
102 static struct hw_interrupt_type ifxmips_irq_type
= {
104 .startup
= ifxmips_startup_irq
,
105 .enable
= ifxmips_enable_irq
,
106 .disable
= ifxmips_disable_irq
,
107 .unmask
= ifxmips_enable_irq
,
108 .ack
= ifxmips_end_irq
,
109 .mask
= ifxmips_disable_irq
,
110 .mask_ack
= ifxmips_mask_and_ack_irq
,
111 .end
= ifxmips_end_irq
,
114 /* silicon bug causes only the msb set to 1 to be valid. all
115 other bits might be bogus */
116 static inline int ls1bit32(unsigned long x
)
128 void ifxmips_hw_irqdispatch(int module
)
132 irq
= ifxmips_r32(IFXMIPS_ICU_IM0_IOSR
+ (module
* IFXMIPS_ICU_OFFSET
));
136 /* we need to do this due to a silicon bug */
138 do_IRQ((int)irq
+ INT_NUM_IM0_IRL0
+ (INT_NUM_IM_OFFSET
* module
));
140 if ((irq
== 22) && (module
== 0))
141 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT
) | 0x10,
142 IFXMIPS_EBU_PCC_ISTAT
);
145 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
146 #define DEFINE_HWx_IRQDISPATCH(x) \
147 static void ifxmips_hw ## x ## _irqdispatch(void)\
149 ifxmips_hw_irqdispatch(x); \
151 static void ifxmips_hw5_irqdispatch(void)
153 do_IRQ(MIPS_CPU_TIMER_IRQ
);
155 DEFINE_HWx_IRQDISPATCH(0)
156 DEFINE_HWx_IRQDISPATCH(1)
157 DEFINE_HWx_IRQDISPATCH(2)
158 DEFINE_HWx_IRQDISPATCH(3)
159 DEFINE_HWx_IRQDISPATCH(4)
160 /*DEFINE_HWx_IRQDISPATCH(5)*/
161 #endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
163 asmlinkage
void plat_irq_dispatch(void)
165 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
168 if (pending
& CAUSEF_IP7
) {
169 do_IRQ(MIPS_CPU_TIMER_IRQ
);
172 for (i
= 0; i
< 5; i
++) {
173 if (pending
& (CAUSEF_IP2
<< i
)) {
174 ifxmips_hw_irqdispatch(i
);
179 printk(KERN_ALERT
"Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
185 static struct irqaction cascade
= {
186 .handler
= no_action
,
187 .flags
= IRQF_DISABLED
,
191 void __init
arch_init_irq(void)
195 for (i
= 0; i
< 5; i
++)
196 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER
+ (i
* IFXMIPS_ICU_OFFSET
));
200 for (i
= 2; i
<= 6; i
++)
201 setup_irq(i
, &cascade
);
203 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
205 printk(KERN_INFO
"Setting up vectored interrupts\n");
206 set_vi_handler(2, ifxmips_hw0_irqdispatch
);
207 set_vi_handler(3, ifxmips_hw1_irqdispatch
);
208 set_vi_handler(4, ifxmips_hw2_irqdispatch
);
209 set_vi_handler(5, ifxmips_hw3_irqdispatch
);
210 set_vi_handler(6, ifxmips_hw4_irqdispatch
);
211 set_vi_handler(7, ifxmips_hw5_irqdispatch
);
213 #endif /* CONFIG_CPU_MIPSR2_IRQ_VI */
215 for (i
= INT_NUM_IRQ0
; i
<= (INT_NUM_IRQ0
+ (5 * INT_NUM_IM_OFFSET
));
217 set_irq_chip_and_handler(i
, &ifxmips_irq_type
,
220 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
221 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
222 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
224 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
225 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
229 void __cpuinit
arch_fixup_c0_irqs(void)
231 /* FIXME: check for CPUID and only do fix for specific chips/versions */
232 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
233 cp0_perfcount_irq
= CP0_LEGACY_PERFCNT_IRQ
;