2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2005 Wu Qi Ming infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/module.h>
27 #include <asm/bootinfo.h>
29 #include <asm/irq_cpu.h>
32 #include <ifxmips_irq.h>
34 void ifxmips_disable_irq(unsigned int irq_nr
)
37 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
39 irq_nr
-= INT_NUM_IRQ0
;
40 for (i
= 0; i
<= 4; i
++) {
41 if (irq_nr
< INT_NUM_IM_OFFSET
) {
42 ifxmips_w32(ifxmips_r32(ifxmips_ier
) & ~(1 << irq_nr
),
46 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
47 irq_nr
-= INT_NUM_IM_OFFSET
;
50 EXPORT_SYMBOL(ifxmips_disable_irq
);
52 void ifxmips_mask_and_ack_irq(unsigned int irq_nr
)
55 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
56 u32
*ifxmips_isr
= IFXMIPS_ICU_IM0_ISR
;
58 irq_nr
-= INT_NUM_IRQ0
;
59 for (i
= 0; i
<= 4; i
++) {
60 if (irq_nr
< INT_NUM_IM_OFFSET
) {
61 ifxmips_w32(ifxmips_r32(ifxmips_ier
) & ~(1 << irq_nr
),
63 ifxmips_w32((1 << irq_nr
), ifxmips_isr
);
66 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
67 ifxmips_isr
+= IFXMIPS_ICU_OFFSET
;
68 irq_nr
-= INT_NUM_IM_OFFSET
;
71 EXPORT_SYMBOL(ifxmips_mask_and_ack_irq
);
73 void ifxmips_enable_irq(unsigned int irq_nr
)
76 u32
*ifxmips_ier
= IFXMIPS_ICU_IM0_IER
;
78 irq_nr
-= INT_NUM_IRQ0
;
79 for (i
= 0; i
<= 4; i
++) {
80 if (irq_nr
< INT_NUM_IM_OFFSET
) {
81 ifxmips_w32(ifxmips_r32(ifxmips_ier
) | (1 << irq_nr
),
85 ifxmips_ier
+= IFXMIPS_ICU_OFFSET
;
86 irq_nr
-= INT_NUM_IM_OFFSET
;
89 EXPORT_SYMBOL(ifxmips_enable_irq
);
91 static unsigned int ifxmips_startup_irq(unsigned int irq
)
93 ifxmips_enable_irq(irq
);
97 static void ifxmips_end_irq(unsigned int irq
)
99 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
100 ifxmips_enable_irq(irq
);
103 static struct hw_interrupt_type ifxmips_irq_type
= {
105 .startup
= ifxmips_startup_irq
,
106 .enable
= ifxmips_enable_irq
,
107 .disable
= ifxmips_disable_irq
,
108 .unmask
= ifxmips_enable_irq
,
109 .ack
= ifxmips_end_irq
,
110 .mask
= ifxmips_disable_irq
,
111 .mask_ack
= ifxmips_mask_and_ack_irq
,
112 .end
= ifxmips_end_irq
,
115 /* silicon bug causes only the msb set to 1 to be valid. all
116 other bits might be bogus */
117 static inline int ls1bit32(unsigned long x
)
129 void ifxmips_hw_irqdispatch(int module
)
133 irq
= ifxmips_r32(IFXMIPS_ICU_IM0_IOSR
+ (module
* IFXMIPS_ICU_OFFSET
));
137 /* we need to do this due to a silicon bug */
139 do_IRQ((int)irq
+ INT_NUM_IM0_IRL0
+ (INT_NUM_IM_OFFSET
* module
));
141 if ((irq
== 22) && (module
== 0))
142 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT
) | 0x10,
143 IFXMIPS_EBU_PCC_ISTAT
);
146 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
147 #define DEFINE_HWx_IRQDISPATCH(x) \
148 static void ifxmips_hw ## x ## _irqdispatch(void)\
150 ifxmips_hw_irqdispatch(x); \
152 static void ifxmips_hw5_irqdispatch(void)
154 do_IRQ(MIPS_CPU_TIMER_IRQ
);
156 DEFINE_HWx_IRQDISPATCH(0)
157 DEFINE_HWx_IRQDISPATCH(1)
158 DEFINE_HWx_IRQDISPATCH(2)
159 DEFINE_HWx_IRQDISPATCH(3)
160 DEFINE_HWx_IRQDISPATCH(4)
161 /*DEFINE_HWx_IRQDISPATCH(5)*/
162 #endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
164 asmlinkage
void plat_irq_dispatch(void)
166 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
169 if (pending
& CAUSEF_IP7
) {
170 do_IRQ(MIPS_CPU_TIMER_IRQ
);
173 for (i
= 0; i
< 5; i
++) {
174 if (pending
& (CAUSEF_IP2
<< i
)) {
175 ifxmips_hw_irqdispatch(i
);
180 printk(KERN_ALERT
"Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
186 static struct irqaction cascade
= {
187 .handler
= no_action
,
188 .flags
= IRQF_DISABLED
,
192 void __init
arch_init_irq(void)
196 for (i
= 0; i
< 5; i
++)
197 ifxmips_w32(0, IFXMIPS_ICU_IM0_IER
+ (i
* IFXMIPS_ICU_OFFSET
));
201 for (i
= 2; i
<= 6; i
++)
202 setup_irq(i
, &cascade
);
204 #ifdef CONFIG_CPU_MIPSR2_IRQ_VI
206 printk(KERN_INFO
"Setting up vectored interrupts\n");
207 set_vi_handler(2, ifxmips_hw0_irqdispatch
);
208 set_vi_handler(3, ifxmips_hw1_irqdispatch
);
209 set_vi_handler(4, ifxmips_hw2_irqdispatch
);
210 set_vi_handler(5, ifxmips_hw3_irqdispatch
);
211 set_vi_handler(6, ifxmips_hw4_irqdispatch
);
212 set_vi_handler(7, ifxmips_hw5_irqdispatch
);
214 #endif /* CONFIG_CPU_MIPSR2_IRQ_VI */
216 for (i
= INT_NUM_IRQ0
; i
<= (INT_NUM_IRQ0
+ (5 * INT_NUM_IM_OFFSET
));
218 set_irq_chip_and_handler(i
, &ifxmips_irq_type
,
221 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
222 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
223 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
225 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
226 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
230 void __cpuinit
arch_fixup_c0_irqs(void)
232 /* FIXME: check for CPUID and only do fix for specific chips/versions */
233 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
234 cp0_perfcount_irq
= CP0_LEGACY_PERFCNT_IRQ
;