1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/version.h>
4 #include <linux/types.h>
6 #include <linux/miscdevice.h>
7 #include <linux/init.h>
8 #include <linux/uaccess.h>
9 #include <linux/unistd.h>
10 #include <linux/errno.h>
11 #include <linux/interrupt.h>
14 #include <asm/div64.h>
16 #include <asm/ifxmips/ifxmips.h>
17 #include <asm/ifxmips/ifxmips_irq.h>
18 #include <asm/mach-ifxmips/cgu.h>
19 #include <asm/ifxmips/ifxmips_gptu.h>
20 #include <asm/ifxmips/ifxmips_pmu.h>
22 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
25 #define FIRST_TIMER TIMER1A
31 * GPTC divider is set or not.
33 #define GPTU_CLC_RMC_IS_SET 0
36 * Timer Interrupt (IRQ)
38 /* Must be adjusted when ICU driver is available */
39 #define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
44 #define GET_BITS(x, msb, lsb) \
45 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
46 #define SET_BITS(x, msb, lsb, value) \
47 (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
48 (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
51 * GPTU Register Mapping
53 #define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
54 #define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
55 #define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
56 #define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
57 #define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
58 #define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
59 #define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
60 #define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
61 #define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
62 #define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
65 * Clock Control Register
67 #define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
68 #define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
69 #define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
70 #define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
71 #define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
72 #define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
73 #define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
75 #define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
76 #define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
77 #define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
78 #define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
79 #define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
80 #define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
81 #define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
86 #define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
87 #define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
88 #define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
91 * Control Register of Timer/Counter nX
92 * n is the index of block (1 based index)
95 #define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
96 #define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
97 #define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
98 #define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
99 #define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
100 #define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
101 #define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
102 #define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
103 #define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
104 #define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
106 #define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
107 #define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
108 #define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
109 #define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
110 #define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
111 #define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
112 #define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
113 #define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
114 #define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
116 #define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
117 #define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
118 #define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
120 #define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
121 #define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
123 #define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
124 #define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
125 #define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
126 #define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
127 #define TIMER_FLAG_NONE_EDGE 0x0000
128 #define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
129 #define TIMER_FLAG_REAL 0x0000
130 #define TIMER_FLAG_INVERT 0x0040
131 #define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
132 #define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
133 #define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
134 #define TIMER_FLAG_CALLBACK_IN_HB 0x0200
135 #define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
136 #define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
138 struct timer_dev_timer
{
139 unsigned int f_irq_on
;
147 struct mutex gptu_mutex
;
148 unsigned int number_of_timers
;
149 unsigned int occupation
;
150 unsigned int f_gptu_on
;
151 struct timer_dev_timer timer
[MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2];
154 static int gptu_ioctl(struct inode
*, struct file
*, unsigned int, unsigned long);
155 static int gptu_open(struct inode
*, struct file
*);
156 static int gptu_release(struct inode
*, struct file
*);
158 static struct file_operations gptu_fops
= {
159 .owner
= THIS_MODULE
,
162 .release
= gptu_release
165 static struct miscdevice gptu_miscdev
= {
166 .minor
= MISC_DYNAMIC_MINOR
,
171 static struct timer_dev timer_dev
;
173 static irqreturn_t
timer_irq_handler(int irq
, void *p
)
177 struct timer_dev_timer
*dev_timer
= (struct timer_dev_timer
*)p
;
179 timer
= irq
- TIMER_INTERRUPT
;
180 if (timer
< timer_dev
.number_of_timers
181 && dev_timer
== &timer_dev
.timer
[timer
]) {
182 /* Clear interrupt. */
183 ifxmips_w32(1 << timer
, IFXMIPS_GPTU_IRNCR
);
185 /* Call user hanler or signal. */
186 flag
= dev_timer
->flag
;
188 || TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
) {
189 /* 16-bit timer or timer A of 32-bit timer */
190 switch (TIMER_FLAG_MASK_HANDLE(flag
)) {
191 case TIMER_FLAG_CALLBACK_IN_IRQ
:
192 case TIMER_FLAG_CALLBACK_IN_HB
:
194 (*(timer_callback
)dev_timer
->arg1
)(dev_timer
->arg2
);
196 case TIMER_FLAG_SIGNAL
:
197 send_sig((int)dev_timer
->arg2
, (struct task_struct
*)dev_timer
->arg1
, 0);
205 static inline void ifxmips_enable_gptu(void)
207 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT
);
209 /* Set divider as 1, disable write protection for SPEN, enable module. */
211 GPTU_CLC_SMC_SET(0x00) |
212 GPTU_CLC_RMC_SET(0x01) |
213 GPTU_CLC_FSOE_SET(0) |
214 GPTU_CLC_SBWE_SET(1) |
215 GPTU_CLC_EDIS_SET(0) |
216 GPTU_CLC_SPEN_SET(0) |
217 GPTU_CLC_DISR_SET(0);
220 static inline void ifxmips_disable_gptu(void)
222 ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN
);
223 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
225 /* Set divider as 0, enable write protection for SPEN, disable module. */
227 GPTU_CLC_SMC_SET(0x00) |
228 GPTU_CLC_RMC_SET(0x00) |
229 GPTU_CLC_FSOE_SET(0) |
230 GPTU_CLC_SBWE_SET(0) |
231 GPTU_CLC_EDIS_SET(0) |
232 GPTU_CLC_SPEN_SET(0) |
233 GPTU_CLC_DISR_SET(1);
235 ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT
);
238 int ifxmips_request_timer(unsigned int timer
, unsigned int flag
,
239 unsigned long value
, unsigned long arg1
, unsigned long arg2
)
242 unsigned int con_reg
, irnen_reg
;
245 if (timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
248 printk(KERN_INFO
"request_timer(%d, 0x%08X, %lu)...",
251 if (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
)
256 mutex_lock(&timer_dev
.gptu_mutex
);
261 if (timer
< FIRST_TIMER
) {
264 /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
265 unsigned int offset
= TIMER2A
;
268 * Pick up a free timer.
270 if (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
) {
278 timer
< offset
+ timer_dev
.number_of_timers
;
279 timer
+= shift
, mask
<<= shift
)
280 if (!(timer_dev
.occupation
& mask
)) {
281 timer_dev
.occupation
|= mask
;
284 if (timer
>= offset
+ timer_dev
.number_of_timers
) {
285 printk("failed![%d]\n", __LINE__
);
286 mutex_unlock(&timer_dev
.gptu_mutex
);
291 register unsigned int mask
;
294 * Check if the requested timer is free.
296 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
297 if ((timer_dev
.occupation
& mask
)) {
298 printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
299 __LINE__
, mask
, timer_dev
.occupation
);
300 mutex_unlock(&timer_dev
.gptu_mutex
);
303 timer_dev
.occupation
|= mask
;
309 * Prepare control register value.
311 switch (TIMER_FLAG_MASK_EDGE(flag
)) {
313 case TIMER_FLAG_NONE_EDGE
:
314 con_reg
= GPTU_CON_EDGE_SET(0x00);
316 case TIMER_FLAG_RISE_EDGE
:
317 con_reg
= GPTU_CON_EDGE_SET(0x01);
319 case TIMER_FLAG_FALL_EDGE
:
320 con_reg
= GPTU_CON_EDGE_SET(0x02);
322 case TIMER_FLAG_ANY_EDGE
:
323 con_reg
= GPTU_CON_EDGE_SET(0x03);
326 if (TIMER_FLAG_MASK_TYPE(flag
) == TIMER_FLAG_TIMER
)
328 TIMER_FLAG_MASK_SRC(flag
) ==
329 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET(1) :
330 GPTU_CON_SRC_EXT_SET(0);
333 TIMER_FLAG_MASK_SRC(flag
) ==
334 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET(1) :
335 GPTU_CON_SRC_EG_SET(0);
337 TIMER_FLAG_MASK_SYNC(flag
) ==
338 TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET(0) :
339 GPTU_CON_SYNC_SET(1);
341 TIMER_FLAG_MASK_INVERT(flag
) ==
342 TIMER_FLAG_REAL
? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
344 TIMER_FLAG_MASK_SIZE(flag
) ==
345 TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET(0) :
348 TIMER_FLAG_MASK_STOP(flag
) ==
349 TIMER_FLAG_ONCE
? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
351 TIMER_FLAG_MASK_TYPE(flag
) ==
352 TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET(0) :
355 TIMER_FLAG_MASK_DIR(flag
) ==
356 TIMER_FLAG_UP
? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
359 * Fill up running data.
361 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flag
;
362 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
= arg1
;
363 timer_dev
.timer
[timer
- FIRST_TIMER
].arg2
= arg2
;
364 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
365 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flag
;
368 * Enable GPTU module.
370 if (!timer_dev
.f_gptu_on
) {
371 ifxmips_enable_gptu();
372 timer_dev
.f_gptu_on
= 1;
378 if (TIMER_FLAG_MASK_HANDLE(flag
) != TIMER_FLAG_NO_HANDLE
) {
379 if (TIMER_FLAG_MASK_HANDLE(flag
) == TIMER_FLAG_SIGNAL
)
380 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
=
381 (unsigned long) find_task_by_vpid((int) arg1
);
383 irnen_reg
= 1 << (timer
- FIRST_TIMER
);
385 if (TIMER_FLAG_MASK_HANDLE(flag
) == TIMER_FLAG_SIGNAL
386 || (TIMER_FLAG_MASK_HANDLE(flag
) ==
387 TIMER_FLAG_CALLBACK_IN_IRQ
388 && timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
)) {
389 enable_irq(timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
390 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 1;
396 * Write config register, reload value and enable interrupt.
400 *IFXMIPS_GPTU_CON(n
, X
) = con_reg
;
401 *IFXMIPS_GPTU_RELOAD(n
, X
) = value
;
402 /* printk("reload value = %d\n", (u32)value); */
403 *IFXMIPS_GPTU_IRNEN
|= irnen_reg
;
405 mutex_unlock(&timer_dev
.gptu_mutex
);
406 printk("successful!\n");
409 EXPORT_SYMBOL(ifxmips_request_timer
);
411 int ifxmips_free_timer(unsigned int timer
)
417 if (!timer_dev
.f_gptu_on
)
420 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
423 mutex_lock(&timer_dev
.gptu_mutex
);
425 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
426 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
429 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
430 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
431 mutex_unlock(&timer_dev
.gptu_mutex
);
438 if (GPTU_CON_EN(n
, X
))
439 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_CEN_SET(1);
441 *IFXMIPS_GPTU_IRNEN
&= ~GPTU_IRNEN_TC_SET(n
, X
, 1);
442 *IFXMIPS_GPTU_IRNCR
|= GPTU_IRNCR_TC_SET(n
, X
, 1);
444 if (timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
) {
445 disable_irq(timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
446 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 0;
449 timer_dev
.occupation
&= ~mask
;
450 if (!timer_dev
.occupation
&& timer_dev
.f_gptu_on
) {
451 ifxmips_disable_gptu();
452 timer_dev
.f_gptu_on
= 0;
455 mutex_unlock(&timer_dev
.gptu_mutex
);
459 EXPORT_SYMBOL(ifxmips_free_timer
);
461 int ifxmips_start_timer(unsigned int timer
, int is_resume
)
467 if (!timer_dev
.f_gptu_on
)
470 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
473 mutex_lock(&timer_dev
.gptu_mutex
);
475 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
476 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
479 mask
= (TIMER_FLAG_MASK_SIZE(flag
) ==
480 TIMER_FLAG_16BIT
? 1 : 3) << timer
;
481 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
482 mutex_unlock(&timer_dev
.gptu_mutex
);
489 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_RL_SET(!is_resume
) | GPTU_RUN_SEN_SET(1);
491 mutex_unlock(&timer_dev
.gptu_mutex
);
495 EXPORT_SYMBOL(ifxmips_start_timer
);
497 int ifxmips_stop_timer(unsigned int timer
)
503 if (!timer_dev
.f_gptu_on
)
506 if (timer
< FIRST_TIMER
507 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
510 mutex_lock(&timer_dev
.gptu_mutex
);
512 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
513 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
516 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
517 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
518 mutex_unlock(&timer_dev
.gptu_mutex
);
525 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_CEN_SET(1);
527 mutex_unlock(&timer_dev
.gptu_mutex
);
531 EXPORT_SYMBOL(ifxmips_stop_timer
);
533 int ifxmips_reset_counter_flags(u32 timer
, u32 flags
)
536 unsigned int mask
, con_reg
;
539 if (!timer_dev
.f_gptu_on
)
542 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
545 mutex_lock(&timer_dev
.gptu_mutex
);
547 oflag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
548 if (TIMER_FLAG_MASK_SIZE(oflag
) != TIMER_FLAG_16BIT
)
551 mask
= (TIMER_FLAG_MASK_SIZE(oflag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
552 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
553 mutex_unlock(&timer_dev
.gptu_mutex
);
557 switch (TIMER_FLAG_MASK_EDGE(flags
)) {
559 case TIMER_FLAG_NONE_EDGE
:
560 con_reg
= GPTU_CON_EDGE_SET(0x00);
562 case TIMER_FLAG_RISE_EDGE
:
563 con_reg
= GPTU_CON_EDGE_SET(0x01);
565 case TIMER_FLAG_FALL_EDGE
:
566 con_reg
= GPTU_CON_EDGE_SET(0x02);
568 case TIMER_FLAG_ANY_EDGE
:
569 con_reg
= GPTU_CON_EDGE_SET(0x03);
572 if (TIMER_FLAG_MASK_TYPE(flags
) == TIMER_FLAG_TIMER
)
573 con_reg
|= TIMER_FLAG_MASK_SRC(flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
575 con_reg
|= TIMER_FLAG_MASK_SRC(flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
576 con_reg
|= TIMER_FLAG_MASK_SYNC(flags
) == TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
577 con_reg
|= TIMER_FLAG_MASK_INVERT(flags
) == TIMER_FLAG_REAL
? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
578 con_reg
|= TIMER_FLAG_MASK_SIZE(flags
) == TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
579 con_reg
|= TIMER_FLAG_MASK_STOP(flags
) == TIMER_FLAG_ONCE
? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
580 con_reg
|= TIMER_FLAG_MASK_TYPE(flags
) == TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
581 con_reg
|= TIMER_FLAG_MASK_DIR(flags
) == TIMER_FLAG_UP
? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
583 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flags
;
584 if (TIMER_FLAG_MASK_SIZE(flags
) != TIMER_FLAG_16BIT
)
585 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flags
;
590 *IFXMIPS_GPTU_CON(n
, X
) = con_reg
;
592 printk(KERN_INFO
"[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__
, timer
, oflag
, flags
, *IFXMIPS_GPTU_CON(n
, X
));
593 mutex_unlock(&timer_dev
.gptu_mutex
);
596 EXPORT_SYMBOL(ifxmips_reset_counter_flags
);
598 int ifxmips_get_count_value(unsigned int timer
, unsigned long *value
)
604 if (!timer_dev
.f_gptu_on
)
607 if (timer
< FIRST_TIMER
608 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
611 mutex_lock(&timer_dev
.gptu_mutex
);
613 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
614 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
617 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
618 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
619 mutex_unlock(&timer_dev
.gptu_mutex
);
626 *value
= *IFXMIPS_GPTU_COUNT(n
, X
);
628 mutex_unlock(&timer_dev
.gptu_mutex
);
632 EXPORT_SYMBOL(ifxmips_get_count_value
);
634 u32
ifxmips_cal_divider(unsigned long freq
)
636 u64 module_freq
, fpi
= cgu_get_fpi_bus_clock(2);
637 u32 clock_divider
= 1;
638 module_freq
= fpi
* 1000;
639 do_div(module_freq
, clock_divider
* freq
);
642 EXPORT_SYMBOL(ifxmips_cal_divider
);
644 int ifxmips_set_timer(unsigned int timer
, unsigned int freq
, int is_cyclic
,
645 int is_ext_src
, unsigned int handle_flag
, unsigned long arg1
,
648 unsigned long divider
;
651 divider
= ifxmips_cal_divider(freq
);
654 flag
= ((divider
& ~0xFFFF) ? TIMER_FLAG_32BIT
: TIMER_FLAG_16BIT
)
655 | (is_cyclic
? TIMER_FLAG_CYCLIC
: TIMER_FLAG_ONCE
)
656 | (is_ext_src
? TIMER_FLAG_EXT_SRC
: TIMER_FLAG_INT_SRC
)
657 | TIMER_FLAG_TIMER
| TIMER_FLAG_DOWN
658 | TIMER_FLAG_MASK_HANDLE(handle_flag
);
660 printk(KERN_INFO
"ifxmips_set_timer(%d, %d), divider = %lu\n",
661 timer
, freq
, divider
);
662 return ifxmips_request_timer(timer
, flag
, divider
, arg1
, arg2
);
664 EXPORT_SYMBOL(ifxmips_set_timer
);
666 int ifxmips_set_counter(unsigned int timer
, unsigned int flag
, u32 reload
,
667 unsigned long arg1
, unsigned long arg2
)
669 printk(KERN_INFO
"ifxmips_set_counter(%d, %#x, %d)\n", timer
, flag
, reload
);
670 return ifxmips_request_timer(timer
, flag
, reload
, arg1
, arg2
);
672 EXPORT_SYMBOL(ifxmips_set_counter
);
674 static int gptu_ioctl(struct inode
*inode
, struct file
*file
, unsigned int cmd
,
678 struct gptu_ioctl_param param
;
680 if (!access_ok(VERIFY_READ
, arg
, sizeof(struct gptu_ioctl_param
)))
682 copy_from_user(¶m
, (void *) arg
, sizeof(param
));
684 if ((((cmd
== GPTU_REQUEST_TIMER
|| cmd
== GPTU_SET_TIMER
685 || GPTU_SET_COUNTER
) && param
.timer
< 2)
686 || cmd
== GPTU_GET_COUNT_VALUE
|| cmd
== GPTU_CALCULATE_DIVIDER
)
687 && !access_ok(VERIFY_WRITE
, arg
,
688 sizeof(struct gptu_ioctl_param
)))
692 case GPTU_REQUEST_TIMER
:
693 ret
= ifxmips_request_timer(param
.timer
, param
.flag
, param
.value
,
694 (unsigned long) param
.pid
,
695 (unsigned long) param
.sig
);
697 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
698 timer
, &ret
, sizeof(&ret
));
702 case GPTU_FREE_TIMER
:
703 ret
= ifxmips_free_timer(param
.timer
);
705 case GPTU_START_TIMER
:
706 ret
= ifxmips_start_timer(param
.timer
, param
.flag
);
708 case GPTU_STOP_TIMER
:
709 ret
= ifxmips_stop_timer(param
.timer
);
711 case GPTU_GET_COUNT_VALUE
:
712 ret
= ifxmips_get_count_value(param
.timer
, ¶m
.value
);
714 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
716 sizeof(param
.value
));
718 case GPTU_CALCULATE_DIVIDER
:
719 param
.value
= ifxmips_cal_divider(param
.value
);
720 if (param
.value
== 0)
723 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
725 sizeof(param
.value
));
730 ret
= ifxmips_set_timer(param
.timer
, param
.value
,
731 TIMER_FLAG_MASK_STOP(param
.flag
) !=
732 TIMER_FLAG_ONCE
? 1 : 0,
733 TIMER_FLAG_MASK_SRC(param
.flag
) ==
734 TIMER_FLAG_EXT_SRC
? 1 : 0,
735 TIMER_FLAG_MASK_HANDLE(param
.flag
) ==
736 TIMER_FLAG_SIGNAL
? TIMER_FLAG_SIGNAL
:
737 TIMER_FLAG_NO_HANDLE
,
738 (unsigned long) param
.pid
,
739 (unsigned long) param
.sig
);
741 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
742 timer
, &ret
, sizeof(&ret
));
746 case GPTU_SET_COUNTER
:
747 ifxmips_set_counter(param
.timer
, param
.flag
, param
.value
, 0, 0);
749 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
750 timer
, &ret
, sizeof(&ret
));
761 static int gptu_open(struct inode
*inode
, struct file
*file
)
766 static int gptu_release(struct inode
*inode
, struct file
*file
)
771 int __init
ifxmips_gptu_init(void)
776 ifxmips_w32(0, IFXMIPS_GPTU_IRNEN
);
777 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
779 memset(&timer_dev
, 0, sizeof(timer_dev
));
780 mutex_init(&timer_dev
.gptu_mutex
);
782 ifxmips_enable_gptu();
783 timer_dev
.number_of_timers
= GPTU_ID_CFG
* 2;
784 ifxmips_disable_gptu();
785 if (timer_dev
.number_of_timers
> MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2)
786 timer_dev
.number_of_timers
= MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2;
787 printk(KERN_INFO
"gptu: totally %d 16-bit timers/counters\n", timer_dev
.number_of_timers
);
789 ret
= misc_register(&gptu_miscdev
);
791 printk(KERN_ERR
"gptu: can't misc_register, get error %d\n", -ret
);
794 printk(KERN_INFO
"gptu: misc_register on minor %d\n", gptu_miscdev
.minor
);
797 for (i
= 0; i
< timer_dev
.number_of_timers
; i
++) {
798 ret
= request_irq(TIMER_INTERRUPT
+ i
, timer_irq_handler
, IRQF_TIMER
, gptu_miscdev
.name
, &timer_dev
.timer
[i
]);
801 free_irq(TIMER_INTERRUPT
+ i
, &timer_dev
.timer
[i
]);
802 misc_deregister(&gptu_miscdev
);
803 printk(KERN_ERR
"gptu: failed in requesting irq (%d), get error %d\n", i
, -ret
);
806 timer_dev
.timer
[i
].irq
= TIMER_INTERRUPT
+ i
;
807 disable_irq(timer_dev
.timer
[i
].irq
);
808 printk(KERN_INFO
"gptu: succeeded to request irq %d\n", timer_dev
.timer
[i
].irq
);
815 void __exit
ifxmips_gptu_exit(void)
819 for (i
= 0; i
< timer_dev
.number_of_timers
; i
++) {
820 if (timer_dev
.timer
[i
].f_irq_on
)
821 disable_irq(timer_dev
.timer
[i
].irq
);
822 free_irq(timer_dev
.timer
[i
].irq
, &timer_dev
.timer
[i
]);
824 ifxmips_disable_gptu();
825 misc_deregister(&gptu_miscdev
);
828 module_init(ifxmips_gptu_init
);
829 module_exit(ifxmips_gptu_exit
);