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lots of ifxmips cleanups
[openwrt/openwrt.git] / target / linux / ifxmips / files / drivers / serial / ifxmips_asc.c
1 /*
2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (C) 2004 Infineon IFAP DC COM CPE
19 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
20 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
21 */
22
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/signal.h>
26 #include <linux/sched.h>
27 #include <linux/interrupt.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/fcntl.h>
33 #include <linux/ptrace.h>
34 #include <linux/ioport.h>
35 #include <linux/mm.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/circ_buf.h>
39 #include <linux/serial.h>
40 #include <linux/serial_core.h>
41 #include <linux/console.h>
42 #include <linux/sysrq.h>
43 #include <linux/irq.h>
44 #include <linux/platform_device.h>
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/uaccess.h>
48 #include <asm/bitops.h>
49 #include <asm/ifxmips/ifxmips.h>
50 #include <asm/ifxmips/ifxmips_irq.h>
51 #include <asm/ifxmips/ifxmips_serial.h>
52
53 #define PORT_IFXMIPSASC 111
54
55 #include <linux/serial_core.h>
56
57 #define UART_DUMMY_UER_RX 1
58
59 static void ifxmipsasc_tx_chars(struct uart_port *port);
60 extern void prom_printf(const char * fmt, ...);
61 static struct uart_port ifxmipsasc_port[2];
62 static struct uart_driver ifxmipsasc_reg;
63 extern unsigned int ifxmips_get_fpi_hz(void);
64
65 static void
66 ifxmipsasc_stop_tx(struct uart_port *port)
67 {
68 return;
69 }
70
71 static void
72 ifxmipsasc_start_tx(struct uart_port *port)
73 {
74 unsigned long flags;
75 local_irq_save(flags);
76 ifxmipsasc_tx_chars(port);
77 local_irq_restore(flags);
78 return;
79 }
80
81 static void
82 ifxmipsasc_stop_rx(struct uart_port *port)
83 {
84 ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
85 }
86
87 static void
88 ifxmipsasc_enable_ms(struct uart_port *port)
89 {
90 }
91
92 static void
93 ifxmipsasc_rx_chars(struct uart_port *port)
94 {
95 struct tty_struct *tty = port->info->tty;
96 unsigned int ch = 0, rsr = 0, fifocnt;
97
98 fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
99 while(fifocnt--)
100 {
101 u8 flag = TTY_NORMAL;
102 ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
103 rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
104 tty_flip_buffer_push(tty);
105 port->icount.rx++;
106
107 /*
108 * Note that the error handling code is
109 * out of the main execution path
110 */
111 if(rsr & ASCSTATE_ANY)
112 {
113 if(rsr & ASCSTATE_PE)
114 {
115 port->icount.parity++;
116 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
117 } else if(rsr & ASCSTATE_FE)
118 {
119 port->icount.frame++;
120 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
121 }
122 if(rsr & ASCSTATE_ROE)
123 {
124 port->icount.overrun++;
125 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
126 }
127
128 rsr &= port->read_status_mask;
129
130 if(rsr & ASCSTATE_PE)
131 flag = TTY_PARITY;
132 else if(rsr & ASCSTATE_FE)
133 flag = TTY_FRAME;
134 }
135
136 if((rsr & port->ignore_status_mask) == 0)
137 tty_insert_flip_char(tty, ch, flag);
138
139 if(rsr & ASCSTATE_ROE)
140 /*
141 * Overrun is special, since it's reported
142 * immediately, and doesn't affect the current
143 * character
144 */
145 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
146 }
147 if(ch != 0)
148 tty_flip_buffer_push(tty);
149 return;
150 }
151
152
153 static void
154 ifxmipsasc_tx_chars(struct uart_port *port)
155 {
156 struct circ_buf *xmit = &port->info->xmit;
157 if(uart_tx_stopped(port))
158 {
159 ifxmipsasc_stop_tx(port);
160 return;
161 }
162
163 while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
164 >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
165 {
166 if(port->x_char)
167 {
168 ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
169 port->icount.tx++;
170 port->x_char = 0;
171 continue;
172 }
173
174 if(uart_circ_empty(xmit))
175 break;
176
177 ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
178 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
179 port->icount.tx++;
180 }
181
182 if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
183 uart_write_wakeup(port);
184 }
185
186 static irqreturn_t
187 ifxmipsasc_tx_int(int irq, void *_port)
188 {
189 struct uart_port *port = (struct uart_port*) _port;
190 ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
191 ifxmipsasc_start_tx(port);
192 ifxmips_mask_and_ack_irq(irq);
193 return IRQ_HANDLED;
194 }
195
196 static irqreturn_t
197 ifxmipsasc_er_int(int irq, void *_port)
198 {
199 struct uart_port *port = (struct uart_port*) _port;
200 /* clear any pending interrupts */
201 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
202 ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
203 return IRQ_HANDLED;
204 }
205
206 static irqreturn_t
207 ifxmipsasc_rx_int(int irq, void *_port)
208 {
209 struct uart_port *port = (struct uart_port*)_port;
210 ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
211 ifxmipsasc_rx_chars((struct uart_port*)port);
212 ifxmips_mask_and_ack_irq(irq);
213 return IRQ_HANDLED;
214 }
215
216 static unsigned int
217 ifxmipsasc_tx_empty(struct uart_port *port)
218 {
219 int status;
220 status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
221 return status ? 0 : TIOCSER_TEMT;
222 }
223
224 static unsigned int
225 ifxmipsasc_get_mctrl(struct uart_port *port)
226 {
227 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
228 }
229
230 static void
231 ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
232 {
233 }
234
235 static void
236 ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
237 {
238 }
239
240 static int
241 ifxmipsasc_startup(struct uart_port *port)
242 {
243 unsigned long flags;
244 int retval;
245
246 port->uartclk = ifxmips_get_fpi_hz();
247
248 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
249 ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
250 ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
251 ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
252 ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
253 wmb ();
254 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
255
256 local_irq_save(flags);
257
258 retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
259 if(retval)
260 {
261 printk("failed to request ifxmipsasc_tx_int\n");
262 return retval;
263 }
264
265 retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
266 if(retval)
267 {
268 printk("failed to request ifxmipsasc_rx_int\n");
269 goto err1;
270 }
271
272 retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
273 if(retval)
274 {
275 printk("failed to request ifxmipsasc_er_int\n");
276 goto err2;
277 }
278
279 ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
280
281 local_irq_restore(flags);
282 return 0;
283
284 err2:
285 free_irq(port->irq + 2, port);
286 err1:
287 free_irq(port->irq, port);
288 local_irq_restore(flags);
289 return retval;
290 }
291
292 static void
293 ifxmipsasc_shutdown(struct uart_port *port)
294 {
295 free_irq(port->irq, port);
296 free_irq(port->irq + 2, port);
297 free_irq(port->irq + 3, port);
298
299 ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
300 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
301 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
302 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
303 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
304 }
305
306 static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
307 {
308 unsigned int cflag;
309 unsigned int iflag;
310 unsigned int quot;
311 unsigned int baud;
312 unsigned int con = 0;
313 unsigned long flags;
314
315 cflag = new->c_cflag;
316 iflag = new->c_iflag;
317
318 switch(cflag & CSIZE)
319 {
320 case CS7:
321 con = ASCCON_M_7ASYNC;
322 break;
323
324 case CS5:
325 case CS6:
326 default:
327 con = ASCCON_M_8ASYNC;
328 break;
329 }
330
331 if(cflag & CSTOPB)
332 con |= ASCCON_STP;
333
334 if(cflag & PARENB)
335 {
336 if(!(cflag & PARODD))
337 con &= ~ASCCON_ODD;
338 else
339 con |= ASCCON_ODD;
340 }
341
342 port->read_status_mask = ASCSTATE_ROE;
343 if(iflag & INPCK)
344 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
345
346 port->ignore_status_mask = 0;
347 if(iflag & IGNPAR)
348 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
349
350 if(iflag & IGNBRK)
351 {
352 /*
353 * If we're ignoring parity and break indicators,
354 * ignore overruns too (for real raw support).
355 */
356 if(iflag & IGNPAR)
357 port->ignore_status_mask |= ASCSTATE_ROE;
358 }
359
360 if((cflag & CREAD) == 0)
361 port->ignore_status_mask |= UART_DUMMY_UER_RX;
362
363 /* set error signals - framing, parity and overrun, enable receiver */
364 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
365
366 local_irq_save(flags);
367
368 /* set up CON */
369 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
370
371 /* Set baud rate - take a divider of 2 into account */
372 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
373 quot = uart_get_divisor(port, baud);
374 quot = quot / 2 - 1;
375
376 /* disable the baudrate generator */
377 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
378
379 /* make sure the fractional divider is off */
380 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
381
382 /* set up to use divisor of 2 */
383 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
384
385 /* now we can write the new baudrate into the register */
386 ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
387
388 /* turn the baudrate generator back on */
389 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
390
391 /* enable rx */
392 ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
393
394 local_irq_restore(flags);
395 }
396
397 static const char*
398 ifxmipsasc_type(struct uart_port *port)
399 {
400 if(port->type == PORT_IFXMIPSASC)
401 {
402 if(port->membase == IFXMIPS_ASC_BASE_ADDR)
403 return "asc0";
404 else
405 return "asc1";
406 } else {
407 return NULL;
408 }
409 }
410
411 static void
412 ifxmipsasc_release_port(struct uart_port *port)
413 {
414 }
415
416 static int
417 ifxmipsasc_request_port(struct uart_port *port)
418 {
419 return 0;
420 }
421
422 static void
423 ifxmipsasc_config_port(struct uart_port *port, int flags)
424 {
425 if(flags & UART_CONFIG_TYPE)
426 {
427 port->type = PORT_IFXMIPSASC;
428 ifxmipsasc_request_port(port);
429 }
430 }
431
432 static int
433 ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
434 {
435 int ret = 0;
436 if(ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
437 ret = -EINVAL;
438 if(ser->irq < 0 || ser->irq >= NR_IRQS)
439 ret = -EINVAL;
440 if(ser->baud_base < 9600)
441 ret = -EINVAL;
442 return ret;
443 }
444
445 static struct uart_ops ifxmipsasc_pops =
446 {
447 .tx_empty = ifxmipsasc_tx_empty,
448 .set_mctrl = ifxmipsasc_set_mctrl,
449 .get_mctrl = ifxmipsasc_get_mctrl,
450 .stop_tx = ifxmipsasc_stop_tx,
451 .start_tx = ifxmipsasc_start_tx,
452 .stop_rx = ifxmipsasc_stop_rx,
453 .enable_ms = ifxmipsasc_enable_ms,
454 .break_ctl = ifxmipsasc_break_ctl,
455 .startup = ifxmipsasc_startup,
456 .shutdown = ifxmipsasc_shutdown,
457 .set_termios = ifxmipsasc_set_termios,
458 .type = ifxmipsasc_type,
459 .release_port = ifxmipsasc_release_port,
460 .request_port = ifxmipsasc_request_port,
461 .config_port = ifxmipsasc_config_port,
462 .verify_port = ifxmipsasc_verify_port,
463 };
464
465 static struct uart_port ifxmipsasc_port[2] =
466 {
467 {
468 membase: (void *)IFXMIPS_ASC_BASE_ADDR,
469 mapbase: IFXMIPS_ASC_BASE_ADDR,
470 iotype: SERIAL_IO_MEM,
471 irq: IFXMIPSASC_TIR(0),
472 uartclk: 0,
473 fifosize: 16,
474 type: PORT_IFXMIPSASC,
475 ops: &ifxmipsasc_pops,
476 flags: ASYNC_BOOT_AUTOCONF,
477 line: 0
478 }, {
479 membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
480 mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
481 iotype: SERIAL_IO_MEM,
482 irq: IFXMIPSASC_TIR(1),
483 uartclk: 0,
484 fifosize: 16,
485 type: PORT_IFXMIPSASC,
486 ops: &ifxmipsasc_pops,
487 flags: ASYNC_BOOT_AUTOCONF,
488 line: 1
489 }
490 };
491
492 static void
493 ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
494 {
495 int port = co->index;
496 int i, fifocnt;
497 unsigned long flags;
498 local_irq_save(flags);
499 for(i = 0; i < count; i++)
500 {
501 do {
502 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
503 >> ASCFSTAT_TXFFLOFF;
504 } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
505
506 if(s[i] == '\0')
507 break;
508
509 if(s[i] == '\n')
510 {
511 ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
512 do {
513 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
514 >> ASCFSTAT_TXFFLOFF;
515 } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
516 }
517 ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
518 }
519
520 local_irq_restore(flags);
521 }
522
523 static int __init
524 ifxmipsasc_console_setup(struct console *co, char *options)
525 {
526 int port = co->index;
527 int baud = 115200;
528 int bits = 8;
529 int parity = 'n';
530 int flow = 'n';
531 ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
532 ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
533 if(options)
534 uart_parse_options(options, &baud, &parity, &bits, &flow);
535 return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
536 }
537
538 static struct console ifxmipsasc_console[2] =
539 {
540 {
541 name: "ttyS",
542 write: ifxmipsasc_console_write,
543 device: uart_console_device,
544 setup: ifxmipsasc_console_setup,
545 flags: CON_PRINTBUFFER,
546 index: 0,
547 data: &ifxmipsasc_reg,
548 }, {
549 name: "ttyS",
550 write: ifxmipsasc_console_write,
551 device: uart_console_device,
552 setup: ifxmipsasc_console_setup,
553 flags: CON_PRINTBUFFER,
554 index: 1,
555 data: &ifxmipsasc_reg,
556 }
557 };
558
559 static int __init
560 ifxmipsasc_console_init(void)
561 {
562 register_console(&ifxmipsasc_console[0]);
563 register_console(&ifxmipsasc_console[1]);
564 return 0;
565 }
566 console_initcall(ifxmipsasc_console_init);
567
568 static struct uart_driver ifxmipsasc_reg =
569 {
570 .owner = THIS_MODULE,
571 .driver_name = "serial",
572 .dev_name = "ttyS",
573 .major = TTY_MAJOR,
574 .minor = 64,
575 .nr = 2,
576 .cons = &ifxmipsasc_console[1],
577 };
578
579 int __init
580 ifxmipsasc_init(void)
581 {
582 int ret;
583 uart_register_driver(&ifxmipsasc_reg);
584 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
585 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
586 return 0;
587 }
588
589 void __exit
590 ifxmipsasc_exit(void)
591 {
592 uart_unregister_driver(&ifxmipsasc_reg);
593 }
594
595 module_init(ifxmipsasc_init);
596 module_exit(ifxmipsasc_exit);
597
598 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
599 MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
600 MODULE_LICENSE("GPL");
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