1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/version.h>
4 #include <linux/types.h>
6 #include <linux/miscdevice.h>
7 #include <linux/init.h>
8 #include <linux/uaccess.h>
9 #include <linux/unistd.h>
10 #include <linux/errno.h>
11 #include <linux/interrupt.h>
12 #include <linux/sched.h>
15 #include <asm/div64.h>
18 #include <ifxmips_irq.h>
19 #include <ifxmips_cgu.h>
20 #include <ifxmips_gptu.h>
21 #include <ifxmips_pmu.h>
23 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
26 #define FIRST_TIMER TIMER1A
32 * GPTC divider is set or not.
34 #define GPTU_CLC_RMC_IS_SET 0
37 * Timer Interrupt (IRQ)
39 /* Must be adjusted when ICU driver is available */
40 #define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
45 #define GET_BITS(x, msb, lsb) \
46 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
47 #define SET_BITS(x, msb, lsb, value) \
48 (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
49 (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
52 * GPTU Register Mapping
54 #define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
55 #define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
56 #define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
57 #define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
58 #define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
59 #define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
60 #define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
61 #define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
62 #define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
63 #define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
66 * Clock Control Register
68 #define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
69 #define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
70 #define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
71 #define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
72 #define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
73 #define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
74 #define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
76 #define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
77 #define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
78 #define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
79 #define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
80 #define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
81 #define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
82 #define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
87 #define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
88 #define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
89 #define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
92 * Control Register of Timer/Counter nX
93 * n is the index of block (1 based index)
96 #define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
97 #define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
98 #define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
99 #define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
100 #define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
101 #define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
102 #define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
103 #define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
104 #define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
105 #define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
107 #define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
108 #define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
109 #define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
110 #define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
111 #define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
112 #define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
113 #define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
114 #define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
115 #define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
117 #define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
118 #define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
119 #define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
121 #define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
122 #define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
124 #define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
125 #define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
126 #define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
127 #define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
128 #define TIMER_FLAG_NONE_EDGE 0x0000
129 #define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
130 #define TIMER_FLAG_REAL 0x0000
131 #define TIMER_FLAG_INVERT 0x0040
132 #define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
133 #define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
134 #define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
135 #define TIMER_FLAG_CALLBACK_IN_HB 0x0200
136 #define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
137 #define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
139 struct timer_dev_timer
{
140 unsigned int f_irq_on
;
148 struct mutex gptu_mutex
;
149 unsigned int number_of_timers
;
150 unsigned int occupation
;
151 unsigned int f_gptu_on
;
152 struct timer_dev_timer timer
[MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2];
155 static int gptu_ioctl(struct inode
*, struct file
*, unsigned int, unsigned long);
156 static int gptu_open(struct inode
*, struct file
*);
157 static int gptu_release(struct inode
*, struct file
*);
159 static struct file_operations gptu_fops
= {
160 .owner
= THIS_MODULE
,
163 .release
= gptu_release
166 static struct miscdevice gptu_miscdev
= {
167 .minor
= MISC_DYNAMIC_MINOR
,
172 static struct timer_dev timer_dev
;
174 static irqreturn_t
timer_irq_handler(int irq
, void *p
)
178 struct timer_dev_timer
*dev_timer
= (struct timer_dev_timer
*)p
;
180 timer
= irq
- TIMER_INTERRUPT
;
181 if (timer
< timer_dev
.number_of_timers
182 && dev_timer
== &timer_dev
.timer
[timer
]) {
183 /* Clear interrupt. */
184 ifxmips_w32(1 << timer
, IFXMIPS_GPTU_IRNCR
);
186 /* Call user hanler or signal. */
187 flag
= dev_timer
->flag
;
189 || TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
) {
190 /* 16-bit timer or timer A of 32-bit timer */
191 switch (TIMER_FLAG_MASK_HANDLE(flag
)) {
192 case TIMER_FLAG_CALLBACK_IN_IRQ
:
193 case TIMER_FLAG_CALLBACK_IN_HB
:
195 (*(timer_callback
)dev_timer
->arg1
)(dev_timer
->arg2
);
197 case TIMER_FLAG_SIGNAL
:
198 send_sig((int)dev_timer
->arg2
, (struct task_struct
*)dev_timer
->arg1
, 0);
206 static inline void ifxmips_enable_gptu(void)
208 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT
);
210 /* Set divider as 1, disable write protection for SPEN, enable module. */
212 GPTU_CLC_SMC_SET(0x00) |
213 GPTU_CLC_RMC_SET(0x01) |
214 GPTU_CLC_FSOE_SET(0) |
215 GPTU_CLC_SBWE_SET(1) |
216 GPTU_CLC_EDIS_SET(0) |
217 GPTU_CLC_SPEN_SET(0) |
218 GPTU_CLC_DISR_SET(0);
221 static inline void ifxmips_disable_gptu(void)
223 ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN
);
224 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
226 /* Set divider as 0, enable write protection for SPEN, disable module. */
228 GPTU_CLC_SMC_SET(0x00) |
229 GPTU_CLC_RMC_SET(0x00) |
230 GPTU_CLC_FSOE_SET(0) |
231 GPTU_CLC_SBWE_SET(0) |
232 GPTU_CLC_EDIS_SET(0) |
233 GPTU_CLC_SPEN_SET(0) |
234 GPTU_CLC_DISR_SET(1);
236 ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT
);
239 int ifxmips_request_timer(unsigned int timer
, unsigned int flag
,
240 unsigned long value
, unsigned long arg1
, unsigned long arg2
)
243 unsigned int con_reg
, irnen_reg
;
246 if (timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
249 printk(KERN_INFO
"request_timer(%d, 0x%08X, %lu)...",
252 if (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
)
257 mutex_lock(&timer_dev
.gptu_mutex
);
262 if (timer
< FIRST_TIMER
) {
265 /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
266 unsigned int offset
= TIMER2A
;
269 * Pick up a free timer.
271 if (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
) {
279 timer
< offset
+ timer_dev
.number_of_timers
;
280 timer
+= shift
, mask
<<= shift
)
281 if (!(timer_dev
.occupation
& mask
)) {
282 timer_dev
.occupation
|= mask
;
285 if (timer
>= offset
+ timer_dev
.number_of_timers
) {
286 printk("failed![%d]\n", __LINE__
);
287 mutex_unlock(&timer_dev
.gptu_mutex
);
292 register unsigned int mask
;
295 * Check if the requested timer is free.
297 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
298 if ((timer_dev
.occupation
& mask
)) {
299 printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
300 __LINE__
, mask
, timer_dev
.occupation
);
301 mutex_unlock(&timer_dev
.gptu_mutex
);
304 timer_dev
.occupation
|= mask
;
310 * Prepare control register value.
312 switch (TIMER_FLAG_MASK_EDGE(flag
)) {
314 case TIMER_FLAG_NONE_EDGE
:
315 con_reg
= GPTU_CON_EDGE_SET(0x00);
317 case TIMER_FLAG_RISE_EDGE
:
318 con_reg
= GPTU_CON_EDGE_SET(0x01);
320 case TIMER_FLAG_FALL_EDGE
:
321 con_reg
= GPTU_CON_EDGE_SET(0x02);
323 case TIMER_FLAG_ANY_EDGE
:
324 con_reg
= GPTU_CON_EDGE_SET(0x03);
327 if (TIMER_FLAG_MASK_TYPE(flag
) == TIMER_FLAG_TIMER
)
329 TIMER_FLAG_MASK_SRC(flag
) ==
330 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET(1) :
331 GPTU_CON_SRC_EXT_SET(0);
334 TIMER_FLAG_MASK_SRC(flag
) ==
335 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET(1) :
336 GPTU_CON_SRC_EG_SET(0);
338 TIMER_FLAG_MASK_SYNC(flag
) ==
339 TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET(0) :
340 GPTU_CON_SYNC_SET(1);
342 TIMER_FLAG_MASK_INVERT(flag
) ==
343 TIMER_FLAG_REAL
? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
345 TIMER_FLAG_MASK_SIZE(flag
) ==
346 TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET(0) :
349 TIMER_FLAG_MASK_STOP(flag
) ==
350 TIMER_FLAG_ONCE
? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
352 TIMER_FLAG_MASK_TYPE(flag
) ==
353 TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET(0) :
356 TIMER_FLAG_MASK_DIR(flag
) ==
357 TIMER_FLAG_UP
? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
360 * Fill up running data.
362 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flag
;
363 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
= arg1
;
364 timer_dev
.timer
[timer
- FIRST_TIMER
].arg2
= arg2
;
365 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
366 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flag
;
369 * Enable GPTU module.
371 if (!timer_dev
.f_gptu_on
) {
372 ifxmips_enable_gptu();
373 timer_dev
.f_gptu_on
= 1;
379 if (TIMER_FLAG_MASK_HANDLE(flag
) != TIMER_FLAG_NO_HANDLE
) {
380 if (TIMER_FLAG_MASK_HANDLE(flag
) == TIMER_FLAG_SIGNAL
)
381 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
=
382 (unsigned long) find_task_by_vpid((int) arg1
);
384 irnen_reg
= 1 << (timer
- FIRST_TIMER
);
386 if (TIMER_FLAG_MASK_HANDLE(flag
) == TIMER_FLAG_SIGNAL
387 || (TIMER_FLAG_MASK_HANDLE(flag
) ==
388 TIMER_FLAG_CALLBACK_IN_IRQ
389 && timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
)) {
390 enable_irq(timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
391 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 1;
397 * Write config register, reload value and enable interrupt.
401 *IFXMIPS_GPTU_CON(n
, X
) = con_reg
;
402 *IFXMIPS_GPTU_RELOAD(n
, X
) = value
;
403 /* printk("reload value = %d\n", (u32)value); */
404 *IFXMIPS_GPTU_IRNEN
|= irnen_reg
;
406 mutex_unlock(&timer_dev
.gptu_mutex
);
407 printk("successful!\n");
410 EXPORT_SYMBOL(ifxmips_request_timer
);
412 int ifxmips_free_timer(unsigned int timer
)
418 if (!timer_dev
.f_gptu_on
)
421 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
424 mutex_lock(&timer_dev
.gptu_mutex
);
426 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
427 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
430 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
431 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
432 mutex_unlock(&timer_dev
.gptu_mutex
);
439 if (GPTU_CON_EN(n
, X
))
440 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_CEN_SET(1);
442 *IFXMIPS_GPTU_IRNEN
&= ~GPTU_IRNEN_TC_SET(n
, X
, 1);
443 *IFXMIPS_GPTU_IRNCR
|= GPTU_IRNCR_TC_SET(n
, X
, 1);
445 if (timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
) {
446 disable_irq(timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
447 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 0;
450 timer_dev
.occupation
&= ~mask
;
451 if (!timer_dev
.occupation
&& timer_dev
.f_gptu_on
) {
452 ifxmips_disable_gptu();
453 timer_dev
.f_gptu_on
= 0;
456 mutex_unlock(&timer_dev
.gptu_mutex
);
460 EXPORT_SYMBOL(ifxmips_free_timer
);
462 int ifxmips_start_timer(unsigned int timer
, int is_resume
)
468 if (!timer_dev
.f_gptu_on
)
471 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
474 mutex_lock(&timer_dev
.gptu_mutex
);
476 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
477 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
480 mask
= (TIMER_FLAG_MASK_SIZE(flag
) ==
481 TIMER_FLAG_16BIT
? 1 : 3) << timer
;
482 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
483 mutex_unlock(&timer_dev
.gptu_mutex
);
490 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_RL_SET(!is_resume
) | GPTU_RUN_SEN_SET(1);
492 mutex_unlock(&timer_dev
.gptu_mutex
);
496 EXPORT_SYMBOL(ifxmips_start_timer
);
498 int ifxmips_stop_timer(unsigned int timer
)
504 if (!timer_dev
.f_gptu_on
)
507 if (timer
< FIRST_TIMER
508 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
511 mutex_lock(&timer_dev
.gptu_mutex
);
513 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
514 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
517 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
518 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
519 mutex_unlock(&timer_dev
.gptu_mutex
);
526 *IFXMIPS_GPTU_RUN(n
, X
) = GPTU_RUN_CEN_SET(1);
528 mutex_unlock(&timer_dev
.gptu_mutex
);
532 EXPORT_SYMBOL(ifxmips_stop_timer
);
534 int ifxmips_reset_counter_flags(u32 timer
, u32 flags
)
537 unsigned int mask
, con_reg
;
540 if (!timer_dev
.f_gptu_on
)
543 if (timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
546 mutex_lock(&timer_dev
.gptu_mutex
);
548 oflag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
549 if (TIMER_FLAG_MASK_SIZE(oflag
) != TIMER_FLAG_16BIT
)
552 mask
= (TIMER_FLAG_MASK_SIZE(oflag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
553 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
554 mutex_unlock(&timer_dev
.gptu_mutex
);
558 switch (TIMER_FLAG_MASK_EDGE(flags
)) {
560 case TIMER_FLAG_NONE_EDGE
:
561 con_reg
= GPTU_CON_EDGE_SET(0x00);
563 case TIMER_FLAG_RISE_EDGE
:
564 con_reg
= GPTU_CON_EDGE_SET(0x01);
566 case TIMER_FLAG_FALL_EDGE
:
567 con_reg
= GPTU_CON_EDGE_SET(0x02);
569 case TIMER_FLAG_ANY_EDGE
:
570 con_reg
= GPTU_CON_EDGE_SET(0x03);
573 if (TIMER_FLAG_MASK_TYPE(flags
) == TIMER_FLAG_TIMER
)
574 con_reg
|= TIMER_FLAG_MASK_SRC(flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
576 con_reg
|= TIMER_FLAG_MASK_SRC(flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
577 con_reg
|= TIMER_FLAG_MASK_SYNC(flags
) == TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
578 con_reg
|= TIMER_FLAG_MASK_INVERT(flags
) == TIMER_FLAG_REAL
? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
579 con_reg
|= TIMER_FLAG_MASK_SIZE(flags
) == TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
580 con_reg
|= TIMER_FLAG_MASK_STOP(flags
) == TIMER_FLAG_ONCE
? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
581 con_reg
|= TIMER_FLAG_MASK_TYPE(flags
) == TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
582 con_reg
|= TIMER_FLAG_MASK_DIR(flags
) == TIMER_FLAG_UP
? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
584 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flags
;
585 if (TIMER_FLAG_MASK_SIZE(flags
) != TIMER_FLAG_16BIT
)
586 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flags
;
591 *IFXMIPS_GPTU_CON(n
, X
) = con_reg
;
593 printk(KERN_INFO
"[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__
, timer
, oflag
, flags
, *IFXMIPS_GPTU_CON(n
, X
));
594 mutex_unlock(&timer_dev
.gptu_mutex
);
597 EXPORT_SYMBOL(ifxmips_reset_counter_flags
);
599 int ifxmips_get_count_value(unsigned int timer
, unsigned long *value
)
605 if (!timer_dev
.f_gptu_on
)
608 if (timer
< FIRST_TIMER
609 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
612 mutex_lock(&timer_dev
.gptu_mutex
);
614 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
615 if (TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
618 mask
= (TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
619 if (((timer_dev
.occupation
& mask
) ^ mask
)) {
620 mutex_unlock(&timer_dev
.gptu_mutex
);
627 *value
= *IFXMIPS_GPTU_COUNT(n
, X
);
629 mutex_unlock(&timer_dev
.gptu_mutex
);
633 EXPORT_SYMBOL(ifxmips_get_count_value
);
635 u32
ifxmips_cal_divider(unsigned long freq
)
637 u64 module_freq
, fpi
= cgu_get_fpi_bus_clock(2);
638 u32 clock_divider
= 1;
639 module_freq
= fpi
* 1000;
640 do_div(module_freq
, clock_divider
* freq
);
643 EXPORT_SYMBOL(ifxmips_cal_divider
);
645 int ifxmips_set_timer(unsigned int timer
, unsigned int freq
, int is_cyclic
,
646 int is_ext_src
, unsigned int handle_flag
, unsigned long arg1
,
649 unsigned long divider
;
652 divider
= ifxmips_cal_divider(freq
);
655 flag
= ((divider
& ~0xFFFF) ? TIMER_FLAG_32BIT
: TIMER_FLAG_16BIT
)
656 | (is_cyclic
? TIMER_FLAG_CYCLIC
: TIMER_FLAG_ONCE
)
657 | (is_ext_src
? TIMER_FLAG_EXT_SRC
: TIMER_FLAG_INT_SRC
)
658 | TIMER_FLAG_TIMER
| TIMER_FLAG_DOWN
659 | TIMER_FLAG_MASK_HANDLE(handle_flag
);
661 printk(KERN_INFO
"ifxmips_set_timer(%d, %d), divider = %lu\n",
662 timer
, freq
, divider
);
663 return ifxmips_request_timer(timer
, flag
, divider
, arg1
, arg2
);
665 EXPORT_SYMBOL(ifxmips_set_timer
);
667 int ifxmips_set_counter(unsigned int timer
, unsigned int flag
, u32 reload
,
668 unsigned long arg1
, unsigned long arg2
)
670 printk(KERN_INFO
"ifxmips_set_counter(%d, %#x, %d)\n", timer
, flag
, reload
);
671 return ifxmips_request_timer(timer
, flag
, reload
, arg1
, arg2
);
673 EXPORT_SYMBOL(ifxmips_set_counter
);
675 static int gptu_ioctl(struct inode
*inode
, struct file
*file
, unsigned int cmd
,
679 struct gptu_ioctl_param param
;
681 if (!access_ok(VERIFY_READ
, arg
, sizeof(struct gptu_ioctl_param
)))
683 copy_from_user(¶m
, (void *) arg
, sizeof(param
));
685 if ((((cmd
== GPTU_REQUEST_TIMER
|| cmd
== GPTU_SET_TIMER
686 || GPTU_SET_COUNTER
) && param
.timer
< 2)
687 || cmd
== GPTU_GET_COUNT_VALUE
|| cmd
== GPTU_CALCULATE_DIVIDER
)
688 && !access_ok(VERIFY_WRITE
, arg
,
689 sizeof(struct gptu_ioctl_param
)))
693 case GPTU_REQUEST_TIMER
:
694 ret
= ifxmips_request_timer(param
.timer
, param
.flag
, param
.value
,
695 (unsigned long) param
.pid
,
696 (unsigned long) param
.sig
);
698 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
699 timer
, &ret
, sizeof(&ret
));
703 case GPTU_FREE_TIMER
:
704 ret
= ifxmips_free_timer(param
.timer
);
706 case GPTU_START_TIMER
:
707 ret
= ifxmips_start_timer(param
.timer
, param
.flag
);
709 case GPTU_STOP_TIMER
:
710 ret
= ifxmips_stop_timer(param
.timer
);
712 case GPTU_GET_COUNT_VALUE
:
713 ret
= ifxmips_get_count_value(param
.timer
, ¶m
.value
);
715 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
717 sizeof(param
.value
));
719 case GPTU_CALCULATE_DIVIDER
:
720 param
.value
= ifxmips_cal_divider(param
.value
);
721 if (param
.value
== 0)
724 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
726 sizeof(param
.value
));
731 ret
= ifxmips_set_timer(param
.timer
, param
.value
,
732 TIMER_FLAG_MASK_STOP(param
.flag
) !=
733 TIMER_FLAG_ONCE
? 1 : 0,
734 TIMER_FLAG_MASK_SRC(param
.flag
) ==
735 TIMER_FLAG_EXT_SRC
? 1 : 0,
736 TIMER_FLAG_MASK_HANDLE(param
.flag
) ==
737 TIMER_FLAG_SIGNAL
? TIMER_FLAG_SIGNAL
:
738 TIMER_FLAG_NO_HANDLE
,
739 (unsigned long) param
.pid
,
740 (unsigned long) param
.sig
);
742 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
743 timer
, &ret
, sizeof(&ret
));
747 case GPTU_SET_COUNTER
:
748 ifxmips_set_counter(param
.timer
, param
.flag
, param
.value
, 0, 0);
750 copy_to_user(&((struct gptu_ioctl_param
*) arg
)->
751 timer
, &ret
, sizeof(&ret
));
762 static int gptu_open(struct inode
*inode
, struct file
*file
)
767 static int gptu_release(struct inode
*inode
, struct file
*file
)
772 int __init
ifxmips_gptu_init(void)
777 ifxmips_w32(0, IFXMIPS_GPTU_IRNEN
);
778 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
780 memset(&timer_dev
, 0, sizeof(timer_dev
));
781 mutex_init(&timer_dev
.gptu_mutex
);
783 ifxmips_enable_gptu();
784 timer_dev
.number_of_timers
= GPTU_ID_CFG
* 2;
785 ifxmips_disable_gptu();
786 if (timer_dev
.number_of_timers
> MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2)
787 timer_dev
.number_of_timers
= MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2;
788 printk(KERN_INFO
"gptu: totally %d 16-bit timers/counters\n", timer_dev
.number_of_timers
);
790 ret
= misc_register(&gptu_miscdev
);
792 printk(KERN_ERR
"gptu: can't misc_register, get error %d\n", -ret
);
795 printk(KERN_INFO
"gptu: misc_register on minor %d\n", gptu_miscdev
.minor
);
798 for (i
= 0; i
< timer_dev
.number_of_timers
; i
++) {
799 ret
= request_irq(TIMER_INTERRUPT
+ i
, timer_irq_handler
, IRQF_TIMER
, gptu_miscdev
.name
, &timer_dev
.timer
[i
]);
802 free_irq(TIMER_INTERRUPT
+ i
, &timer_dev
.timer
[i
]);
803 misc_deregister(&gptu_miscdev
);
804 printk(KERN_ERR
"gptu: failed in requesting irq (%d), get error %d\n", i
, -ret
);
807 timer_dev
.timer
[i
].irq
= TIMER_INTERRUPT
+ i
;
808 disable_irq(timer_dev
.timer
[i
].irq
);
809 printk(KERN_INFO
"gptu: succeeded to request irq %d\n", timer_dev
.timer
[i
].irq
);
816 void __exit
ifxmips_gptu_exit(void)
820 for (i
= 0; i
< timer_dev
.number_of_timers
; i
++) {
821 if (timer_dev
.timer
[i
].f_irq_on
)
822 disable_irq(timer_dev
.timer
[i
].irq
);
823 free_irq(timer_dev
.timer
[i
].irq
, &timer_dev
.timer
[i
]);
825 ifxmips_disable_gptu();
826 misc_deregister(&gptu_miscdev
);
829 module_init(ifxmips_gptu_init
);
830 module_exit(ifxmips_gptu_exit
);