1 Author: Tim Harvey <tharvey@gateworks.com>
2 Date: Thu May 15 00:29:18 2014 -0700
4 net: igb: add phy read/write functions that accept phy addr
6 Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
7 The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
12 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c
13 +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
14 @@ -2142,7 +2142,7 @@ static s32 igb_read_phy_reg_82580(struct
18 - ret_val = igb_read_phy_reg_mdic(hw, offset, data);
19 + ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
21 hw->phy.ops.release(hw);
23 @@ -2167,7 +2167,7 @@ static s32 igb_write_phy_reg_82580(struc
27 - ret_val = igb_write_phy_reg_mdic(hw, offset, data);
28 + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
30 hw->phy.ops.release(hw);
32 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c
33 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
34 @@ -136,9 +136,8 @@ out:
35 * Reads the MDI control regsiter in the PHY at offset and stores the
36 * information read to data.
38 -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
39 +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
41 - struct e1000_phy_info *phy = &hw->phy;
42 u32 i, mdicnfg, mdic = 0;
45 @@ -157,14 +156,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
47 mdicnfg = rd32(E1000_MDICNFG);
48 mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
49 - mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
50 + mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
51 wr32(E1000_MDICNFG, mdicnfg);
52 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
53 (E1000_MDIC_OP_READ));
56 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
57 - (phy->addr << E1000_MDIC_PHY_SHIFT) |
58 + (addr << E1000_MDIC_PHY_SHIFT) |
59 (E1000_MDIC_OP_READ));
62 @@ -218,9 +217,8 @@ out:
64 * Writes data to MDI control register in the PHY at offset.
66 -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
67 +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
69 - struct e1000_phy_info *phy = &hw->phy;
70 u32 i, mdicnfg, mdic = 0;
73 @@ -239,7 +237,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
75 mdicnfg = rd32(E1000_MDICNFG);
76 mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
77 - mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
78 + mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
79 wr32(E1000_MDICNFG, mdicnfg);
81 (offset << E1000_MDIC_REG_SHIFT) |
82 @@ -248,7 +246,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
85 (offset << E1000_MDIC_REG_SHIFT) |
86 - (phy->addr << E1000_MDIC_PHY_SHIFT) |
87 + (addr << E1000_MDIC_PHY_SHIFT) |
88 (E1000_MDIC_OP_WRITE));
91 @@ -539,7 +537,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
94 if (offset > MAX_PHY_MULTI_PAGE_REG) {
95 - ret_val = igb_write_phy_reg_mdic(hw,
96 + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
97 IGP01E1000_PHY_PAGE_SELECT,
100 @@ -548,8 +546,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
104 - ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
106 + ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
107 + MAX_PHY_REG_ADDRESS & offset, data);
109 hw->phy.ops.release(hw);
111 @@ -578,7 +576,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
114 if (offset > MAX_PHY_MULTI_PAGE_REG) {
115 - ret_val = igb_write_phy_reg_mdic(hw,
116 + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
117 IGP01E1000_PHY_PAGE_SELECT,
120 @@ -587,8 +585,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
124 - ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
126 + ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
127 + MAX_PHY_REG_ADDRESS & offset, data);
129 hw->phy.ops.release(hw);
131 @@ -2554,8 +2552,9 @@ out:
135 - * igb_write_phy_reg_gs40g - Write GS40G PHY register
136 + * igb_write_reg_gs40g - Write GS40G PHY register
137 * @hw: pointer to the HW structure
138 + * @addr: phy address to write to
139 * @offset: lower half is register offset to write to
140 * upper half is page to use.
141 * @data: data to write at register offset
142 @@ -2563,7 +2562,7 @@ out:
143 * Acquires semaphore, if necessary, then writes the data to PHY register
144 * at the offset. Release any acquired semaphores before exiting.
146 -s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
147 +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
150 u16 page = offset >> GS40G_PAGE_SHIFT;
151 @@ -2573,10 +2572,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
155 - ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
156 + ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
159 - ret_val = igb_write_phy_reg_mdic(hw, offset, data);
160 + ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
163 hw->phy.ops.release(hw);
164 @@ -2584,8 +2583,24 @@ release:
168 - * igb_read_phy_reg_gs40g - Read GS40G PHY register
169 + * igb_write_phy_reg_gs40g - Write GS40G PHY register
170 + * @hw: pointer to the HW structure
171 + * @offset: lower half is register offset to write to
172 + * upper half is page to use.
173 + * @data: data to write at register offset
175 + * Acquires semaphore, if necessary, then writes the data to PHY register
176 + * at the offset. Release any acquired semaphores before exiting.
178 +s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
180 + return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
184 + * igb_read_reg_gs40g - Read GS40G PHY register
185 * @hw: pointer to the HW structure
186 + * @addr: phy address to read from
187 * @offset: lower half is register offset to read to
188 * upper half is page to use.
189 * @data: data to read at register offset
190 @@ -2593,7 +2608,7 @@ release:
191 * Acquires semaphore, if necessary, then reads the data in the PHY register
192 * at the offset. Release any acquired semaphores before exiting.
194 -s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
195 +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
198 u16 page = offset >> GS40G_PAGE_SHIFT;
199 @@ -2603,10 +2618,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
203 - ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
204 + ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
207 - ret_val = igb_read_phy_reg_mdic(hw, offset, data);
208 + ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
211 hw->phy.ops.release(hw);
212 @@ -2614,6 +2629,21 @@ release:
216 + * igb_read_phy_reg_gs40g - Read GS40G PHY register
217 + * @hw: pointer to the HW structure
218 + * @offset: lower half is register offset to read to
219 + * upper half is page to use.
220 + * @data: data to read at register offset
222 + * Acquires semaphore, if necessary, then reads the data in the PHY register
223 + * at the offset. Release any acquired semaphores before exiting.
225 +s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
227 + return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
231 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
232 * @hw: pointer to the HW structure
234 --- a/drivers/net/ethernet/intel/igb/e1000_phy.h
235 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
236 @@ -65,8 +65,8 @@ s32 igb_phy_has_link(struct e1000_hw *h
237 void igb_power_up_phy_copper(struct e1000_hw *hw);
238 void igb_power_down_phy_copper(struct e1000_hw *hw);
239 s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
240 -s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
241 -s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
242 +s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
243 +s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
244 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
245 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
246 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
247 @@ -77,6 +77,8 @@ s32 igb_phy_force_speed_duplex_82580(st
248 s32 igb_get_cable_length_82580(struct e1000_hw *hw);
249 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
250 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
251 +s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
252 +s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
253 s32 igb_check_polarity_m88(struct e1000_hw *hw);
255 /* IGP01E1000 Specific Registers */