ipq40xx: fix reset button GPIO for GL.iNet GL-B2200
[openwrt/staging/mkresin.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4019-gl-b2200.dts
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7
8 / {
9 model = "GL.iNet GL-B2200";
10 compatible = "glinet,gl-b2200", "qcom,ipq4019";
11
12 memory {
13 device_type = "memory";
14 reg = <0x80000000 0x10000000>;
15 };
16
17 chosen {
18 bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
19 };
20
21 soc {
22 rng@22000 {
23 status = "okay";
24 };
25
26 mdio@90000 {
27 status = "okay";
28 };
29
30 ess-psgmii@98000 {
31 status = "okay";
32 };
33
34 tcsr@1949000 {
35 compatible = "qcom,tcsr";
36 reg = <0x1949000 0x100>;
37 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
38 };
39
40 tcsr@194b000 {
41 /* select hostmode */
42 compatible = "qcom,tcsr";
43 reg = <0x194b000 0x100>;
44 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
45 status = "okay";
46 };
47
48 ess_tcsr@1953000 {
49 compatible = "qcom,tcsr";
50 reg = <0x1953000 0x1000>;
51 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
52 };
53
54 tcsr@1957000 {
55 compatible = "qcom,tcsr";
56 reg = <0x1957000 0x100>;
57 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
58 };
59
60 crypto@8e3a000 {
61 status = "okay";
62 };
63
64 ess-switch@c000000 {
65 status = "okay";
66 switch_lan_bmp = <0x2e>;
67 switch_wan_bmp = <0x10>;
68 };
69
70 edma@c080000 {
71 status = "okay";
72 };
73 };
74
75 keys {
76 compatible = "gpio-keys";
77
78 wps {
79 label = "wps";
80 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
81 linux,code = <KEY_WPS_BUTTON>;
82 linux,input-type = <1>;
83 };
84
85 reset {
86 label = "reset";
87 gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
88 linux,code = <KEY_RESTART>;
89 linux,input-type = <1>;
90 };
91 };
92
93 leds {
94 compatible = "gpio-leds";
95
96 power_blue {
97 label = "blue:power";
98 gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
99 default-state = "on";
100 };
101 internet_blue {
102 label = "blue:internet";
103 gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
104 };
105 power_white {
106 label = "white:power";
107 gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
108 };
109 internet_white {
110 label = "white:internet";
111 gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
112 };
113 };
114 };
115
116 &gmac1 {
117 qcom,phy_mdio_addr = <3>;
118 qcom,poll_required = <1>;
119 qcom,forced_speed = <1000>;
120 qcom,forced_duplex = <1>;
121 vlan_tag = <2 0x10>;
122 };
123
124 &gmac0 {
125 vlan_tag = <1 0x2e>;
126 };
127
128 &vqmmc {
129 status = "okay";
130 };
131
132 &sdhci {
133 status = "okay";
134 pinctrl-0 = <&sd_pins>;
135 pinctrl-names = "default";
136 cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
137 vqmmc-supply = <&vqmmc>;
138 };
139
140 &blsp_dma {
141 status = "okay";
142 };
143
144 &cryptobam {
145 status = "okay";
146 };
147
148 &blsp1_spi1 {
149 pinctrl-0 = <&spi_0_pins>;
150 pinctrl-names = "default";
151 status = "okay";
152 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
153
154 flash@0 {
155 compatible = "jedec,spi-nor";
156 reg = <0>;
157 spi-max-frequency = <24000000>;
158
159 partitions {
160 compatible = "fixed-partitions";
161 #address-cells = <1>;
162 #size-cells = <1>;
163
164 partition@0 {
165 label = "SBL1";
166 reg = <0x0 0x40000>;
167 read-only;
168 };
169
170 partition@40000 {
171 label = "MIBIB";
172 reg = <0x40000 0x20000>;
173 read-only;
174 };
175
176 partition@60000 {
177 label = "QSEE";
178 reg = <0x60000 0x60000>;
179 read-only;
180 };
181
182 partition@c0000 {
183 label = "CDT";
184 reg = <0xc0000 0x10000>;
185 read-only;
186 };
187
188 partition@d0000 {
189 label = "DDRPARAMS";
190 reg = <0xd0000 0x10000>;
191 read-only;
192 };
193
194 partition@e0000 {
195 label = "APPSBLENV";
196 reg = <0xe0000 0x10000>;
197 read-only;
198 };
199
200 partition@f0000 {
201 label = "APPSBL";
202 reg = <0xf0000 0x80000>;
203 read-only;
204 };
205
206 partition@170000 {
207 label = "ART";
208 reg = <0x170000 0x10000>;
209 read-only;
210 };
211 };
212 };
213 };
214
215 &blsp1_spi2 {
216 pinctrl-0 = <&spi_1_pins>;
217 pinctrl-names = "default";
218 status = "okay";
219
220 spidev1: spi@0 {
221 compatible = "siliconlabs,si3210";
222 reg = <0>;
223 spi-max-frequency = <24000000>;
224 };
225 };
226
227 &blsp1_uart1 {
228 pinctrl-0 = <&serial_pins>;
229 pinctrl-names = "default";
230 status = "okay";
231 };
232
233 &blsp1_uart2 {
234 pinctrl-0 = <&serial_1_pins>;
235 pinctrl-names = "default";
236 status = "okay";
237 };
238
239 &tlmm {
240 serial_pins: serial_pinmux {
241 mux {
242 pins = "gpio16", "gpio17";
243 function = "blsp_uart0";
244 bias-disable;
245 };
246 };
247
248 serial_1_pins: serial1_pinmux {
249 mux {
250 pins = "gpio8", "gpio9",
251 "gpio10", "gpio11";
252 function = "blsp_uart1";
253 bias-disable;
254 };
255 };
256
257 spi_0_pins: spi_0_pinmux {
258 pinmux {
259 function = "blsp_spi0";
260 pins = "gpio13", "gpio14", "gpio15";
261 };
262 pinmux_cs {
263 function = "gpio";
264 pins = "gpio12";
265 };
266 pinconf {
267 pins = "gpio13", "gpio14", "gpio15";
268 drive-strength = <12>;
269 bias-disable;
270 };
271 pinconf_cs {
272 pins = "gpio12";
273 drive-strength = <2>;
274 bias-disable;
275 output-high;
276 };
277 };
278
279 spi_1_pins: spi_1_pinmux {
280 mux {
281 pins = "gpio44", "gpio46", "gpio47";
282 function = "blsp_spi1";
283 bias-disable;
284 };
285 cs {
286 pins = "gpio45";
287 function = "gpio";
288 bias-pull-up;
289 };
290 reset {
291 pins = "gpio43";
292 function = "gpio";
293 output-high;
294 };
295 mux_2 {
296 pins = "gpio35";
297 function = "gpio";
298 output-high;
299 };
300 host_int {
301 pins = "gpio2";
302 function = "gpio";
303 input;
304 };
305 wake {
306 pins = "gpio48";
307 function = "gpio";
308 output-high;
309 };
310 };
311
312 sd_pins: sd_pins {
313 pinmux {
314 function = "sdio";
315 pins = "gpio23", "gpio24", "gpio25", "gpio26",
316 "gpio29", "gpio30", "gpio31", "gpio32";
317 drive-strength = <10>;
318 };
319
320 pinmux_sd_clk {
321 function = "sdio";
322 pins = "gpio27";
323 drive-strength = <16>;
324 };
325
326 pinmux_sd7 {
327 function = "sdio";
328 pins = "gpio28";
329 drive-strength = <10>;
330 bias-disable;
331 };
332 };
333
334 };
335
336 &pcie0 {
337 status = "okay";
338 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
339 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
340
341 bridge@0,0 {
342 reg = <0x00000000 0 0 0 0>;
343 #address-cells = <3>;
344 #size-cells = <2>;
345 ranges;
346
347 wifi2: wifi@1,0 {
348 status = "okay";
349 compatible = "qcom,ath10k";
350 reg = <0x00010000 0 0 0 0>;
351 qcom,ath10k-calibration-variant = "GL-B2200";
352 };
353 };
354 };
355
356 &wifi0 {
357 status = "okay";
358 qcom,ath10k-calibration-variant = "GL-B2200";
359 };
360
361 &wifi1 {
362 status = "okay";
363 qcom,ath10k-calibration-variant = "GL-B2200";
364 };