ipq40xx: add Qualcomm QCA807x driver
[openwrt/openwrt.git] / target / linux / ipq40xx / files / drivers / net / phy / qca807x.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2020 Sartura Ltd.
4 *
5 * Author: Robert Marko <robert.marko@sartura.hr>
6 *
7 * Qualcomm QCA8072 and QCA8075 PHY driver
8 */
9
10 #include <linux/version.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/bitfield.h>
15 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
16 #include <linux/ethtool_netlink.h>
17 #endif
18 #include <linux/gpio.h>
19 #include <linux/sfp.h>
20
21 #include <dt-bindings/net/qcom-qca807x.h>
22
23 #define PHY_ID_QCA8072 0x004dd0b2
24 #define PHY_ID_QCA8075 0x004dd0b1
25 #define PHY_ID_QCA807X_PSGMII 0x06820805
26
27 /* Downshift */
28 #define QCA807X_SMARTSPEED_EN BIT(5)
29 #define QCA807X_SMARTSPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
30 #define QCA807X_SMARTSPEED_RETRY_LIMIT_DEFAULT 5
31 #define QCA807X_SMARTSPEED_RETRY_LIMIT_MIN 2
32 #define QCA807X_SMARTSPEED_RETRY_LIMIT_MAX 9
33
34 /* Cable diagnostic test (CDT) */
35 #define QCA807X_CDT 0x16
36 #define QCA807X_CDT_ENABLE BIT(15)
37 #define QCA807X_CDT_ENABLE_INTER_PAIR_SHORT BIT(13)
38 #define QCA807X_CDT_STATUS BIT(11)
39 #define QCA807X_CDT_MMD3_STATUS 0x8064
40 #define QCA807X_CDT_MDI0_STATUS_MASK GENMASK(15, 12)
41 #define QCA807X_CDT_MDI1_STATUS_MASK GENMASK(11, 8)
42 #define QCA807X_CDT_MDI2_STATUS_MASK GENMASK(7, 4)
43 #define QCA807X_CDT_MDI3_STATUS_MASK GENMASK(3, 0)
44 #define QCA807X_CDT_RESULTS_INVALID 0x0
45 #define QCA807X_CDT_RESULTS_OK 0x1
46 #define QCA807X_CDT_RESULTS_OPEN 0x2
47 #define QCA807X_CDT_RESULTS_SAME_SHORT 0x3
48 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK 0x4
49 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK 0x8
50 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK 0xc
51 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN 0x6
52 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN 0xa
53 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN 0xe
54 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT 0x7
55 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT 0xb
56 #define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT 0xf
57 #define QCA807X_CDT_RESULTS_BUSY 0x9
58 #define QCA807X_CDT_MMD3_MDI0_LENGTH 0x8065
59 #define QCA807X_CDT_MMD3_MDI1_LENGTH 0x8066
60 #define QCA807X_CDT_MMD3_MDI2_LENGTH 0x8067
61 #define QCA807X_CDT_MMD3_MDI3_LENGTH 0x8068
62 #define QCA807X_CDT_SAME_SHORT_LENGTH_MASK GENMASK(15, 8)
63 #define QCA807X_CDT_CROSS_SHORT_LENGTH_MASK GENMASK(7, 0)
64
65 #define QCA807X_CHIP_CONFIGURATION 0x1f
66 #define QCA807X_BT_BX_REG_SEL BIT(15)
67 #define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK GENMASK(3, 0)
68 #define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII 4
69 #define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER 3
70 #define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER 0
71
72 #define QCA807X_MEDIA_SELECT_STATUS 0x1a
73 #define QCA807X_MEDIA_DETECTED_COPPER BIT(5)
74 #define QCA807X_MEDIA_DETECTED_1000_BASE_X BIT(4)
75 #define QCA807X_MEDIA_DETECTED_100_BASE_FX BIT(3)
76
77 #define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION 0x807e
78 #define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN BIT(0)
79
80 #define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a
81 #define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0)
82
83 #define QCA807X_MMD7_LED_100N_1 0x8074
84 #define QCA807X_MMD7_LED_100N_2 0x8075
85 #define QCA807X_MMD7_LED_1000N_1 0x8076
86 #define QCA807X_MMD7_LED_1000N_2 0x8077
87 #define QCA807X_LED_TXACT_BLK_EN_2 BIT(10)
88 #define QCA807X_LED_RXACT_BLK_EN_2 BIT(9)
89 #define QCA807X_LED_GT_ON_EN_2 BIT(6)
90 #define QCA807X_LED_HT_ON_EN_2 BIT(5)
91 #define QCA807X_LED_BT_ON_EN_2 BIT(4)
92 #define QCA807X_GPIO_FORCE_EN BIT(15)
93 #define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13)
94
95 #define QCA807X_INTR_ENABLE 0x12
96 #define QCA807X_INTR_STATUS 0x13
97 #define QCA807X_INTR_ENABLE_AUTONEG_ERR BIT(15)
98 #define QCA807X_INTR_ENABLE_SPEED_CHANGED BIT(14)
99 #define QCA807X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
100 #define QCA807X_INTR_ENABLE_LINK_FAIL BIT(11)
101 #define QCA807X_INTR_ENABLE_LINK_SUCCESS BIT(10)
102
103 #define QCA807X_FUNCTION_CONTROL 0x10
104 #define QCA807X_FC_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5)
105 #define QCA807X_FC_MDI_CROSSOVER_AUTO 3
106 #define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX 1
107 #define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI 0
108
109 #define QCA807X_PHY_SPECIFIC_STATUS 0x11
110 #define QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED BIT(11)
111 #define QCA807X_SS_SPEED_MASK GENMASK(15, 14)
112 #define QCA807X_SS_SPEED_1000 2
113 #define QCA807X_SS_SPEED_100 1
114 #define QCA807X_SS_SPEED_10 0
115 #define QCA807X_SS_DUPLEX BIT(13)
116 #define QCA807X_SS_MDIX BIT(6)
117
118 /* PSGMII PHY specific */
119 #define PSGMII_QSGMII_DRIVE_CONTROL_1 0xb
120 #define PSGMII_QSGMII_TX_DRIVER_MASK GENMASK(7, 4)
121 #define PSGMII_MODE_CTRL 0x6d
122 #define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK GENMASK(3, 0)
123 #define PSGMII_MMD3_SERDES_CONTROL 0x805a
124
125 struct qca807x_gpio_priv {
126 struct phy_device *phy;
127 };
128
129 static int qca807x_get_downshift(struct phy_device *phydev, u8 *data)
130 {
131 int val, cnt, enable;
132
133 val = phy_read(phydev, MII_NWAYTEST);
134 if (val < 0)
135 return val;
136
137 enable = FIELD_GET(QCA807X_SMARTSPEED_EN, val);
138 cnt = FIELD_GET(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, val) + 2;
139
140 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
141
142 return 0;
143 }
144
145 static int qca807x_set_downshift(struct phy_device *phydev, u8 cnt)
146 {
147 int ret, val;
148
149 if (cnt > QCA807X_SMARTSPEED_RETRY_LIMIT_MAX ||
150 (cnt < QCA807X_SMARTSPEED_RETRY_LIMIT_MIN && cnt != DOWNSHIFT_DEV_DISABLE))
151 return -EINVAL;
152
153 if (!cnt) {
154 ret = phy_clear_bits(phydev, MII_NWAYTEST, QCA807X_SMARTSPEED_EN);
155 } else {
156 val = QCA807X_SMARTSPEED_EN;
157 val |= FIELD_PREP(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, cnt - 2);
158
159 phy_modify(phydev, MII_NWAYTEST,
160 QCA807X_SMARTSPEED_EN |
161 QCA807X_SMARTSPEED_RETRY_LIMIT_MASK,
162 val);
163 }
164
165 ret = genphy_soft_reset(phydev);
166
167 return ret;
168 }
169
170 static int qca807x_get_tunable(struct phy_device *phydev,
171 struct ethtool_tunable *tuna, void *data)
172 {
173 switch (tuna->id) {
174 case ETHTOOL_PHY_DOWNSHIFT:
175 return qca807x_get_downshift(phydev, data);
176 default:
177 return -EOPNOTSUPP;
178 }
179 }
180
181 static int qca807x_set_tunable(struct phy_device *phydev,
182 struct ethtool_tunable *tuna, const void *data)
183 {
184 switch (tuna->id) {
185 case ETHTOOL_PHY_DOWNSHIFT:
186 return qca807x_set_downshift(phydev, *(const u8 *)data);
187 default:
188 return -EOPNOTSUPP;
189 }
190 }
191
192 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
193 static bool qca807x_distance_valid(int result)
194 {
195 switch (result) {
196 case QCA807X_CDT_RESULTS_OPEN:
197 case QCA807X_CDT_RESULTS_SAME_SHORT:
198 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
199 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
200 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
201 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
202 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
203 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
204 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
205 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
206 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
207 return true;
208 }
209 return false;
210 }
211
212 static int qca807x_report_length(struct phy_device *phydev,
213 int pair, int result)
214 {
215 int length;
216 int ret;
217
218 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_MDI0_LENGTH + pair);
219 if (ret < 0)
220 return ret;
221
222 switch (result) {
223 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
224 length = (FIELD_GET(QCA807X_CDT_SAME_SHORT_LENGTH_MASK, ret) * 800) / 10;
225 break;
226 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
227 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
228 length = (FIELD_GET(QCA807X_CDT_CROSS_SHORT_LENGTH_MASK, ret) * 800) / 10;
229 break;
230 }
231
232 ethnl_cable_test_fault_length(phydev, pair, length);
233
234 return 0;
235 }
236
237 static int qca807x_cable_test_report_trans(int result)
238 {
239 switch (result) {
240 case QCA807X_CDT_RESULTS_OK:
241 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
242 case QCA807X_CDT_RESULTS_OPEN:
243 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
244 case QCA807X_CDT_RESULTS_SAME_SHORT:
245 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
246 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:
247 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:
248 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:
249 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
250 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
251 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
252 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
253 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
254 case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
255 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
256 default:
257 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
258 }
259 }
260
261 static int qca807x_cable_test_report(struct phy_device *phydev)
262 {
263 int pair0, pair1, pair2, pair3;
264 int ret;
265
266 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_STATUS);
267 if (ret < 0)
268 return ret;
269
270 pair0 = FIELD_GET(QCA807X_CDT_MDI0_STATUS_MASK, ret);
271 pair1 = FIELD_GET(QCA807X_CDT_MDI1_STATUS_MASK, ret);
272 pair2 = FIELD_GET(QCA807X_CDT_MDI2_STATUS_MASK, ret);
273 pair3 = FIELD_GET(QCA807X_CDT_MDI3_STATUS_MASK, ret);
274
275 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
276 qca807x_cable_test_report_trans(pair0));
277 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
278 qca807x_cable_test_report_trans(pair1));
279 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
280 qca807x_cable_test_report_trans(pair2));
281 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
282 qca807x_cable_test_report_trans(pair3));
283
284 if (qca807x_distance_valid(pair0))
285 qca807x_report_length(phydev, 0, qca807x_cable_test_report_trans(pair0));
286 if (qca807x_distance_valid(pair1))
287 qca807x_report_length(phydev, 1, qca807x_cable_test_report_trans(pair1));
288 if (qca807x_distance_valid(pair2))
289 qca807x_report_length(phydev, 2, qca807x_cable_test_report_trans(pair2));
290 if (qca807x_distance_valid(pair3))
291 qca807x_report_length(phydev, 3, qca807x_cable_test_report_trans(pair3));
292
293 return 0;
294 }
295
296 static int qca807x_cable_test_get_status(struct phy_device *phydev,
297 bool *finished)
298 {
299 int val;
300
301 *finished = false;
302
303 val = phy_read(phydev, QCA807X_CDT);
304 if (!((val & QCA807X_CDT_ENABLE) && (val & QCA807X_CDT_STATUS))) {
305 *finished = true;
306
307 return qca807x_cable_test_report(phydev);
308 }
309
310 return 0;
311 }
312
313 static int qca807x_cable_test_start(struct phy_device *phydev)
314 {
315 int val, ret;
316
317 val = phy_read(phydev, QCA807X_CDT);
318 /* Enable inter-pair short check as well */
319 val &= ~QCA807X_CDT_ENABLE_INTER_PAIR_SHORT;
320 val |= QCA807X_CDT_ENABLE;
321 ret = phy_write(phydev, QCA807X_CDT, val);
322
323 return ret;
324 }
325 #endif
326
327 #ifdef CONFIG_GPIOLIB
328 static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
329 {
330 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,5,0)
331 return GPIO_LINE_DIRECTION_OUT;
332 #else
333 return GPIOF_DIR_OUT;
334 #endif
335 }
336
337 static int qca807x_gpio_get_reg(unsigned int offset)
338 {
339 return QCA807X_MMD7_LED_100N_2 + (offset % 2) * 2;
340 }
341
342 static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
343 {
344 struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
345 int val;
346
347 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
348
349 return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
350 }
351
352 static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
353 {
354 struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
355 int val;
356
357 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));
358 val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
359 val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
360
361 phy_write_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset), val);
362 }
363
364 static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
365 {
366 qca807x_gpio_set(gc, offset, value);
367
368 return 0;
369 }
370
371 static int qca807x_gpio(struct phy_device *phydev)
372 {
373 struct device *dev = &phydev->mdio.dev;
374 struct qca807x_gpio_priv *priv;
375 struct gpio_chip *gc;
376
377 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
378 if (!priv)
379 return -ENOMEM;
380
381 priv->phy = phydev;
382
383 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
384 if (!gc)
385 return -ENOMEM;
386
387 gc->label = dev_name(dev);
388 gc->base = -1;
389 gc->ngpio = 2;
390 gc->parent = dev;
391 gc->owner = THIS_MODULE;
392 gc->can_sleep = true;
393 gc->get_direction = qca807x_gpio_get_direction;
394 gc->direction_output = qca807x_gpio_dir_out;
395 gc->get = qca807x_gpio_get;
396 gc->set = qca807x_gpio_set;
397
398 return devm_gpiochip_add_data(dev, gc, priv);
399 }
400 #endif
401
402 static int qca807x_read_copper_status(struct phy_device *phydev, bool combo_port)
403 {
404 int ss, err, page, old_link = phydev->link;
405
406 /* Only combo port has dual pages */
407 if (combo_port) {
408 /* Check whether copper page is set and set if needed */
409 page = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
410 if (!(page & QCA807X_BT_BX_REG_SEL)) {
411 page |= QCA807X_BT_BX_REG_SEL;
412 phy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);
413 }
414 }
415
416 /* Update the link, but return if there was an error */
417 err = genphy_update_link(phydev);
418 if (err)
419 return err;
420
421 /* why bother the PHY if nothing can have changed */
422 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
423 return 0;
424
425 phydev->speed = SPEED_UNKNOWN;
426 phydev->duplex = DUPLEX_UNKNOWN;
427 phydev->pause = 0;
428 phydev->asym_pause = 0;
429
430 err = genphy_read_lpa(phydev);
431 if (err < 0)
432 return err;
433
434 /* Read the QCA807x PHY-Specific Status register copper page,
435 * which indicates the speed and duplex that the PHY is actually
436 * using, irrespective of whether we are in autoneg mode or not.
437 */
438 ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
439 if (ss < 0)
440 return ss;
441
442 if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
443 int sfc;
444
445 sfc = phy_read(phydev, QCA807X_FUNCTION_CONTROL);
446 if (sfc < 0)
447 return sfc;
448
449 switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
450 case QCA807X_SS_SPEED_10:
451 phydev->speed = SPEED_10;
452 break;
453 case QCA807X_SS_SPEED_100:
454 phydev->speed = SPEED_100;
455 break;
456 case QCA807X_SS_SPEED_1000:
457 phydev->speed = SPEED_1000;
458 break;
459 }
460 if (ss & QCA807X_SS_DUPLEX)
461 phydev->duplex = DUPLEX_FULL;
462 else
463 phydev->duplex = DUPLEX_HALF;
464
465 if (ss & QCA807X_SS_MDIX)
466 phydev->mdix = ETH_TP_MDI_X;
467 else
468 phydev->mdix = ETH_TP_MDI;
469
470 switch (FIELD_GET(QCA807X_FC_MDI_CROSSOVER_MODE_MASK, sfc)) {
471 case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI:
472 phydev->mdix_ctrl = ETH_TP_MDI;
473 break;
474 case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX:
475 phydev->mdix_ctrl = ETH_TP_MDI_X;
476 break;
477 case QCA807X_FC_MDI_CROSSOVER_AUTO:
478 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
479 break;
480 }
481 }
482
483 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
484 phy_resolve_aneg_pause(phydev);
485
486 return 0;
487 }
488
489 static int qca807x_read_fiber_status(struct phy_device *phydev, bool combo_port)
490 {
491 int ss, err, page, lpa, old_link = phydev->link;
492
493 /* Check whether fiber page is set and set if needed */
494 page = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
495 if (page & QCA807X_BT_BX_REG_SEL) {
496 page &= ~QCA807X_BT_BX_REG_SEL;
497 phy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);
498 }
499
500 /* Update the link, but return if there was an error */
501 err = genphy_update_link(phydev);
502 if (err)
503 return err;
504
505 /* why bother the PHY if nothing can have changed */
506 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
507 return 0;
508
509 phydev->speed = SPEED_UNKNOWN;
510 phydev->duplex = DUPLEX_UNKNOWN;
511 phydev->pause = 0;
512 phydev->asym_pause = 0;
513
514 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
515 lpa = phy_read(phydev, MII_LPA);
516 if (lpa < 0)
517 return lpa;
518
519 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
520 phydev->lp_advertising, lpa & LPA_LPACK);
521 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
522 phydev->lp_advertising, lpa & LPA_1000XFULL);
523 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
524 phydev->lp_advertising, lpa & LPA_1000XPAUSE);
525 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
526 phydev->lp_advertising,
527 lpa & LPA_1000XPAUSE_ASYM);
528
529 phy_resolve_aneg_linkmode(phydev);
530 }
531
532 /* Read the QCA807x PHY-Specific Status register fiber page,
533 * which indicates the speed and duplex that the PHY is actually
534 * using, irrespective of whether we are in autoneg mode or not.
535 */
536 ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);
537 if (ss < 0)
538 return ss;
539
540 if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {
541 switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {
542 case QCA807X_SS_SPEED_100:
543 phydev->speed = SPEED_100;
544 break;
545 case QCA807X_SS_SPEED_1000:
546 phydev->speed = SPEED_1000;
547 break;
548 }
549
550 if (ss & QCA807X_SS_DUPLEX)
551 phydev->duplex = DUPLEX_FULL;
552 else
553 phydev->duplex = DUPLEX_HALF;
554 }
555
556 return 0;
557 }
558
559 static int qca807x_read_status(struct phy_device *phydev)
560 {
561 int val;
562
563 /* Check for Combo port */
564 if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
565 /* Check for fiber mode first */
566 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
567 /* Check for actual detected media */
568 val = phy_read(phydev, QCA807X_MEDIA_SELECT_STATUS);
569 if (val & QCA807X_MEDIA_DETECTED_COPPER) {
570 qca807x_read_copper_status(phydev, true);
571 } else if ((val & QCA807X_MEDIA_DETECTED_1000_BASE_X) ||
572 (val & QCA807X_MEDIA_DETECTED_100_BASE_FX)) {
573 qca807x_read_fiber_status(phydev, true);
574 }
575 } else {
576 qca807x_read_copper_status(phydev, true);
577 }
578 } else {
579 qca807x_read_copper_status(phydev, false);
580 }
581
582 return 0;
583 }
584
585 static int qca807x_config_intr(struct phy_device *phydev)
586 {
587 int ret, val;
588
589 val = phy_read(phydev, QCA807X_INTR_ENABLE);
590
591 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
592 /* Check for combo port as it has fewer interrupts */
593 if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
594 val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
595 val |= QCA807X_INTR_ENABLE_LINK_FAIL;
596 val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
597 } else {
598 val |= QCA807X_INTR_ENABLE_AUTONEG_ERR;
599 val |= QCA807X_INTR_ENABLE_SPEED_CHANGED;
600 val |= QCA807X_INTR_ENABLE_DUPLEX_CHANGED;
601 val |= QCA807X_INTR_ENABLE_LINK_FAIL;
602 val |= QCA807X_INTR_ENABLE_LINK_SUCCESS;
603 }
604 ret = phy_write(phydev, QCA807X_INTR_ENABLE, val);
605 } else {
606 ret = phy_write(phydev, QCA807X_INTR_ENABLE, 0);
607 }
608
609 return ret;
610 }
611
612 static int qca807x_ack_intr(struct phy_device *phydev)
613 {
614 int ret;
615
616 ret = phy_read(phydev, QCA807X_INTR_STATUS);
617
618 return (ret < 0) ? ret : 0;
619 }
620
621 static int qca807x_led_config(struct phy_device *phydev)
622 {
623 struct device_node *node = phydev->mdio.dev.of_node;
624 bool led_config = false;
625 int val;
626
627 val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1);
628 if (val < 0)
629 return val;
630
631 if (of_property_read_bool(node, "qcom,single-led-1000")) {
632 val |= QCA807X_LED_TXACT_BLK_EN_2;
633 val |= QCA807X_LED_RXACT_BLK_EN_2;
634 val |= QCA807X_LED_GT_ON_EN_2;
635
636 led_config = true;
637 }
638
639 if (of_property_read_bool(node, "qcom,single-led-100")) {
640 val |= QCA807X_LED_HT_ON_EN_2;
641
642 led_config = true;
643 }
644
645 if (of_property_read_bool(node, "qcom,single-led-10")) {
646 val |= QCA807X_LED_BT_ON_EN_2;
647
648 led_config = true;
649 }
650
651 if (led_config)
652 return phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1, val);
653 else
654 return 0;
655 }
656
657 static const struct sfp_upstream_ops qca807x_sfp_ops = {
658 .attach = phy_sfp_attach,
659 .detach = phy_sfp_detach,
660 };
661
662 static int qca807x_config(struct phy_device *phydev)
663 {
664 struct device_node *node = phydev->mdio.dev.of_node;
665 int control_dac, ret = 0;
666 u32 of_control_dac;
667
668 /* Check for Combo port */
669 if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
670 int fiber_mode_autodect;
671 int psgmii_serdes;
672 int chip_config;
673
674 if (of_property_read_bool(node, "qcom,fiber-enable")) {
675 /* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
676 fiber_mode_autodect = phy_read_mmd(phydev, MDIO_MMD_AN,
677 QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION);
678 fiber_mode_autodect |= QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN;
679 phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
680 fiber_mode_autodect);
681
682 /* Enable 4 copper + combo port mode */
683 chip_config = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);
684 chip_config &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;
685 chip_config |= FIELD_PREP(QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
686 QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
687 phy_write(phydev, QCA807X_CHIP_CONFIGURATION, chip_config);
688
689 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
690 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
691 }
692
693 /* Prevent PSGMII going into hibernation via PSGMII self test */
694 psgmii_serdes = phy_read_mmd(phydev, MDIO_MMD_PCS, PSGMII_MMD3_SERDES_CONTROL);
695 psgmii_serdes &= ~BIT(1);
696 ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
697 PSGMII_MMD3_SERDES_CONTROL,
698 psgmii_serdes);
699 }
700
701 if (!of_property_read_u32(node, "qcom,control-dac", &of_control_dac)) {
702 control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
703 QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
704 control_dac &= ~QCA807X_CONTROL_DAC_MASK;
705 control_dac |= FIELD_PREP(QCA807X_CONTROL_DAC_MASK, of_control_dac);
706 ret = phy_write_mmd(phydev, MDIO_MMD_AN,
707 QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
708 control_dac);
709 }
710
711 /* Optionally configure LED-s */
712 if (IS_ENABLED(CONFIG_GPIOLIB)) {
713 /* Check whether PHY-s pins are used as GPIO-s */
714 if (!of_property_read_bool(node, "gpio-controller"))
715 ret = qca807x_led_config(phydev);
716 } else {
717 ret = qca807x_led_config(phydev);
718 }
719
720 return ret;
721 }
722
723 static int qca807x_probe(struct phy_device *phydev)
724 {
725 struct device_node *node = phydev->mdio.dev.of_node;
726 int ret = 0;
727
728 if (IS_ENABLED(CONFIG_GPIOLIB)) {
729 /* Do not register a GPIO controller unless flagged for it */
730 if (of_property_read_bool(node, "gpio-controller"))
731 ret = qca807x_gpio(phydev);
732 }
733
734 /* Attach SFP bus on combo port*/
735 if (of_property_read_bool(node, "qcom,fiber-enable")) {
736 if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION))
737 ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
738 }
739
740 return ret;
741 }
742
743 static int qca807x_psgmii_config(struct phy_device *phydev)
744 {
745 struct device_node *node = phydev->mdio.dev.of_node;
746 int psgmii_az, tx_amp, ret = 0;
747 u32 tx_driver_strength;
748
749 /* Workaround to enable AZ transmitting ability */
750 if (of_property_read_bool(node, "qcom,psgmii-az")) {
751 psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);
752 psgmii_az &= ~PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;
753 psgmii_az |= FIELD_PREP(PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK, 0xc);
754 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL, psgmii_az);
755 psgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);
756 }
757
758 /* PSGMII/QSGMII TX amp set to DT defined value instead of default 600mV */
759 if (!of_property_read_u32(node, "qcom,tx-driver-strength", &tx_driver_strength)) {
760 tx_amp = phy_read(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1);
761 tx_amp &= ~PSGMII_QSGMII_TX_DRIVER_MASK;
762 tx_amp |= FIELD_PREP(PSGMII_QSGMII_TX_DRIVER_MASK, tx_driver_strength);
763 ret = phy_write(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1, tx_amp);
764 }
765
766 return ret;
767 }
768
769 static struct phy_driver qca807x_drivers[] = {
770 {
771 PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
772 .name = "Qualcomm QCA8072",
773 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
774 .flags = PHY_POLL_CABLE_TEST,
775 #endif
776 /* PHY_GBIT_FEATURES */
777 .probe = qca807x_probe,
778 .config_init = qca807x_config,
779 .read_status = qca807x_read_status,
780 .config_intr = qca807x_config_intr,
781 .ack_interrupt = qca807x_ack_intr,
782 .soft_reset = genphy_soft_reset,
783 .get_tunable = qca807x_get_tunable,
784 .set_tunable = qca807x_set_tunable,
785 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
786 .cable_test_start = qca807x_cable_test_start,
787 .cable_test_get_status = qca807x_cable_test_get_status,
788 #endif
789 },
790 {
791 PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
792 .name = "Qualcomm QCA8075",
793 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
794 .flags = PHY_POLL_CABLE_TEST,
795 #endif
796 /* PHY_GBIT_FEATURES */
797 .probe = qca807x_probe,
798 .config_init = qca807x_config,
799 .read_status = qca807x_read_status,
800 .config_intr = qca807x_config_intr,
801 .ack_interrupt = qca807x_ack_intr,
802 .soft_reset = genphy_soft_reset,
803 .get_tunable = qca807x_get_tunable,
804 .set_tunable = qca807x_set_tunable,
805 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
806 .cable_test_start = qca807x_cable_test_start,
807 .cable_test_get_status = qca807x_cable_test_get_status,
808 #endif
809 },
810 {
811 PHY_ID_MATCH_EXACT(PHY_ID_QCA807X_PSGMII),
812 .name = "Qualcomm QCA807x PSGMII",
813 .probe = qca807x_psgmii_config,
814 },
815 };
816 module_phy_driver(qca807x_drivers);
817
818 static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
819 { PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
820 { PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
821 { PHY_ID_MATCH_MODEL(PHY_ID_QCA807X_PSGMII) },
822 { }
823 };
824
825 MODULE_AUTHOR("Robert Marko");
826 MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
827 MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
828 MODULE_LICENSE("GPL");