target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "EdgeCore OAP-100";
  10         compatible = "edgecore,oap100";
  11
  12         aliases {
  13                 led-boot = &led_system;
  14                 led-failsafe = &led_system;
  15                 led-running = &led_system;
  16                 led-upgrade = &led_system;
  17         };
  18
  19         chosen {
  20                 bootargs-append = " root=/dev/ubiblock0_1";
  21         };
  22
  23         soc {
  24                 mdio@90000 {
  25                         status = "okay";
  26                         pinctrl-0 = <&mdio_pins>;
  27                         pinctrl-names = "default";
  28                 };
  29
  30                 tcsr@1949000 {
  31                         compatible = "qcom,tcsr";
  32                         reg = <0x1949000 0x100>;
  33                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  34                 };
  35
  36                 ess_tcsr@1953000 {
  37                         compatible = "qcom,tcsr";
  38                         reg = <0x1953000 0x1000>;
  39                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  40                 };
  41
  42                 tcsr@1957000 {
  43                         compatible = "qcom,tcsr";
  44                         reg = <0x1957000 0x100>;
  45                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  46                 };
  47
  48                 tcsr@194b000 {
  49                         /* select hostmode */
  50                         compatible = "qcom,tcsr";
  51                         reg = <0x194b000 0x100>;
  52                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  53                         status = "okay";
  54                 };
  55
  56                 crypto@8e3a000 {
  57                         status = "okay";
  58                 };
  59
  60                 watchdog@b017000 {
  61                         status = "okay";
  62                 };
  63         };
  64
  65         key {
  66                 compatible = "gpio-keys";
  67
  68                 button@1 {
  69                         label = "reset";
  70                         linux,code = <KEY_RESTART>;
  71                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  72                         linux,input-type = <1>;
  73                 };
  74         };
  75
  76         leds {
  77                 compatible = "gpio-leds";
  78
  79                 led_system: led_system {
  80                         label = "green:system";
  81                         gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
  82                 };
  83
  84                 led_2g {
  85                         label = "blue:wlan2g";
  86                         gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
  87                 };
  88
  89                 led_5g {
  90                         label = "blue:wlan5g";
  91                         gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
  92                 };
  93         };
  94
  95         gpio_export {
  96                 compatible = "gpio-export";
  97                 #size-cells = <0>;
  98
  99                 usb {
 100                         gpio-export,name = "usb-power";
 101                         gpio-export,output = <1>;
 102                         gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
 103                 };
 104
 105                 poe {
 106                         gpio-export,name = "poe-power";
 107                         gpio-export,output = <0>;
 108                         gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
 109                 };
 110         };
 111 };
 112
 113 &tlmm {
 114         serial_0_pins: serial_pinmux {
 115                 mux {
 116                         pins = "gpio16", "gpio17";
 117                         function = "blsp_uart0";
 118                         bias-disable;
 119                 };
 120         };
 121
 122         spi_0_pins: spi_0_pinmux {
 123                 pinmux {
 124                         function = "blsp_spi0";
 125                         pins = "gpio13", "gpio14", "gpio15";
 126                         drive-strength = <12>;
 127                         bias-disable;
 128                 };
 129
 130                 pinmux_cs {
 131                         function = "gpio";
 132                         pins = "gpio12";
 133                         drive-strength = <2>;
 134                         bias-disable;
 135                         output-high;
 136                 };
 137         };
 138
 139         nand_pins: nand_pins {
 140                 pullups {
 141                         pins = "gpio53", "gpio58", "gpio59";
 142                         function = "qpic";
 143                         bias-pull-up;
 144                 };
 145
 146                 pulldowns {
 147                         pins = "gpio54", "gpio55", "gpio56",
 148                                 "gpio57", "gpio60", "gpio61",
 149                                 "gpio62", "gpio63", "gpio64",
 150                                 "gpio65", "gpio66", "gpio67",
 151                                 "gpio68", "gpio69";
 152                         function = "qpic";
 153                         bias-pull-down;
 154                 };
 155         };
 156
 157         mdio_pins: mdio_pinmux {
 158                 mux_1 {
 159                         pins = "gpio6";
 160                         function = "mdio";
 161                         bias-pull-up;
 162                 };
 163                 mux_2 {
 164                         pins = "gpio7";
 165                         function = "mdc";
 166                         bias-pull-up;
 167                 };
 168         };
 169 };
 170
 171 &cryptobam {
 172         status = "okay";
 173 };
 174
 175 &blsp1_spi1 {
 176         pinctrl-0 = <&spi_0_pins>;
 177         pinctrl-names = "default";
 178         status = "okay";
 179         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
 180
 181         flash@0 {
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184                 compatible = "jedec,spi-nor";
 185                 reg = <0>;
 186                 linux,modalias = "m25p80", "gd25q256";
 187                 spi-max-frequency = <24000000>;
 188
 189                 partitions {
 190                         compatible = "fixed-partitions";
 191                         #address-cells = <1>;
 192                         #size-cells = <1>;
 193
 194                         partition0@0 {
 195                                 label = "0:SBL1";
 196                                 reg = <0x00000000 0x00040000>;
 197                                 read-only;
 198                         };
 199                         partition1@40000 {
 200                                 label = "0:MIBIB";
 201                                 reg = <0x00040000 0x00020000>;
 202                                 read-only;
 203                         };
 204                         partition2@60000 {
 205                                 label = "0:QSEE";
 206                                 reg = <0x00060000 0x00060000>;
 207                                 read-only;
 208                         };
 209                         partition3@c0000 {
 210                                 label = "0:CDT";
 211                                 reg = <0x000c0000 0x00010000>;
 212                                 read-only;
 213                         };
 214                         partition4@d0000 {
 215                                 label = "0:DDRPARAMS";
 216                                 reg = <0x000d0000 0x00010000>;
 217                                 read-only;
 218                         };
 219                         partition5@e0000 {
 220                                 label = "0:APPSBLENV";
 221                                 reg = <0x000e0000 0x00010000>;
 222                                 read-only;
 223                         };
 224                         partition6@f0000 {
 225                                 label = "0:APPSBL";
 226                                 reg = <0x000f0000 0x00080000>;
 227                                 read-only;
 228                         };
 229                         partition7@170000 {
 230                                 label = "0:ART";
 231                                 reg = <0x00170000 0x00010000>;
 232                                 read-only;
 233
 234                                 nvmem-layout {
 235                                         compatible = "fixed-layout";
 236                                         #address-cells = <1>;
 237                                         #size-cells = <1>;
 238
 239                                         precal_art_1000: precal@1000 {
 240                                                 reg = <0x1000 0x2f20>;
 241                                         };
 242
 243                                         precal_art_5000: precal@5000 {
 244                                                 reg = <0x5000 0x2f20>;
 245                                         };
 246                                 };
 247                         };
 248                 };
 249         };
 250 };
 251
 252 &nand {
 253         pinctrl-0 = <&nand_pins>;
 254         pinctrl-names = "default";
 255         status = "okay";
 256
 257         nand@0 {
 258                 partitions {
 259                         compatible = "fixed-partitions";
 260                         #address-cells = <1>;
 261                         #size-cells = <1>;
 262
 263                         partition@0 {
 264                                 label = "rootfs";
 265                                 reg = <0x00000000 0x4000000>;
 266                         };
 267                 };
 268         };
 269 };
 270
 271 &blsp_dma {
 272         status = "okay";
 273 };
 274
 275 &blsp1_uart1 {
 276         pinctrl-0 = <&serial_0_pins>;
 277         pinctrl-names = "default";
 278         status = "okay";
 279 };
 280
 281 &qpic_bam {
 282         status = "okay";
 283 };
 284
 285 &wifi0 {
 286         status = "okay";
 287         nvmem-cell-names = "pre-calibration";
 288         nvmem-cells = <&precal_art_1000>;
 289         qcom,ath10k-calibration-variant = "Edgecore OAP100";
 290 };
 291
 292 &wifi1 {
 293         status = "okay";
 294         nvmem-cell-names = "pre-calibration";
 295         nvmem-cells = <&precal_art_5000>;
 296         qcom,ath10k-calibration-variant = "Edgecore OAP100";
 297 };
 298
 299 &usb3_ss_phy {
 300         status = "okay";
 301 };
 302
 303 &usb3_hs_phy {
 304         status = "okay";
 305 };
 306
 307 &usb3 {
 308         status = "okay";
 309 };
 310
 311 &usb3_dwc {
 312         #address-cells = <1>;
 313         #size-cells = <0>;
 314
 315         usb3_port1: port@1 {
 316                 reg = <1>;
 317                 #trigger-source-cells = <0>;
 318         };
 319
 320         usb3_port2: port@2 {
 321                 reg = <2>;
 322                 #trigger-source-cells = <0>;
 323         };
 324 };
 325
 326
 327 &usb2_hs_phy {
 328         status = "okay";
 329 };
 330
 331 &usb2 {
 332         status = "okay";
 333
 334         usb@6000000 {
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337
 338                 usb2_port1: port@1 {
 339                         reg = <1>;
 340                         #trigger-source-cells = <0>;
 341                 };
 342         };
 343 };