1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for Meraki "Insect" series
5 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
6 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
8 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
15 #include "qcom-ipq4019.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
19 #include <dt-bindings/leds/common.h>
23 led-boot = &status_green;
24 led-failsafe = &status_red;
25 led-running = &status_green;
26 led-upgrade = &power_orange;
29 /* Do we really need this defined? */
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>;
38 pinctrl-0 = <&mdio_pins>;
39 pinctrl-names = "default";
42 /* It is a 56-bit counter that supplies the count to the ARM arch
43 timers and without upstream driver */
45 compatible = "qcom,qca-gcnt";
50 compatible = "qcom,tcsr";
51 reg = <0x1953000 0x1000>;
52 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
56 compatible = "qcom,tcsr";
57 reg = <0x1949000 0x100>;
58 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
62 compatible = "qcom,tcsr";
63 reg = <0x1957000 0x100>;
64 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
68 pinctrl-0 = <&serial_1_pins>;
69 pinctrl-names = "default";
73 compatible = "ti,cc2650";
74 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
84 compatible = "gpio-keys";
88 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
89 linux,code = <KEY_RESTART>;
94 compatible = "gpio-leds";
97 function = LED_FUNCTION_POWER;
98 color = <LED_COLOR_ID_ORANGE>;
99 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
118 pinctrl-0 = <&serial_0_pins>;
119 pinctrl-names = "default";
128 pinctrl-0 = <&i2c_0_pins>;
129 pinctrl-names = "default";
133 compatible = "atmel,24c64";
136 read-only; /* This holds our MAC & Meraki board-data */
137 #address-cells = <1>;
140 mac_address: mac-address@66 {
141 compatible = "mac-base";
143 #nvmem-cell-cells = <1>;
149 pinctrl-0 = <&i2c_1_pins>;
150 pinctrl-names = "default";
153 tricolor: led-controller@30 {
154 compatible = "ti,lp5562";
156 clock-mode = /bits/8 <2>;
157 #address-cells = <1>;
162 chan-name = "red:status";
163 led-cur = /bits/ 8 <0x20>;
164 max-cur = /bits/ 8 <0x60>;
166 color = <LED_COLOR_ID_RED>;
169 status_green: chan@1 {
170 chan-name = "green:status";
171 led-cur = /bits/ 8 <0x20>;
172 max-cur = /bits/ 8 <0x60>;
174 color = <LED_COLOR_ID_GREEN>;
178 chan-name = "blue:status";
179 led-cur = /bits/ 8 <0x20>;
180 max-cur = /bits/ 8 <0x60>;
182 color = <LED_COLOR_ID_BLUE>;
186 chan-name = "white:status";
187 led-cur = /bits/ 8 <0x20>;
188 max-cur = /bits/ 8 <0x60>;
190 color = <LED_COLOR_ID_WHITE>;
196 pinctrl-0 = <&nand_pins>;
197 pinctrl-names = "default";
202 compatible = "fixed-partitions";
203 #address-cells = <1>;
208 reg = <0x00000000 0x00100000>;
213 reg = <0x00100000 0x00100000>;
217 label = "bootconfig";
218 reg = <0x00200000 0x00100000>;
223 reg = <0x00300000 0x00100000>;
228 reg = <0x00400000 0x00100000>;
233 reg = <0x00500000 0x00080000>;
238 reg = <0x00580000 0x00080000>;
243 reg = <0x00600000 0x00080000>;
248 reg = <0x00700000 0x00200000>;
252 label = "u-boot-backup";
253 reg = <0x00900000 0x00200000>;
258 reg = <0x00b00000 0x00080000>;
263 reg = <0x00c00000 0x07000000>;
265 * Do not try to allocate the remaining
266 * 4 MiB to this ubi partition. It will
267 * confuse the u-boot and it might not
268 * find the kernel partition anymore.
277 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
278 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
281 reg = <0x00000000 0 0 0 0>;
282 #address-cells = <3>;
287 compatible = "qcom,ath10k";
289 reg = <0x00010000 0 0 0 0>;
290 nvmem-cells = <&mac_address 1>;
291 nvmem-cell-names = "mac-address";
302 * GPIO43 should be 0/1 whenever the unit is
303 * powered through PoE or AC-Adapter.
304 * That said, playing with this seems to
308 mdio_pins: mdio_pinmux {
321 serial_0_pins: serial_pinmux {
323 pins = "gpio16", "gpio17";
324 function = "blsp_uart0";
329 serial_1_pins: serial1_pinmux {
331 /* We use the i2c-0 pins for serial_1 */
332 pins = "gpio8", "gpio9";
333 function = "blsp_uart1";
338 i2c_0_pins: i2c_0_pinmux {
340 function = "blsp_i2c0";
341 pins = "gpio20", "gpio21";
344 pins = "gpio20", "gpio21";
345 drive-strength = <16>;
350 i2c_1_pins: i2c_1_pinmux {
352 function = "blsp_i2c1";
353 pins = "gpio34", "gpio35";
356 pins = "gpio34", "gpio35";
357 drive-strength = <16>;
362 nand_pins: nand_pins {
364 * There are 18 pins. 15 pins are common between LCD and NAND.
365 * The QPIC controller arbitrates between LCD and NAND. Of the
366 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
368 * The meraki source hints that the bluetooth module claims
369 * pin 52 as well. But sadly, there's no data whenever this
370 * is a NAND or LCD exclusive pin or not.
374 pins = "gpio52", "gpio53", "gpio58",
381 pins = "gpio54", "gpio55", "gpio56",
382 "gpio57", "gpio60", "gpio61",
383 "gpio62", "gpio63", "gpio64",
384 "gpio65", "gpio66", "gpio67",
394 qcom,ath10k-calibration-variant = "Meraki-MR33";
395 nvmem-cells = <&mac_address 2>;
396 nvmem-cell-names = "mac-address";
401 qcom,ath10k-calibration-variant = "Meraki-MR33";
402 nvmem-cells = <&mac_address 3>;
403 nvmem-cell-names = "mac-address";
408 nvmem-cells = <&mac_address 0>;
409 nvmem-cell-names = "mac-address";
415 /delete-property/ psgmii-ethphy;
422 phy-handle = <ðphy1>;
423 phy-mode = "rgmii-rxid";