target/linux/ipq40xx/patches-4.14/716-essedma-vlan-double-tag.patch

   1 From: Sven Eckelmann <sven@narfation.org>
   2 Date: Wed, 8 Feb 2017 16:26:00 +0100
   3 Subject: [PATCH] ipq40xx: Fix ar40xx port separation
   4
   5 It is currently not possible to submit (or receive) VLAN tagged frames over
   6 the ar40xx PHY switch and the edma ethernet device.
   7
   8 This can be worked around by disabling enable_vlan. The separation of the
   9 eth0 and eth1 ports is then done by the vlan_tag information from the
  10 device tree. But the ar40xx PHY switch then also has to parse the word3
  11 port bitmap (word3) from the TDP when data was received from the CPU port
  12 (0).
  13
  14 IssueID: #2857
  15
  16 Forwarded: no
  17  The ar40xx.c change was forwarded to Xiaofei Shen <xiaofeis@codeaurora.org>
  18  (QCA). But John Crispin will rewrite the driver anyway and we have to check
  19  later if this change is required in his driver too.
  20 ---
  21  drivers/net/phy/ar40xx.c | 6 +++++-
  22  1 file changed, 5 insertions(+), 1 deletion(-)
  23
  24 --- a/drivers/net/phy/ar40xx.c
  25 +++ b/drivers/net/phy/ar40xx.c
  26 @@ -1200,7 +1200,11 @@ ar40xx_init_port(struct ar40xx_priv *pri
  27         ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
  28                         AR40XX_PORT_AUTO_LINK_EN, 0);
  29
  30 -       ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
  31 +       /* CPU port is setting headers to limit output ports */
  32 +       if (port == 0)
  33 +               ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0x8);
  34 +       else
  35 +               ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
  36
  37         ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
  38
  39 @@ -1243,6 +1247,10 @@ ar40xx_init_globals(struct ar40xx_priv *
  40         t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
  41               AR40XX_PORT0_FC_THRESH_OFF_DFLT;
  42         ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
  43 +
  44 +       /* set service tag to 802.1q */
  45 +       t = ETH_P_8021Q | AR40XX_ESS_SERVICE_TAG_STAG;
  46 +       ar40xx_write(priv, AR40XX_ESS_SERVICE_TAG, t);
  47  }
  48
  49  static void
  50 @@ -1568,7 +1576,11 @@ ar40xx_setup_port(struct ar40xx_priv *pr
  51         u32 pvid = priv->vlan_id[priv->pvid[port]];
  52
  53         if (priv->vlan) {
  54 -               egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
  55 +               if (priv->vlan_tagged & BIT(port))
  56 +                       egress = AR40XX_PORT_VLAN1_OUT_MODE_TAG;
  57 +               else
  58 +                       egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
  59 +
  60                 ingress = AR40XX_IN_SECURE;
  61         } else {
  62                 egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
  63 @@ -1579,8 +1591,17 @@ ar40xx_setup_port(struct ar40xx_priv *pr
  64         t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
  65         ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
  66
  67 -       t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
  68 -       t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
  69 +       t = egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
  70 +
  71 +       /* set CPU port to core port */
  72 +       if (port == 0)
  73 +               t |= AR40XX_PORT_VLAN1_CORE_PORT;
  74 +
  75 +       if (priv->vlan_tagged & BIT(port))
  76 +               t |= AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
  77 +       else
  78 +               t |= AR40XX_PORT_VLAN1_PORT_TLS_MODE;
  79 +
  80         ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
  81
  82         t = members;
  83 --- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
  84 +++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
  85 @@ -970,7 +970,6 @@ static int edma_axi_probe(struct platfor
  86                 edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;
  87                 edma_netdev[i]->max_mtu = 9000;
  88                 edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
  89 -                                     | NETIF_F_HW_VLAN_CTAG_TX
  90                                       | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
  91                                       NETIF_F_TSO | NETIF_F_GRO;
  92                 edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
  93 @@ -982,10 +981,10 @@ static int edma_axi_probe(struct platfor
  94                                              NETIF_F_TSO | NETIF_F_GRO;
  95
  96  #ifdef CONFIG_RFS_ACCEL
  97 -               edma_netdev[i]->features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
  98 -               edma_netdev[i]->hw_features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
  99 -               edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
 100 -               edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
 101 +               edma_netdev[i]->features |=  NETIF_F_NTUPLE;
 102 +               edma_netdev[i]->hw_features |=  NETIF_F_NTUPLE;
 103 +               edma_netdev[i]->vlan_features |= NETIF_F_NTUPLE;
 104 +               edma_netdev[i]->wanted_features |= NETIF_F_NTUPLE;
 105  #endif
 106                 edma_set_ethtool_ops(edma_netdev[i]);
 107
 108 --- a/drivers/net/phy/ar40xx.h
 109 +++ b/drivers/net/phy/ar40xx.h
 110 @@ -151,6 +151,9 @@ struct ar40xx_mib_desc {
 111  #define   AR40XX_MIB_FUNC_NO_OP                0x0
 112  #define   AR40XX_MIB_FUNC_FLUSH                0x1
 113
 114 +#define AR40XX_ESS_SERVICE_TAG         0x48
 115 +#define AR40XX_ESS_SERVICE_TAG_STAG    BIT(17)
 116 +
 117  #define AR40XX_REG_PORT_STATUS(_i)             (0x07c + (_i) * 4)
 118  #define   AR40XX_PORT_SPEED                    BITS(0, 2)
 119  #define   AR40XX_PORT_STATUS_SPEED_S   0
 120 @@ -179,6 +182,8 @@ struct ar40xx_mib_desc {
 121  #define   AR40XX_PORT_VLAN0_DEF_CVID_S         16
 122
 123  #define AR40XX_REG_PORT_VLAN1(_i)              (0x424 + (_i) * 0x8)
 124 +#define   AR40XX_PORT_VLAN1_CORE_PORT          BIT(9)
 125 +#define   AR40XX_PORT_VLAN1_PORT_TLS_MODE      BIT(7)
 126  #define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP     BIT(6)
 127  #define   AR40XX_PORT_VLAN1_OUT_MODE           BITS(12, 2)
 128  #define   AR40XX_PORT_VLAN1_OUT_MODE_S         12