1 --- a/drivers/net/phy/Kconfig
2 +++ b/drivers/net/phy/Kconfig
3 @@ -519,6 +519,13 @@ config XILINX_GMII2RGMII
4 the Reduced Gigabit Media Independent Interface(RGMII) between
5 Ethernet physical media devices and the Gigabit Ethernet controller.
8 + tristate "Qualcomm Atheros ipq40xx MDIO interface"
9 + depends on HAS_IOMEM && OF
11 + This driver supports the MDIO interface found in Qualcomm
12 + Atheros ipq40xx Soc chip.
16 config MICREL_KS8995MA
17 --- a/drivers/net/phy/Makefile
18 +++ b/drivers/net/phy/Makefile
19 @@ -48,6 +48,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium
20 obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
21 obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
22 obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
23 +obj-$(CONFIG_MDIO_IPQ40XX) += mdio-ipq40xx.o
24 obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
25 obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
26 obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
28 +++ b/drivers/net/phy/mdio-ipq40xx.c
31 + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
33 + * Permission to use, copy, modify, and/or distribute this software for
34 + * any purpose with or without fee is hereby granted, provided that the
35 + * above copyright notice and this permission notice appear in all copies.
36 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
37 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
38 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
39 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
40 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
41 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
42 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
45 +#include <linux/delay.h>
46 +#include <linux/kernel.h>
47 +#include <linux/module.h>
48 +#include <linux/mutex.h>
49 +#include <linux/io.h>
50 +#include <linux/of_address.h>
51 +#include <linux/of_mdio.h>
52 +#include <linux/phy.h>
53 +#include <linux/platform_device.h>
55 +#define MDIO_CTRL_0_REG 0x40
56 +#define MDIO_CTRL_1_REG 0x44
57 +#define MDIO_CTRL_2_REG 0x48
58 +#define MDIO_CTRL_3_REG 0x4c
59 +#define MDIO_CTRL_4_REG 0x50
60 +#define MDIO_CTRL_4_ACCESS_BUSY BIT(16)
61 +#define MDIO_CTRL_4_ACCESS_START BIT(8)
62 +#define MDIO_CTRL_4_ACCESS_CODE_READ 0
63 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1
64 +#define CTRL_0_REG_DEFAULT_VALUE 0x150FF
66 +#define IPQ40XX_MDIO_RETRY 1000
67 +#define IPQ40XX_MDIO_DELAY 10
69 +struct ipq40xx_mdio_data {
70 + struct mii_bus *mii_bus;
71 + void __iomem *membase;
72 + int phy_irq[PHY_MAX_ADDR];
76 +static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
80 + for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
83 + busy = readl(am->membase + MDIO_CTRL_4_REG) &
84 + MDIO_CTRL_4_ACCESS_BUSY;
88 + /* BUSY might take to be cleard by 15~20 times of loop */
89 + udelay(IPQ40XX_MDIO_DELAY);
92 + dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
97 +static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
99 + struct ipq40xx_mdio_data *am = bus->priv;
101 + unsigned int cmd = 0;
103 + lockdep_assert_held(&bus->mdio_lock);
105 + if (ipq40xx_mdio_wait_busy(am))
108 + /* issue the phy address and reg */
109 + writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
111 + cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
113 + /* issue read command */
114 + writel(cmd, am->membase + MDIO_CTRL_4_REG);
116 + /* Wait read complete */
117 + if (ipq40xx_mdio_wait_busy(am))
121 + value = readl(am->membase + MDIO_CTRL_3_REG);
126 +static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
129 + struct ipq40xx_mdio_data *am = bus->priv;
130 + unsigned int cmd = 0;
132 + lockdep_assert_held(&bus->mdio_lock);
134 + if (ipq40xx_mdio_wait_busy(am))
137 + /* issue the phy address and reg */
138 + writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
140 + /* issue write data */
141 + writel(value, am->membase + MDIO_CTRL_2_REG);
143 + cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
144 + /* issue write command */
145 + writel(cmd, am->membase + MDIO_CTRL_4_REG);
147 + /* Wait write complete */
148 + if (ipq40xx_mdio_wait_busy(am))
154 +static int ipq40xx_mdio_probe(struct platform_device *pdev)
156 + struct ipq40xx_mdio_data *am;
157 + struct resource *res;
160 + am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
164 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
166 + dev_err(&pdev->dev, "no iomem resource found\n");
170 + am->membase = devm_ioremap_resource(&pdev->dev, res);
171 + if (IS_ERR(am->membase)) {
172 + dev_err(&pdev->dev, "unable to ioremap registers\n");
173 + return PTR_ERR(am->membase);
176 + am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
180 + writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
182 + am->mii_bus->name = "ipq40xx_mdio";
183 + am->mii_bus->read = ipq40xx_mdio_read;
184 + am->mii_bus->write = ipq40xx_mdio_write;
185 + am->mii_bus->priv = am;
186 + am->mii_bus->parent = &pdev->dev;
187 + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
189 + for (i = 0; i < PHY_MAX_ADDR; i++)
190 + am->phy_irq[i] = PHY_POLL;
192 + memcpy(am->mii_bus->irq, am->phy_irq, sizeof(am->phy_irq));
193 + am->dev = &pdev->dev;
194 + platform_set_drvdata(pdev, am);
196 + return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
199 +static int ipq40xx_mdio_remove(struct platform_device *pdev)
201 + struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
203 + mdiobus_unregister(am->mii_bus);
208 +static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
209 + { .compatible = "qcom,ipq4019-mdio" },
212 +MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
214 +static struct platform_driver ipq40xx_mdio_driver = {
215 + .probe = ipq40xx_mdio_probe,
216 + .remove = ipq40xx_mdio_remove,
218 + .name = "ipq40xx-mdio",
219 + .of_match_table = ipq40xx_mdio_dt_ids,
223 +module_platform_driver(ipq40xx_mdio_driver);
225 +#define DRV_VERSION "1.0"
227 +MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
228 +MODULE_AUTHOR("Qualcomm Atheros");
229 +MODULE_VERSION(DRV_VERSION);
230 +MODULE_LICENSE("Dual BSD/GPL");