1 #include "qcom-ipq8064-v1.0.dtsi"
4 model = "Qualcomm IPQ8064/AP161";
5 compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
8 reg = <0x42000000 0x1e000000>;
9 device_type = "memory";
17 reg = <0x41200000 0x300000>;
23 serial0 = &gsbi4_serial;
28 stdout-path = "serial0:115200n8";
33 rgmii2_pins: rgmii2_pins {
35 pins = "gpio27", "gpio28", "gpio29",
36 "gpio30", "gpio31", "gpio32",
37 "gpio51", "gpio52", "gpio59",
38 "gpio60", "gpio61", "gpio62",
45 qcom,mode = <GSBI_PROT_I2C_UART>;
52 * The i2c device on gsbi4 should not be enabled.
53 * On ipq806x designs gsbi4 i2c is meant for exclusive
54 * RPM usage. Turning this on in kernel manifests as
55 * i2c failure for the RPM.
60 qcom,mode = <GSBI_PROT_SPI>;
65 spi-max-frequency = <50000000>;
67 pinctrl-0 = <&spi_pins>;
68 pinctrl-names = "default";
70 cs-gpios = <&qcom_pinmux 20 0>;
73 compatible = "s25fl256s1";
76 spi-max-frequency = <50000000>;
80 compatible = "qcom,smem";
118 pinctrl-0 = <&nand_pins>;
119 pinctrl-names = "default";
123 compatible = "qcom,nandcs";
125 nand-ecc-strength = <4>;
126 nand-bus-width = <8>;
127 nand-ecc-step-size = <512>;
130 compatible = "qcom,smem";
138 pinctrl-0 = <&mdio0_pins>;
139 pinctrl-names = "default";
141 phy0: ethernet-phy@0 {
143 qca,ar8327-initvals = <
144 0x00004 0x7600000 /* PAD0_MODE */
145 0x00008 0x1000000 /* PAD5_MODE */
146 0x0000c 0x20080 /* PAD6_MODE */
147 0x000e4 0x6a545 /* MAC_POWER_SEL */
148 0x000e0 0xc74164de /* SGMII_CTRL */
149 0x0007c 0x4e /* PORT0_STATUS */
150 0x00094 0x4e /* PORT6_STATUS */
154 phy4: ethernet-phy@4 {
161 phy3: ethernet-phy@3 {
162 device_type = "ethernet-phy";
172 pinctrl-0 = <&rgmii2_pins>;
173 pinctrl-names = "default";