3 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Qualcomm IPQ8064";
14 compatible = "qcom,ipq8064";
15 interrupt-parent = <&intc>;
19 memory { device_type = "memory"; reg = <0 0>; };
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
30 next-level-cache = <&L2>;
31 qcom,acc = <&acpu0_aux>;
33 clocks = <&kraitcc 0>, <&kraitcc 4>;
34 clock-names = "cpu", "l2";
35 clock-latency = <100000>;
36 cpu-supply = <&smb208_s2a>;
37 operating-points-v2 = <&opp_table0>;
38 voltage-tolerance = <5>;
39 cooling-min-state = <0>;
40 cooling-max-state = <10>;
42 cpu-idle-states = <&CPU_SPC>;
46 compatible = "qcom,krait";
47 enable-method = "qcom,kpss-acc-v1";
50 next-level-cache = <&L2>;
51 qcom,acc = <&acpu1_aux>;
53 clocks = <&kraitcc 1>, <&kraitcc 4>;
54 clock-names = "cpu", "l2";
55 clock-latency = <100000>;
56 cpu-supply = <&smb208_s2b>;
57 operating-points-v2 = <&opp_table0>;
58 voltage-tolerance = <5>;
59 cooling-min-state = <0>;
60 cooling-max-state = <10>;
62 cpu-idle-states = <&CPU_SPC>;
72 qcom,l2-rates = <384000000 1000000000 1200000000>;
73 qcom,l2-cpufreq = <384000000 600000000 1200000000>;
74 qcom,l2-volt = <1100000 1100000 1150000>;
75 qcom,l2-supply = <&smb208_s1a>;
80 compatible = "qcom,idle-state-spc",
83 entry-latency-us = <400>;
84 exit-latency-us = <900>;
85 min-residency-us = <3000>;
90 opp_table0: opp_table0 {
91 compatible = "operating-points-v2-qcom-cpu";
92 nvmem-cells = <&speedbin_efuse>;
95 opp-hz = /bits/ 64 <384000000>;
96 opp-microvolt-speed0-pvs0-v0 = <1000000>;
97 opp-microvolt-speed0-pvs1-v0 = <925000>;
98 opp-microvolt-speed0-pvs2-v0 = <875000>;
99 opp-microvolt-speed0-pvs3-v0 = <800000>;
100 opp-supported-hw = <0x1>;
101 clock-latency-ns = <100000>;
105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt-speed0-pvs0-v0 = <1050000>;
107 opp-microvolt-speed0-pvs1-v0 = <975000>;
108 opp-microvolt-speed0-pvs2-v0 = <925000>;
109 opp-microvolt-speed0-pvs3-v0 = <850000>;
110 opp-supported-hw = <0x1>;
111 clock-latency-ns = <100000>;
115 opp-hz = /bits/ 64 <800000000>;
116 opp-microvolt-speed0-pvs0-v0 = <1100000>;
117 opp-microvolt-speed0-pvs1-v0 = <1025000>;
118 opp-microvolt-speed0-pvs2-v0 = <995000>;
119 opp-microvolt-speed0-pvs3-v0 = <900000>;
120 opp-supported-hw = <0x1>;
121 clock-latency-ns = <100000>;
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt-speed0-pvs0-v0 = <1150000>;
127 opp-microvolt-speed0-pvs1-v0 = <1075000>;
128 opp-microvolt-speed0-pvs2-v0 = <1025000>;
129 opp-microvolt-speed0-pvs3-v0 = <950000>;
130 opp-supported-hw = <0x1>;
131 clock-latency-ns = <100000>;
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt-speed0-pvs0-v0 = <1200000>;
137 opp-microvolt-speed0-pvs1-v0 = <1125000>;
138 opp-microvolt-speed0-pvs2-v0 = <1075000>;
139 opp-microvolt-speed0-pvs3-v0 = <1000000>;
140 opp-supported-hw = <0x1>;
141 clock-latency-ns = <100000>;
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt-speed0-pvs0-v0 = <1250000>;
147 opp-microvolt-speed0-pvs1-v0 = <1175000>;
148 opp-microvolt-speed0-pvs2-v0 = <1125000>;
149 opp-microvolt-speed0-pvs3-v0 = <1050000>;
150 opp-supported-hw = <0x1>;
151 clock-latency-ns = <100000>;
158 polling-delay-passive = <0>;
160 thermal-sensors = <&tsens 0>;
164 temperature = <125000>;
166 type = "critical_high";
170 temperature = <105000>;
172 type = "configurable_hi";
176 temperature = <95000>;
178 type = "configurable_lo";
184 type = "critical_low";
190 polling-delay-passive = <0>;
192 thermal-sensors = <&tsens 1>;
196 temperature = <125000>;
198 type = "critical_high";
202 temperature = <105000>;
204 type = "configurable_hi";
208 temperature = <95000>;
210 type = "configurable_lo";
216 type = "critical_low";
222 polling-delay-passive = <0>;
224 thermal-sensors = <&tsens 2>;
228 temperature = <125000>;
230 type = "critical_high";
234 temperature = <105000>;
236 type = "configurable_hi";
240 temperature = <95000>;
242 type = "configurable_lo";
248 type = "critical_low";
254 polling-delay-passive = <0>;
256 thermal-sensors = <&tsens 3>;
260 temperature = <125000>;
262 type = "critical_high";
266 temperature = <105000>;
268 type = "configurable_hi";
272 temperature = <95000>;
274 type = "configurable_lo";
280 type = "critical_low";
286 polling-delay-passive = <0>;
288 thermal-sensors = <&tsens 4>;
292 temperature = <125000>;
294 type = "critical_high";
298 temperature = <105000>;
300 type = "configurable_hi";
304 temperature = <95000>;
306 type = "configurable_lo";
312 type = "critical_low";
318 polling-delay-passive = <0>;
320 thermal-sensors = <&tsens 5>;
324 temperature = <125000>;
326 type = "critical_high";
330 temperature = <105000>;
332 type = "configurable_hi";
336 temperature = <95000>;
338 type = "configurable_lo";
344 type = "critical_low";
350 polling-delay-passive = <0>;
352 thermal-sensors = <&tsens 6>;
356 temperature = <125000>;
358 type = "critical_high";
362 temperature = <105000>;
364 type = "configurable_hi";
368 temperature = <95000>;
370 type = "configurable_lo";
376 type = "critical_low";
382 polling-delay-passive = <0>;
384 thermal-sensors = <&tsens 7>;
388 temperature = <125000>;
390 type = "critical_high";
394 temperature = <105000>;
396 type = "configurable_hi";
400 temperature = <95000>;
402 type = "configurable_lo";
408 type = "critical_low";
414 polling-delay-passive = <0>;
416 thermal-sensors = <&tsens 8>;
420 temperature = <125000>;
422 type = "critical_high";
426 temperature = <105000>;
428 type = "configurable_hi";
432 temperature = <95000>;
434 type = "configurable_lo";
440 type = "critical_low";
446 polling-delay-passive = <0>;
448 thermal-sensors = <&tsens 9>;
452 temperature = <125000>;
454 type = "critical_high";
458 temperature = <105000>;
460 type = "configurable_hi";
464 temperature = <95000>;
466 type = "configurable_lo";
472 type = "critical_low";
478 polling-delay-passive = <0>;
480 thermal-sensors = <&tsens 10>;
484 temperature = <125000>;
486 type = "critical_high";
490 temperature = <105000>;
492 type = "configurable_hi";
496 temperature = <95000>;
498 type = "configurable_lo";
504 type = "critical_low";
511 compatible = "qcom,krait-pmu";
512 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
513 IRQ_TYPE_LEVEL_HIGH)>;
517 #address-cells = <1>;
522 reg = <0x40000000 0x1000000>;
526 smem: smem@41000000 {
527 reg = <0x41000000 0x200000>;
534 compatible = "fixed-clock";
536 clock-frequency = <25000000>;
540 compatible = "fixed-clock";
542 clock-frequency = <25000000>;
545 sleep_clk: sleep_clk {
546 compatible = "fixed-clock";
547 clock-frequency = <32768>;
553 compatible = "qcom,fab-scaling";
554 clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
555 clock-names = "apps-fab-clk", "ddr-fab-clk";
556 fab_freq_high = <533000000>;
557 fab_freq_nominal = <400000000>;
558 cpu_freq_threshold = <1000000000>;
563 compatible = "qcom,scm-ipq806x";
568 #address-cells = <1>;
571 compatible = "simple-bus";
574 compatible = "qcom,lpass-cpu";
576 clocks = <&lcc AHBIX_CLK>,
579 clock-names = "ahbix-clk",
582 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
583 interrupt-names = "lpass-irq-lpaif";
584 reg = <0x28100000 0x10000>;
585 reg-names = "lpass-lpaif";
588 qfprom: qfprom@700000 {
589 compatible = "qcom,qfprom", "syscon";
590 reg = <0x700000 0x1000>;
591 #address-cells = <1>;
594 tsens_calib: calib@400 {
597 tsens_backup: backup@410 {
600 speedbin_efuse: speedbin@0c0 {
606 compatible = "qcom,rpm-ipq8064";
607 reg = <0x108000 0x1000>;
608 qcom,ipc = <&l2cc 0x8 2>;
610 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "ack",
617 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
620 #address-cells = <1>;
623 rpmcc: clock-controller {
624 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
629 compatible = "qcom,rpm-smb208-regulators";
632 regulator-min-microvolt = <1050000>;
633 regulator-max-microvolt = <1150000>;
635 qcom,switch-mode-frequency = <1200000>;
640 regulator-min-microvolt = <1050000>;
641 regulator-max-microvolt = <1150000>;
643 qcom,switch-mode-frequency = <1200000>;
647 regulator-min-microvolt = < 800000>;
648 regulator-max-microvolt = <1250000>;
650 qcom,switch-mode-frequency = <1200000>;
654 regulator-min-microvolt = < 800000>;
655 regulator-max-microvolt = <1250000>;
657 qcom,switch-mode-frequency = <1200000>;
663 compatible = "qcom,prng";
664 reg = <0x1a500000 0x200>;
665 clocks = <&gcc PRNG_CLK>;
666 clock-names = "core";
669 qcom_pinmux: pinmux@800000 {
670 compatible = "qcom,ipq8064-pinctrl";
671 reg = <0x800000 0x4000>;
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
679 pcie0_pins: pcie0_pinmux {
682 function = "pcie1_rst";
683 drive-strength = <12>;
688 pcie1_pins: pcie1_pinmux {
691 function = "pcie2_rst";
692 drive-strength = <12>;
697 pcie2_pins: pcie2_pinmux {
700 function = "pcie3_rst";
701 drive-strength = <12>;
709 pins = "gpio18", "gpio19", "gpio21";
711 drive-strength = <10>;
716 leds_pins: leds_pins {
718 pins = "gpio7", "gpio8", "gpio9",
721 drive-strength = <2>;
727 buttons_pins: buttons_pins {
730 drive-strength = <2>;
736 intc: interrupt-controller@2000000 {
737 compatible = "qcom,msm-qgic2";
738 interrupt-controller;
739 #interrupt-cells = <3>;
740 reg = <0x02000000 0x1000>,
745 compatible = "qcom,kpss-timer", "qcom,msm-timer";
746 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
747 IRQ_TYPE_EDGE_RISING)>,
748 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
749 IRQ_TYPE_EDGE_RISING)>,
750 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
751 IRQ_TYPE_EDGE_RISING)>,
752 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
753 IRQ_TYPE_EDGE_RISING)>,
754 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
755 IRQ_TYPE_EDGE_RISING)>;
756 reg = <0x0200a000 0x100>;
757 clock-frequency = <25000000>,
759 clocks = <&sleep_clk>;
760 clock-names = "sleep";
761 cpu-offset = <0x80000>;
764 acpu0_aux: clock-controller@2088000 {
765 compatible = "qcom,kpss-acc-v1";
766 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
767 clock-output-names = "acpu0_aux";
770 acpu1_aux: clock-controller@2098000 {
771 compatible = "qcom,kpss-acc-v1";
772 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
773 clock-output-names = "acpu1_aux";
776 l2cc: clock-controller@2011000 {
777 compatible = "qcom,kpss-gcc", "syscon";
778 reg = <0x2011000 0x1000>;
779 clock-output-names = "acpu_l2_aux";
782 kraitcc: clock-controller {
783 compatible = "qcom,krait-cc-v1";
787 saw0: regulator@2089000 {
788 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
789 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
793 saw1: regulator@2099000 {
794 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
795 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
799 saw_l2: regulator@02012000 {
800 compatible = "qcom,saw2", "syscon";
801 reg = <0x02012000 0x1000>;
805 sic_non_secure: sic-non-secure@12100000 {
806 compatible = "syscon";
807 reg = <0x12100000 0x10000>;
810 gsbi2: gsbi@12480000 {
811 compatible = "qcom,gsbi-v1.0.0";
813 reg = <0x12480000 0x100>;
814 clocks = <&gcc GSBI2_H_CLK>;
815 clock-names = "iface";
816 #address-cells = <1>;
821 syscon-tcsr = <&tcsr>;
823 uart2: serial@12490000 {
824 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
825 reg = <0x12490000 0x1000>,
827 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
829 clock-names = "core", "iface";
834 compatible = "qcom,i2c-qup-v1.1.1";
835 reg = <0x124a0000 0x1000>;
836 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
839 clock-names = "core", "iface";
842 #address-cells = <1>;
848 gsbi4: gsbi@16300000 {
849 compatible = "qcom,gsbi-v1.0.0";
851 reg = <0x16300000 0x100>;
852 clocks = <&gcc GSBI4_H_CLK>;
853 clock-names = "iface";
854 #address-cells = <1>;
859 syscon-tcsr = <&tcsr>;
861 gsbi4_serial: serial@16340000 {
862 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
863 reg = <0x16340000 0x1000>,
865 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
867 clock-names = "core", "iface";
872 compatible = "qcom,i2c-qup-v1.1.1";
873 reg = <0x16380000 0x1000>;
874 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
877 clock-names = "core", "iface";
880 #address-cells = <1>;
885 gsbi5: gsbi@1a200000 {
886 compatible = "qcom,gsbi-v1.0.0";
888 reg = <0x1a200000 0x100>;
889 clocks = <&gcc GSBI5_H_CLK>;
890 clock-names = "iface";
891 #address-cells = <1>;
896 syscon-tcsr = <&tcsr>;
898 uart5: serial@1a240000 {
899 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
900 reg = <0x1a240000 0x1000>,
902 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
904 clock-names = "core", "iface";
909 compatible = "qcom,i2c-qup-v1.1.1";
910 reg = <0x1a280000 0x1000>;
911 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
914 clock-names = "core", "iface";
917 #address-cells = <1>;
922 compatible = "qcom,spi-qup-v1.1.1";
923 reg = <0x1a280000 0x1000>;
924 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
927 clock-names = "core", "iface";
930 #address-cells = <1>;
935 gsbi7: gsbi@16600000 {
937 compatible = "qcom,gsbi-v1.0.0";
939 reg = <0x16600000 0x100>;
940 clocks = <&gcc GSBI7_H_CLK>;
941 clock-names = "iface";
942 #address-cells = <1>;
945 syscon-tcsr = <&tcsr>;
947 gsbi7_serial: serial@16640000 {
948 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
949 reg = <0x16640000 0x1000>,
951 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
953 clock-names = "core", "iface";
958 sata_phy: sata-phy@1b400000 {
959 compatible = "qcom,ipq806x-sata-phy";
960 reg = <0x1b400000 0x200>;
962 clocks = <&gcc SATA_PHY_CFG_CLK>;
969 sata: sata@29000000 {
970 compatible = "qcom,ipq806x-ahci", "generic-ahci";
971 reg = <0x29000000 0x180>;
973 ports-implemented = <0x1>;
975 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&gcc SFAB_SATA_S_H_CLK>,
980 <&gcc SATA_RXOOB_CLK>,
981 <&gcc SATA_PMALIVE_CLK>;
982 clock-names = "slave_face", "iface", "core",
985 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
986 assigned-clock-rates = <100000000>, <100000000>;
989 phy-names = "sata-phy";
994 compatible = "qcom,ssbi";
995 reg = <0x00500000 0x1000>;
996 qcom,controller-type = "pmic-arbiter";
999 gcc: clock-controller@900000 {
1000 compatible = "qcom,gcc-ipq8064";
1001 reg = <0x00900000 0x4000>;
1004 #power-domain-cells = <1>;
1007 tsens: thermal-sensor@900000 {
1008 compatible = "qcom,ipq8064-tsens";
1009 reg = <0x900000 0x3680>;
1010 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1011 nvmem-cell-names = "calib", "calib_backup";
1012 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1013 #thermal-sensor-cells = <1>;
1016 tcsr: syscon@1a400000 {
1017 compatible = "qcom,tcsr-ipq8064", "syscon";
1018 reg = <0x1a400000 0x100>;
1021 lcc: clock-controller@28000000 {
1022 compatible = "qcom,lcc-ipq8064";
1023 reg = <0x28000000 0x1000>;
1028 sfpb_mutex_block: syscon@1200600 {
1029 compatible = "syscon";
1030 reg = <0x01200600 0x100>;
1033 hs_phy_0: hs_phy_0 {
1034 compatible = "qcom,dwc3-hs-usb-phy";
1036 clocks = <&gcc USB30_0_UTMI_CLK>;
1037 clock-names = "ref";
1041 ss_phy_0: ss_phy_0 {
1042 compatible = "qcom,dwc3-ss-usb-phy";
1044 clocks = <&gcc USB30_0_MASTER_CLK>;
1045 clock-names = "ref";
1049 usb3_0: usb3@110f8800 {
1050 compatible = "qcom,dwc3", "syscon";
1051 #address-cells = <1>;
1053 reg = <0x110f8800 0x8000>;
1054 clocks = <&gcc USB30_0_MASTER_CLK>;
1055 clock-names = "core";
1059 resets = <&gcc USB30_0_MASTER_RESET>;
1060 reset-names = "master";
1062 status = "disabled";
1064 dwc3_0: dwc3@11000000 {
1065 compatible = "snps,dwc3";
1066 reg = <0x11000000 0xcd00>;
1067 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1068 phys = <&hs_phy_0>, <&ss_phy_0>;
1069 phy-names = "usb2-phy", "usb3-phy";
1071 snps,dis_u3_susphy_quirk;
1075 hs_phy_1: hs_phy_1 {
1076 compatible = "qcom,dwc3-hs-usb-phy";
1078 clocks = <&gcc USB30_1_UTMI_CLK>;
1079 clock-names = "ref";
1083 ss_phy_1: ss_phy_1 {
1084 compatible = "qcom,dwc3-ss-usb-phy";
1086 clocks = <&gcc USB30_1_MASTER_CLK>;
1087 clock-names = "ref";
1091 usb3_1: usb3@100f8800 {
1092 compatible = "qcom,dwc3", "syscon";
1093 #address-cells = <1>;
1095 reg = <0x100f8800 0x8000>;
1096 clocks = <&gcc USB30_1_MASTER_CLK>;
1097 clock-names = "core";
1101 resets = <&gcc USB30_1_MASTER_RESET>;
1102 reset-names = "master";
1104 status = "disabled";
1106 dwc3_1: dwc3@10000000 {
1107 compatible = "snps,dwc3";
1108 reg = <0x10000000 0xcd00>;
1109 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1110 phys = <&hs_phy_1>, <&ss_phy_1>;
1111 phy-names = "usb2-phy", "usb3-phy";
1113 snps,dis_u3_susphy_quirk;
1117 pcie0: pci@1b500000 {
1118 compatible = "qcom,pcie-ipq8064";
1119 reg = <0x1b500000 0x1000
1122 0x0ff00000 0x100000>;
1123 reg-names = "dbi", "elbi", "parf", "config";
1124 device_type = "pci";
1125 linux,pci-domain = <0>;
1126 bus-range = <0x00 0xff>;
1128 #address-cells = <3>;
1131 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1132 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1134 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "msi";
1136 #interrupt-cells = <1>;
1137 interrupt-map-mask = <0 0 0 0x7>;
1138 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1139 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1140 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1141 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1143 clocks = <&gcc PCIE_A_CLK>,
1145 <&gcc PCIE_PHY_CLK>,
1146 <&gcc PCIE_AUX_CLK>,
1147 <&gcc PCIE_ALT_REF_CLK>;
1148 clock-names = "core", "iface", "phy", "aux", "ref";
1150 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1151 assigned-clock-rates = <100000000>;
1153 resets = <&gcc PCIE_ACLK_RESET>,
1154 <&gcc PCIE_HCLK_RESET>,
1155 <&gcc PCIE_POR_RESET>,
1156 <&gcc PCIE_PCI_RESET>,
1157 <&gcc PCIE_PHY_RESET>,
1158 <&gcc PCIE_EXT_RESET>;
1159 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1161 pinctrl-0 = <&pcie0_pins>;
1162 pinctrl-names = "default";
1164 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1166 phy-tx0-term-offset = <7>;
1168 status = "disabled";
1171 pcie1: pci@1b700000 {
1172 compatible = "qcom,pcie-ipq8064";
1173 reg = <0x1b700000 0x1000
1176 0x31f00000 0x100000>;
1177 reg-names = "dbi", "elbi", "parf", "config";
1178 device_type = "pci";
1179 linux,pci-domain = <1>;
1180 bus-range = <0x00 0xff>;
1182 #address-cells = <3>;
1185 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1186 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1188 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1189 interrupt-names = "msi";
1190 #interrupt-cells = <1>;
1191 interrupt-map-mask = <0 0 0 0x7>;
1192 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1193 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1194 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1195 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1197 clocks = <&gcc PCIE_1_A_CLK>,
1198 <&gcc PCIE_1_H_CLK>,
1199 <&gcc PCIE_1_PHY_CLK>,
1200 <&gcc PCIE_1_AUX_CLK>,
1201 <&gcc PCIE_1_ALT_REF_CLK>;
1202 clock-names = "core", "iface", "phy", "aux", "ref";
1204 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1205 assigned-clock-rates = <100000000>;
1207 resets = <&gcc PCIE_1_ACLK_RESET>,
1208 <&gcc PCIE_1_HCLK_RESET>,
1209 <&gcc PCIE_1_POR_RESET>,
1210 <&gcc PCIE_1_PCI_RESET>,
1211 <&gcc PCIE_1_PHY_RESET>,
1212 <&gcc PCIE_1_EXT_RESET>;
1213 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1215 pinctrl-0 = <&pcie1_pins>;
1216 pinctrl-names = "default";
1218 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1220 phy-tx0-term-offset = <7>;
1222 status = "disabled";
1225 pcie2: pci@1b900000 {
1226 compatible = "qcom,pcie-ipq8064";
1227 reg = <0x1b900000 0x1000
1230 0x35f00000 0x100000>;
1231 reg-names = "dbi", "elbi", "parf", "config";
1232 device_type = "pci";
1233 linux,pci-domain = <2>;
1234 bus-range = <0x00 0xff>;
1236 #address-cells = <3>;
1239 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1240 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1243 interrupt-names = "msi";
1244 #interrupt-cells = <1>;
1245 interrupt-map-mask = <0 0 0 0x7>;
1246 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1247 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1248 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1249 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1251 clocks = <&gcc PCIE_2_A_CLK>,
1252 <&gcc PCIE_2_H_CLK>,
1253 <&gcc PCIE_2_PHY_CLK>,
1254 <&gcc PCIE_2_AUX_CLK>,
1255 <&gcc PCIE_2_ALT_REF_CLK>;
1256 clock-names = "core", "iface", "phy", "aux", "ref";
1258 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1259 assigned-clock-rates = <100000000>;
1261 resets = <&gcc PCIE_2_ACLK_RESET>,
1262 <&gcc PCIE_2_HCLK_RESET>,
1263 <&gcc PCIE_2_POR_RESET>,
1264 <&gcc PCIE_2_PCI_RESET>,
1265 <&gcc PCIE_2_PHY_RESET>,
1266 <&gcc PCIE_2_EXT_RESET>;
1267 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1269 pinctrl-0 = <&pcie2_pins>;
1270 pinctrl-names = "default";
1272 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1274 phy-tx0-term-offset = <7>;
1276 status = "disabled";
1279 adm_dma: dma@18300000 {
1280 compatible = "qcom,adm";
1281 reg = <0x18300000 0x100000>;
1282 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1286 clock-names = "core", "iface";
1288 resets = <&gcc ADM0_RESET>,
1289 <&gcc ADM0_PBUS_RESET>,
1290 <&gcc ADM0_C0_RESET>,
1291 <&gcc ADM0_C1_RESET>,
1292 <&gcc ADM0_C2_RESET>;
1293 reset-names = "clk", "pbus", "c0", "c1", "c2";
1296 status = "disabled";
1299 nand_controller: nand-controller@1ac00000 {
1300 compatible = "qcom,ipq806x-nand";
1301 reg = <0x1ac00000 0x800>;
1303 clocks = <&gcc EBI2_CLK>,
1304 <&gcc EBI2_AON_CLK>;
1305 clock-names = "core", "aon";
1307 dmas = <&adm_dma 3>;
1309 qcom,cmd-crci = <15>;
1310 qcom,data-crci = <3>;
1312 status = "disabled";
1314 #address-cells = <1>;
1318 nss_common: syscon@03000000 {
1319 compatible = "syscon";
1320 reg = <0x03000000 0x0000FFFF>;
1323 qsgmii_csr: syscon@1bb00000 {
1324 compatible = "syscon";
1325 reg = <0x1bb00000 0x000001FF>;
1328 stmmac_axi_setup: stmmac-axi-config {
1329 snps,wr_osr_lmt = <7>;
1330 snps,rd_osr_lmt = <7>;
1331 snps,blen = <16 0 0 0 0 0 0>;
1334 mdio0: mdio@37000000 {
1335 #address-cells = <1>;
1338 compatible = "qcom,ipq8064-mdio", "syscon";
1339 reg = <0x37000000 0x200000>;
1340 resets = <&gcc GMAC_CORE1_RESET>;
1341 reset-names = "stmmaceth";
1342 clocks = <&gcc GMAC_CORE1_CLK>;
1343 clock-names = "stmmaceth";
1345 status = "disabled";
1348 gmac0: ethernet@37000000 {
1349 device_type = "network";
1350 compatible = "qcom,ipq806x-gmac";
1351 reg = <0x37000000 0x200000>;
1352 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1353 interrupt-names = "macirq";
1355 snps,axi-config = <&stmmac_axi_setup>;
1359 qcom,nss-common = <&nss_common>;
1360 qcom,qsgmii-csr = <&qsgmii_csr>;
1362 clocks = <&gcc GMAC_CORE1_CLK>;
1363 clock-names = "stmmaceth";
1365 resets = <&gcc GMAC_CORE1_RESET>;
1366 reset-names = "stmmaceth";
1368 status = "disabled";
1371 gmac1: ethernet@37200000 {
1372 device_type = "network";
1373 compatible = "qcom,ipq806x-gmac";
1374 reg = <0x37200000 0x200000>;
1375 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "macirq";
1378 snps,axi-config = <&stmmac_axi_setup>;
1382 qcom,nss-common = <&nss_common>;
1383 qcom,qsgmii-csr = <&qsgmii_csr>;
1385 clocks = <&gcc GMAC_CORE2_CLK>;
1386 clock-names = "stmmaceth";
1388 resets = <&gcc GMAC_CORE2_RESET>;
1389 reset-names = "stmmaceth";
1391 status = "disabled";
1394 gmac2: ethernet@37400000 {
1395 device_type = "network";
1396 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1397 reg = <0x37400000 0x200000>;
1398 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1399 interrupt-names = "macirq";
1401 snps,axi-config = <&stmmac_axi_setup>;
1405 qcom,nss-common = <&nss_common>;
1406 qcom,qsgmii-csr = <&qsgmii_csr>;
1408 clocks = <&gcc GMAC_CORE3_CLK>;
1409 clock-names = "stmmaceth";
1411 resets = <&gcc GMAC_CORE3_RESET>;
1412 reset-names = "stmmaceth";
1414 status = "disabled";
1417 gmac3: ethernet@37600000 {
1418 device_type = "network";
1419 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1420 reg = <0x37600000 0x200000>;
1421 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-names = "macirq";
1424 snps,axi-config = <&stmmac_axi_setup>;
1428 qcom,nss-common = <&nss_common>;
1429 qcom,qsgmii-csr = <&qsgmii_csr>;
1431 clocks = <&gcc GMAC_CORE4_CLK>;
1432 clock-names = "stmmaceth";
1434 resets = <&gcc GMAC_CORE4_RESET>;
1435 reset-names = "stmmaceth";
1437 status = "disabled";
1440 /* Temporary fixed regulator */
1441 vsdcc_fixed: vsdcc-regulator {
1442 compatible = "regulator-fixed";
1443 regulator-name = "SDCC Power";
1444 regulator-min-microvolt = <3300000>;
1445 regulator-max-microvolt = <3300000>;
1446 regulator-always-on;
1449 sdcc1bam: dma@12402000 {
1450 compatible = "qcom,bam-v1.3.0";
1451 reg = <0x12402000 0x8000>;
1452 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&gcc SDC1_H_CLK>;
1454 clock-names = "bam_clk";
1459 sdcc3bam: dma@12182000 {
1460 compatible = "qcom,bam-v1.3.0";
1461 reg = <0x12182000 0x8000>;
1462 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&gcc SDC3_H_CLK>;
1464 clock-names = "bam_clk";
1470 compatible = "arm,amba-bus";
1471 #address-cells = <1>;
1474 sdcc1: sdcc@12400000 {
1475 status = "disabled";
1476 compatible = "arm,pl18x", "arm,primecell";
1477 arm,primecell-periphid = <0x00051180>;
1478 reg = <0x12400000 0x2000>;
1479 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1480 interrupt-names = "cmd_irq";
1481 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1482 clock-names = "mclk", "apb_pclk";
1484 max-frequency = <96000000>;
1488 vmmc-supply = <&vsdcc_fixed>;
1489 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1490 dma-names = "tx", "rx";
1493 sdcc3: sdcc@12180000 {
1494 compatible = "arm,pl18x", "arm,primecell";
1495 arm,primecell-periphid = <0x00051180>;
1496 status = "disabled";
1497 reg = <0x12180000 0x2000>;
1498 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1499 interrupt-names = "cmd_irq";
1500 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1501 clock-names = "mclk", "apb_pclk";
1505 max-frequency = <192000000>;
1509 vqmmc-supply = <&vsdcc_fixed>;
1510 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1511 dma-names = "tx", "rx";
1516 sfpb_mutex: sfpb-mutex {
1517 compatible = "qcom,sfpb-mutex";
1518 syscon = <&sfpb_mutex_block 4 4>;
1520 #hwlock-cells = <1>;
1524 compatible = "qcom,smem";
1525 memory-region = <&smem>;
1526 hwlocks = <&sfpb_mutex 3>;