target/linux/ipq806x/patches/0010-devicetree-bindings-Document-Krait-Scorpion-cpus-and.patch

   1 From 236d07c7bb0c758ea40ea0110d37306d2e7d9a4b Mon Sep 17 00:00:00 2001
   2 From: Rohit Vaswani <rvaswani@codeaurora.org>
   3 Date: Thu, 31 Oct 2013 17:26:33 -0700
   4 Subject: [PATCH 010/182] devicetree: bindings: Document Krait/Scorpion cpus
   5  and enable-method
   6
   7 Scorpion and Krait don't use the spin-table enable-method.
   8 Instead they rely on mmio register accesses to enable power and
   9 clocks to bring CPUs out of reset. Document their enable-methods.
  10
  11 Cc: <devicetree@vger.kernel.org>
  12 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
  13 [sboyd: Split off into separate patch, renamed methods to
  14 match compatible nodes]
  15 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  16 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  17 ---
  18  Documentation/devicetree/bindings/arm/cpus.txt |   25 +++++++++++++++++++++++-
  19  1 file changed, 24 insertions(+), 1 deletion(-)
  20
  21 diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
  22 index 9130435..333f4ae 100644
  23 --- a/Documentation/devicetree/bindings/arm/cpus.txt
  24 +++ b/Documentation/devicetree/bindings/arm/cpus.txt
  25 @@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
  26                           be one of:
  27                              "spin-table"
  28                              "psci"
  29 -                       # On ARM 32-bit systems this property is optional.
  30 +                       # On ARM 32-bit systems this property is optional and
  31 +                         can be one of:
  32 +                           "qcom,gcc-msm8660"
  33 +                           "qcom,kpss-acc-v1"
  34 +                           "qcom,kpss-acc-v2"
  35
  36         - cpu-release-addr
  37                 Usage: required for systems that have an "enable-method"
  38 @@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
  39                           property identifying a 64-bit zero-initialised
  40                           memory location.
  41
  42 +       - qcom,saw
  43 +               Usage: required for systems that have an "enable-method"
  44 +                      property value of "qcom,kpss-acc-v1" or
  45 +                      "qcom,kpss-acc-v2"
  46 +               Value type: <phandle>
  47 +               Definition: Specifies the SAW[1] node associated with this CPU.
  48 +
  49 +       - qcom,acc
  50 +               Usage: required for systems that have an "enable-method"
  51 +                      property value of "qcom,kpss-acc-v1" or
  52 +                      "qcom,kpss-acc-v2"
  53 +               Value type: <phandle>
  54 +               Definition: Specifies the ACC[2] node associated with this CPU.
  55 +
  56 +
  57  Example 1 (dual-cluster big.LITTLE system 32-bit):
  58
  59         cpus {
  60 @@ -382,3 +401,7 @@ cpus {
  61                 cpu-release-addr = <0 0x20000000>;
  62         };
  63  };
  64 +
  65 +--
  66 +[1] arm/msm/qcom,saw2.txt
  67 +[2] arm/msm/qcom,kpss-acc.txt
  68 --
  69 1.7.10.4
  70