1 From 3a4fe9a3a4aff8b1f1c3685bc9b6adbe739d7367 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Thu, 31 Oct 2013 18:20:30 -0700
4 Subject: [PATCH 011/182] devicetree: bindings: Document qcom,kpss-acc
6 The kpss acc binding describes the clock, reset, and power domain
7 controller for a Krait CPU.
9 Cc: <devicetree@vger.kernel.org>
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 Signed-off-by: Kumar Gala <galak@codeaurora.org>
13 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 30 ++++++++++++++++++++
14 1 file changed, 30 insertions(+)
15 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
17 diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
19 index 0000000..1333db9
21 +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
23 +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
25 +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
26 +There is one ACC register region per CPU within the KPSS remapped region as
27 +well as an alias register region that remaps accesses to the ACC associated
28 +with the CPU accessing the region.
34 + Value type: <string>
35 + Definition: should be one of:
41 + Value type: <prop-encoded-array>
42 + Definition: the first element specifies the base address and size of
43 + the register region. An optional second element specifies
44 + the base address and size of the alias register region.
48 + clock-controller@2088000 {
49 + compatible = "qcom,kpss-acc-v2";
50 + reg = <0x02088000 0x1000>,
51 + <0x02008000 0x1000>;