1 From 5a8f026acb4a7a6c6d0c868cc1790363640b9b8f Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <gdjakov@mm-sol.com>
3 Date: Mon, 10 Mar 2014 17:37:12 +0200
4 Subject: [PATCH 047/182] mmc: sdhci-msm: Initial support for Qualcomm
7 This platform driver adds the initial support of Secure Digital Host
8 Controller Interface compliant controller found in Qualcomm chipsets.
10 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
11 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
12 Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
13 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
14 Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
15 Signed-off-by: Chris Ball <chris@printf.net>
17 drivers/mmc/host/Kconfig | 13 +++
18 drivers/mmc/host/Makefile | 1 +
19 drivers/mmc/host/sdhci-msm.c | 208 ++++++++++++++++++++++++++++++++++++++++++
20 3 files changed, 222 insertions(+)
21 create mode 100644 drivers/mmc/host/sdhci-msm.c
23 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
24 index 1384f67..c0ea72a 100644
25 --- a/drivers/mmc/host/Kconfig
26 +++ b/drivers/mmc/host/Kconfig
27 @@ -334,6 +334,19 @@ config MMC_ATMELMCI
32 + tristate "Qualcomm SDHCI Controller Support"
33 + depends on ARCH_QCOM
34 + depends on MMC_SDHCI_PLTFM
36 + This selects the Secure Digital Host Controller Interface (SDHCI)
37 + support present in Qualcomm SOCs. The controller supports
38 + SD/MMC/SDIO devices.
40 + If you have a controller with this interface, say Y or M here.
45 tristate "Qualcomm SDCC Controller Support"
46 depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
47 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
48 index 3483b6b..bbc8445 100644
49 --- a/drivers/mmc/host/Makefile
50 +++ b/drivers/mmc/host/Makefile
51 @@ -64,6 +64,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
52 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
53 obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
54 obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
55 +obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
57 ifeq ($(CONFIG_CB710_DEBUG),y)
58 CFLAGS-cb710-mmc += -DDEBUG
59 diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
61 index 0000000..3b0606f
63 +++ b/drivers/mmc/host/sdhci-msm.c
66 + * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
68 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
70 + * This program is free software; you can redistribute it and/or modify
71 + * it under the terms of the GNU General Public License version 2 and
72 + * only version 2 as published by the Free Software Foundation.
74 + * This program is distributed in the hope that it will be useful,
75 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
76 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77 + * GNU General Public License for more details.
81 +#include <linux/module.h>
82 +#include <linux/of_device.h>
83 +#include <linux/regulator/consumer.h>
84 +#include <linux/delay.h>
86 +#include "sdhci-pltfm.h"
88 +#define CORE_HC_MODE 0x78
89 +#define HC_MODE_EN 0x1
90 +#define CORE_POWER 0x0
91 +#define CORE_SW_RST BIT(7)
94 +struct sdhci_msm_host {
95 + struct platform_device *pdev;
96 + void __iomem *core_mem; /* MSM SDCC mapped address */
97 + struct clk *clk; /* main SD/MMC bus clock */
98 + struct clk *pclk; /* SDHC peripheral bus clock */
99 + struct clk *bus_clk; /* SDHC bus voter clock */
100 + struct mmc_host *mmc;
101 + struct sdhci_pltfm_data sdhci_msm_pdata;
104 +/* Platform specific tuning */
105 +static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
108 + * Tuning is required for SDR104, HS200 and HS400 cards and if the clock
109 + * frequency greater than 100MHz in those modes. The standard tuning
110 + * procedure should not be executed, but a custom implementation will be
111 + * added here instead.
116 +static const struct of_device_id sdhci_msm_dt_match[] = {
117 + { .compatible = "qcom,sdhci-msm-v4" },
121 +MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
123 +static struct sdhci_ops sdhci_msm_ops = {
124 + .platform_execute_tuning = sdhci_msm_execute_tuning,
127 +static int sdhci_msm_probe(struct platform_device *pdev)
129 + struct sdhci_host *host;
130 + struct sdhci_pltfm_host *pltfm_host;
131 + struct sdhci_msm_host *msm_host;
132 + struct resource *core_memres;
136 + msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
140 + msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
141 + host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
143 + return PTR_ERR(host);
145 + pltfm_host = sdhci_priv(host);
146 + pltfm_host->priv = msm_host;
147 + msm_host->mmc = host->mmc;
148 + msm_host->pdev = pdev;
150 + ret = mmc_of_parse(host->mmc);
154 + sdhci_get_of_property(pdev);
156 + /* Setup SDCC bus voter clock. */
157 + msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
158 + if (!IS_ERR(msm_host->bus_clk)) {
159 + /* Vote for max. clk rate for max. performance */
160 + ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
163 + ret = clk_prepare_enable(msm_host->bus_clk);
168 + /* Setup main peripheral bus clock */
169 + msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
170 + if (IS_ERR(msm_host->pclk)) {
171 + ret = PTR_ERR(msm_host->pclk);
172 + dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
173 + goto bus_clk_disable;
176 + ret = clk_prepare_enable(msm_host->pclk);
178 + goto bus_clk_disable;
180 + /* Setup SDC MMC clock */
181 + msm_host->clk = devm_clk_get(&pdev->dev, "core");
182 + if (IS_ERR(msm_host->clk)) {
183 + ret = PTR_ERR(msm_host->clk);
184 + dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
188 + ret = clk_prepare_enable(msm_host->clk);
192 + core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
193 + msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
195 + if (IS_ERR(msm_host->core_mem)) {
196 + dev_err(&pdev->dev, "Failed to remap registers\n");
197 + ret = PTR_ERR(msm_host->core_mem);
201 + /* Reset the core and Enable SDHC mode */
202 + writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
203 + CORE_SW_RST, msm_host->core_mem + CORE_POWER);
205 + /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
206 + usleep_range(1000, 5000);
207 + if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
208 + dev_err(&pdev->dev, "Stuck in reset\n");
213 + /* Set HC_MODE_EN bit in HC_MODE register */
214 + writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
216 + host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
217 + host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
219 + host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
220 + dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
221 + host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
222 + SDHCI_VENDOR_VER_SHIFT));
224 + ret = sdhci_add_host(host);
231 + clk_disable_unprepare(msm_host->clk);
233 + clk_disable_unprepare(msm_host->pclk);
235 + if (!IS_ERR(msm_host->bus_clk))
236 + clk_disable_unprepare(msm_host->bus_clk);
238 + sdhci_pltfm_free(pdev);
242 +static int sdhci_msm_remove(struct platform_device *pdev)
244 + struct sdhci_host *host = platform_get_drvdata(pdev);
245 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
246 + struct sdhci_msm_host *msm_host = pltfm_host->priv;
247 + int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
250 + sdhci_remove_host(host, dead);
251 + sdhci_pltfm_free(pdev);
252 + clk_disable_unprepare(msm_host->clk);
253 + clk_disable_unprepare(msm_host->pclk);
254 + if (!IS_ERR(msm_host->bus_clk))
255 + clk_disable_unprepare(msm_host->bus_clk);
259 +static struct platform_driver sdhci_msm_driver = {
260 + .probe = sdhci_msm_probe,
261 + .remove = sdhci_msm_remove,
263 + .name = "sdhci_msm",
264 + .owner = THIS_MODULE,
265 + .of_match_table = sdhci_msm_dt_match,
269 +module_platform_driver(sdhci_msm_driver);
271 +MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
272 +MODULE_LICENSE("GPL v2");