projects / openwrt / openwrt.git / blob
? search:


64993a3e8cc7422c22cd9bf2beedd06b4619b823
[openwrt/openwrt.git] / target / linux / ipq806x / patches / 0060-i2c-qup-New-bus-driver-for-the-Qualcomm-QUP-I2C-cont.patch
1 From 226eff10dc11af5d6b1bc31e5cedc079aa564fb3 Mon Sep 17 00:00:00 2001
2 From: Bjorn Andersson <bjorn.andersson@sonymobile.com>
3 Date: Thu, 13 Mar 2014 19:07:43 -0700
4 Subject: [PATCH 060/182] i2c: qup: New bus driver for the Qualcomm QUP I2C
5 controller
6
7 This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
8 The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
9 engine with input/output FIFOs and an embedded i2c mini-core. The driver
10 supports FIFO mode (for low bandwidth applications) and block mode (interrupt
11 generated for each block-size data transfer).
12
13 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
14 Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
15 Reviewed-by: Andy Gross <agross@codeaurora.org>
16 Tested-by: Philip Elcan <pelcan@codeaurora.org>
17 [wsa: removed needless IS_ERR_VALUE]
18 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
19 ---
20 drivers/i2c/busses/Kconfig | 10 +
21 drivers/i2c/busses/Makefile | 1 +
22 drivers/i2c/busses/i2c-qup.c | 768 ++++++++++++++++++++++++++++++++++++++++++
23 3 files changed, 779 insertions(+)
24 create mode 100644 drivers/i2c/busses/i2c-qup.c
25
26 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
27 index de17c55..1886315 100644
28 --- a/drivers/i2c/busses/Kconfig
29 +++ b/drivers/i2c/busses/Kconfig
30 @@ -648,6 +648,16 @@ config I2C_PXA_SLAVE
31 is necessary for systems where the PXA may be a target on the
32 I2C bus.
33
34 +config I2C_QUP
35 + tristate "Qualcomm QUP based I2C controller"
36 + depends on ARCH_QCOM
37 + help
38 + If you say yes to this option, support will be included for the
39 + built-in I2C interface on the Qualcomm SoCs.
40 +
41 + This driver can also be built as a module. If so, the module
42 + will be called i2c-qup.
43 +
44 config I2C_RIIC
45 tristate "Renesas RIIC adapter"
46 depends on ARCH_SHMOBILE || COMPILE_TEST
47 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
48 index a08931f..bf2257b 100644
49 --- a/drivers/i2c/busses/Makefile
50 +++ b/drivers/i2c/busses/Makefile
51 @@ -63,6 +63,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
52 obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
53 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
54 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
55 +obj-$(CONFIG_I2C_QUP) += i2c-qup.o
56 obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
57 obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
58 obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
59 diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
60 new file mode 100644
61 index 0000000..c9d5f78
62 --- /dev/null
63 +++ b/drivers/i2c/busses/i2c-qup.c
64 @@ -0,0 +1,768 @@
65 +/*
66 + * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
67 + * Copyright (c) 2014, Sony Mobile Communications AB.
68 + *
69 + *
70 + * This program is free software; you can redistribute it and/or modify
71 + * it under the terms of the GNU General Public License version 2 and
72 + * only version 2 as published by the Free Software Foundation.
73 + *
74 + * This program is distributed in the hope that it will be useful,
75 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
76 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77 + * GNU General Public License for more details.
78 + *
79 + */
80 +
81 +#include <linux/clk.h>
82 +#include <linux/delay.h>
83 +#include <linux/err.h>
84 +#include <linux/i2c.h>
85 +#include <linux/interrupt.h>
86 +#include <linux/io.h>
87 +#include <linux/module.h>
88 +#include <linux/of.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/pm_runtime.h>
91 +
92 +/* QUP Registers */
93 +#define QUP_CONFIG 0x000
94 +#define QUP_STATE 0x004
95 +#define QUP_IO_MODE 0x008
96 +#define QUP_SW_RESET 0x00c
97 +#define QUP_OPERATIONAL 0x018
98 +#define QUP_ERROR_FLAGS 0x01c
99 +#define QUP_ERROR_FLAGS_EN 0x020
100 +#define QUP_HW_VERSION 0x030
101 +#define QUP_MX_OUTPUT_CNT 0x100
102 +#define QUP_OUT_FIFO_BASE 0x110
103 +#define QUP_MX_WRITE_CNT 0x150
104 +#define QUP_MX_INPUT_CNT 0x200
105 +#define QUP_MX_READ_CNT 0x208
106 +#define QUP_IN_FIFO_BASE 0x218
107 +#define QUP_I2C_CLK_CTL 0x400
108 +#define QUP_I2C_STATUS 0x404
109 +
110 +/* QUP States and reset values */
111 +#define QUP_RESET_STATE 0
112 +#define QUP_RUN_STATE 1
113 +#define QUP_PAUSE_STATE 3
114 +#define QUP_STATE_MASK 3
115 +
116 +#define QUP_STATE_VALID BIT(2)
117 +#define QUP_I2C_MAST_GEN BIT(4)
118 +
119 +#define QUP_OPERATIONAL_RESET 0x000ff0
120 +#define QUP_I2C_STATUS_RESET 0xfffffc
121 +
122 +/* QUP OPERATIONAL FLAGS */
123 +#define QUP_I2C_NACK_FLAG BIT(3)
124 +#define QUP_OUT_NOT_EMPTY BIT(4)
125 +#define QUP_IN_NOT_EMPTY BIT(5)
126 +#define QUP_OUT_FULL BIT(6)
127 +#define QUP_OUT_SVC_FLAG BIT(8)
128 +#define QUP_IN_SVC_FLAG BIT(9)
129 +#define QUP_MX_OUTPUT_DONE BIT(10)
130 +#define QUP_MX_INPUT_DONE BIT(11)
131 +
132 +/* I2C mini core related values */
133 +#define QUP_CLOCK_AUTO_GATE BIT(13)
134 +#define I2C_MINI_CORE (2 << 8)
135 +#define I2C_N_VAL 15
136 +/* Most significant word offset in FIFO port */
137 +#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
138 +
139 +/* Packing/Unpacking words in FIFOs, and IO modes */
140 +#define QUP_OUTPUT_BLK_MODE (1 << 10)
141 +#define QUP_INPUT_BLK_MODE (1 << 12)
142 +#define QUP_UNPACK_EN BIT(14)
143 +#define QUP_PACK_EN BIT(15)
144 +
145 +#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
146 +
147 +#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
148 +#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
149 +#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
150 +#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
151 +
152 +/* QUP tags */
153 +#define QUP_TAG_START (1 << 8)
154 +#define QUP_TAG_DATA (2 << 8)
155 +#define QUP_TAG_STOP (3 << 8)
156 +#define QUP_TAG_REC (4 << 8)
157 +
158 +/* Status, Error flags */
159 +#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
160 +#define I2C_STATUS_BUS_ACTIVE BIT(8)
161 +#define I2C_STATUS_ERROR_MASK 0x38000fc
162 +#define QUP_STATUS_ERROR_FLAGS 0x7c
163 +
164 +#define QUP_READ_LIMIT 256
165 +
166 +struct qup_i2c_dev {
167 + struct device *dev;
168 + void __iomem *base;
169 + int irq;
170 + struct clk *clk;
171 + struct clk *pclk;
172 + struct i2c_adapter adap;
173 +
174 + int clk_ctl;
175 + int out_fifo_sz;
176 + int in_fifo_sz;
177 + int out_blk_sz;
178 + int in_blk_sz;
179 +
180 + unsigned long one_byte_t;
181 +
182 + struct i2c_msg *msg;
183 + /* Current posion in user message buffer */
184 + int pos;
185 + /* I2C protocol errors */
186 + u32 bus_err;
187 + /* QUP core errors */
188 + u32 qup_err;
189 +
190 + struct completion xfer;
191 +};
192 +
193 +static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
194 +{
195 + struct qup_i2c_dev *qup = dev;
196 + u32 bus_err;
197 + u32 qup_err;
198 + u32 opflags;
199 +
200 + bus_err = readl(qup->base + QUP_I2C_STATUS);
201 + qup_err = readl(qup->base + QUP_ERROR_FLAGS);
202 + opflags = readl(qup->base + QUP_OPERATIONAL);
203 +
204 + if (!qup->msg) {
205 + /* Clear Error interrupt */
206 + writel(QUP_RESET_STATE, qup->base + QUP_STATE);
207 + return IRQ_HANDLED;
208 + }
209 +
210 + bus_err &= I2C_STATUS_ERROR_MASK;
211 + qup_err &= QUP_STATUS_ERROR_FLAGS;
212 +
213 + if (qup_err) {
214 + /* Clear Error interrupt */
215 + writel(qup_err, qup->base + QUP_ERROR_FLAGS);
216 + goto done;
217 + }
218 +
219 + if (bus_err) {
220 + /* Clear Error interrupt */
221 + writel(QUP_RESET_STATE, qup->base + QUP_STATE);
222 + goto done;
223 + }
224 +
225 + if (opflags & QUP_IN_SVC_FLAG)
226 + writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
227 +
228 + if (opflags & QUP_OUT_SVC_FLAG)
229 + writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
230 +
231 +done:
232 + qup->qup_err = qup_err;
233 + qup->bus_err = bus_err;
234 + complete(&qup->xfer);
235 + return IRQ_HANDLED;
236 +}
237 +
238 +static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
239 + u32 req_state, u32 req_mask)
240 +{
241 + int retries = 1;
242 + u32 state;
243 +
244 + /*
245 + * State transition takes 3 AHB clocks cycles + 3 I2C master clock
246 + * cycles. So retry once after a 1uS delay.
247 + */
248 + do {
249 + state = readl(qup->base + QUP_STATE);
250 +
251 + if (state & QUP_STATE_VALID &&
252 + (state & req_mask) == req_state)
253 + return 0;
254 +
255 + udelay(1);
256 + } while (retries--);
257 +
258 + return -ETIMEDOUT;
259 +}
260 +
261 +static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
262 +{
263 + return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
264 +}
265 +
266 +static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
267 +{
268 + return qup_i2c_poll_state_mask(qup, 0, 0);
269 +}
270 +
271 +static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
272 +{
273 + return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
274 +}
275 +
276 +static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
277 +{
278 + if (qup_i2c_poll_state_valid(qup) != 0)
279 + return -EIO;
280 +
281 + writel(state, qup->base + QUP_STATE);
282 +
283 + if (qup_i2c_poll_state(qup, state) != 0)
284 + return -EIO;
285 + return 0;
286 +}
287 +
288 +static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
289 +{
290 + unsigned long timeout;
291 + u32 opflags;
292 + u32 status;
293 +
294 + timeout = jiffies + HZ;
295 +
296 + for (;;) {
297 + opflags = readl(qup->base + QUP_OPERATIONAL);
298 + status = readl(qup->base + QUP_I2C_STATUS);
299 +
300 + if (!(opflags & QUP_OUT_NOT_EMPTY) &&
301 + !(status & I2C_STATUS_BUS_ACTIVE))
302 + return 0;
303 +
304 + if (time_after(jiffies, timeout))
305 + return -ETIMEDOUT;
306 +
307 + usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
308 + }
309 +}
310 +
311 +static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
312 +{
313 + /* Number of entries to shift out, including the start */
314 + int total = msg->len + 1;
315 +
316 + if (total < qup->out_fifo_sz) {
317 + /* FIFO mode */
318 + writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
319 + writel(total, qup->base + QUP_MX_WRITE_CNT);
320 + } else {
321 + /* BLOCK mode (transfer data on chunks) */
322 + writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
323 + qup->base + QUP_IO_MODE);
324 + writel(total, qup->base + QUP_MX_OUTPUT_CNT);
325 + }
326 +}
327 +
328 +static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
329 +{
330 + u32 addr = msg->addr << 1;
331 + u32 qup_tag;
332 + u32 opflags;
333 + int idx;
334 + u32 val;
335 +
336 + if (qup->pos == 0) {
337 + val = QUP_TAG_START | addr;
338 + idx = 1;
339 + } else {
340 + val = 0;
341 + idx = 0;
342 + }
343 +
344 + while (qup->pos < msg->len) {
345 + /* Check that there's space in the FIFO for our pair */
346 + opflags = readl(qup->base + QUP_OPERATIONAL);
347 + if (opflags & QUP_OUT_FULL)
348 + break;
349 +
350 + if (qup->pos == msg->len - 1)
351 + qup_tag = QUP_TAG_STOP;
352 + else
353 + qup_tag = QUP_TAG_DATA;
354 +
355 + if (idx & 1)
356 + val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
357 + else
358 + val = qup_tag | msg->buf[qup->pos];
359 +
360 + /* Write out the pair and the last odd value */
361 + if (idx & 1 || qup->pos == msg->len - 1)
362 + writel(val, qup->base + QUP_OUT_FIFO_BASE);
363 +
364 + qup->pos++;
365 + idx++;
366 + }
367 +}
368 +
369 +static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
370 +{
371 + unsigned long left;
372 + int ret;
373 +
374 + qup->msg = msg;
375 + qup->pos = 0;
376 +
377 + enable_irq(qup->irq);
378 +
379 + qup_i2c_set_write_mode(qup, msg);
380 +
381 + ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
382 + if (ret)
383 + goto err;
384 +
385 + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
386 +
387 + do {
388 + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
389 + if (ret)
390 + goto err;
391 +
392 + qup_i2c_issue_write(qup, msg);
393 +
394 + ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
395 + if (ret)
396 + goto err;
397 +
398 + left = wait_for_completion_timeout(&qup->xfer, HZ);
399 + if (!left) {
400 + writel(1, qup->base + QUP_SW_RESET);
401 + ret = -ETIMEDOUT;
402 + goto err;
403 + }
404 +
405 + if (qup->bus_err || qup->qup_err) {
406 + if (qup->bus_err & QUP_I2C_NACK_FLAG)
407 + dev_err(qup->dev, "NACK from %x\n", msg->addr);
408 + ret = -EIO;
409 + goto err;
410 + }
411 + } while (qup->pos < msg->len);
412 +
413 + /* Wait for the outstanding data in the fifo to drain */
414 + ret = qup_i2c_wait_writeready(qup);
415 +
416 +err:
417 + disable_irq(qup->irq);
418 + qup->msg = NULL;
419 +
420 + return ret;
421 +}
422 +
423 +static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
424 +{
425 + if (len < qup->in_fifo_sz) {
426 + /* FIFO mode */
427 + writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
428 + writel(len, qup->base + QUP_MX_READ_CNT);
429 + } else {
430 + /* BLOCK mode (transfer data on chunks) */
431 + writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
432 + qup->base + QUP_IO_MODE);
433 + writel(len, qup->base + QUP_MX_INPUT_CNT);
434 + }
435 +}
436 +
437 +static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
438 +{
439 + u32 addr, len, val;
440 +
441 + addr = (msg->addr << 1) | 1;
442 +
443 + /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
444 + len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
445 +
446 + val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
447 + writel(val, qup->base + QUP_OUT_FIFO_BASE);
448 +}
449 +
450 +
451 +static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
452 +{
453 + u32 opflags;
454 + u32 val = 0;
455 + int idx;
456 +
457 + for (idx = 0; qup->pos < msg->len; idx++) {
458 + if ((idx & 1) == 0) {
459 + /* Check that FIFO have data */
460 + opflags = readl(qup->base + QUP_OPERATIONAL);
461 + if (!(opflags & QUP_IN_NOT_EMPTY))
462 + break;
463 +
464 + /* Reading 2 words at time */
465 + val = readl(qup->base + QUP_IN_FIFO_BASE);
466 +
467 + msg->buf[qup->pos++] = val & 0xFF;
468 + } else {
469 + msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
470 + }
471 + }
472 +}
473 +
474 +static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
475 +{
476 + unsigned long left;
477 + int ret;
478 +
479 + /*
480 + * The QUP block will issue a NACK and STOP on the bus when reaching
481 + * the end of the read, the length of the read is specified as one byte
482 + * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
483 + */
484 + if (msg->len > QUP_READ_LIMIT) {
485 + dev_err(qup->dev, "HW not capable of reads over %d bytes\n",
486 + QUP_READ_LIMIT);
487 + return -EINVAL;
488 + }
489 +
490 + qup->msg = msg;
491 + qup->pos = 0;
492 +
493 + enable_irq(qup->irq);
494 +
495 + qup_i2c_set_read_mode(qup, msg->len);
496 +
497 + ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
498 + if (ret)
499 + goto err;
500 +
501 + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
502 +
503 + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
504 + if (ret)
505 + goto err;
506 +
507 + qup_i2c_issue_read(qup, msg);
508 +
509 + ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
510 + if (ret)
511 + goto err;
512 +
513 + do {
514 + left = wait_for_completion_timeout(&qup->xfer, HZ);
515 + if (!left) {
516 + writel(1, qup->base + QUP_SW_RESET);
517 + ret = -ETIMEDOUT;
518 + goto err;
519 + }
520 +
521 + if (qup->bus_err || qup->qup_err) {
522 + if (qup->bus_err & QUP_I2C_NACK_FLAG)
523 + dev_err(qup->dev, "NACK from %x\n", msg->addr);
524 + ret = -EIO;
525 + goto err;
526 + }
527 +
528 + qup_i2c_read_fifo(qup, msg);
529 + } while (qup->pos < msg->len);
530 +
531 +err:
532 + disable_irq(qup->irq);
533 + qup->msg = NULL;
534 +
535 + return ret;
536 +}
537 +
538 +static int qup_i2c_xfer(struct i2c_adapter *adap,
539 + struct i2c_msg msgs[],
540 + int num)
541 +{
542 + struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
543 + int ret, idx;
544 +
545 + ret = pm_runtime_get_sync(qup->dev);
546 + if (ret)
547 + goto out;
548 +
549 + writel(1, qup->base + QUP_SW_RESET);
550 + ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
551 + if (ret)
552 + goto out;
553 +
554 + /* Configure QUP as I2C mini core */
555 + writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
556 +
557 + for (idx = 0; idx < num; idx++) {
558 + if (msgs[idx].len == 0) {
559 + ret = -EINVAL;
560 + goto out;
561 + }
562 +
563 + if (qup_i2c_poll_state_i2c_master(qup)) {
564 + ret = -EIO;
565 + goto out;
566 + }
567 +
568 + if (msgs[idx].flags & I2C_M_RD)
569 + ret = qup_i2c_read_one(qup, &msgs[idx]);
570 + else
571 + ret = qup_i2c_write_one(qup, &msgs[idx]);
572 +
573 + if (ret)
574 + break;
575 +
576 + ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
577 + if (ret)
578 + break;
579 + }
580 +
581 + if (ret == 0)
582 + ret = num;
583 +out:
584 +
585 + pm_runtime_mark_last_busy(qup->dev);
586 + pm_runtime_put_autosuspend(qup->dev);
587 +
588 + return ret;
589 +}
590 +
591 +static u32 qup_i2c_func(struct i2c_adapter *adap)
592 +{
593 + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
594 +}
595 +
596 +static const struct i2c_algorithm qup_i2c_algo = {
597 + .master_xfer = qup_i2c_xfer,
598 + .functionality = qup_i2c_func,
599 +};
600 +
601 +static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
602 +{
603 + clk_prepare_enable(qup->clk);
604 + clk_prepare_enable(qup->pclk);
605 +}
606 +
607 +static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
608 +{
609 + u32 config;
610 +
611 + qup_i2c_change_state(qup, QUP_RESET_STATE);
612 + clk_disable_unprepare(qup->clk);
613 + config = readl(qup->base + QUP_CONFIG);
614 + config |= QUP_CLOCK_AUTO_GATE;
615 + writel(config, qup->base + QUP_CONFIG);
616 + clk_disable_unprepare(qup->pclk);
617 +}
618 +
619 +static int qup_i2c_probe(struct platform_device *pdev)
620 +{
621 + static const int blk_sizes[] = {4, 16, 32};
622 + struct device_node *node = pdev->dev.of_node;
623 + struct qup_i2c_dev *qup;
624 + unsigned long one_bit_t;
625 + struct resource *res;
626 + u32 io_mode, hw_ver, size;
627 + int ret, fs_div, hs_div;
628 + int src_clk_freq;
629 + int clk_freq = 100000;
630 +
631 + qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
632 + if (!qup)
633 + return -ENOMEM;
634 +
635 + qup->dev = &pdev->dev;
636 + init_completion(&qup->xfer);
637 + platform_set_drvdata(pdev, qup);
638 +
639 + of_property_read_u32(node, "clock-frequency", &clk_freq);
640 +
641 + /* We support frequencies up to FAST Mode (400KHz) */
642 + if (!clk_freq || clk_freq > 400000) {
643 + dev_err(qup->dev, "clock frequency not supported %d\n",
644 + clk_freq);
645 + return -EINVAL;
646 + }
647 +
648 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 + qup->base = devm_ioremap_resource(qup->dev, res);
650 + if (IS_ERR(qup->base))
651 + return PTR_ERR(qup->base);
652 +
653 + qup->irq = platform_get_irq(pdev, 0);
654 + if (qup->irq < 0) {
655 + dev_err(qup->dev, "No IRQ defined\n");
656 + return qup->irq;
657 + }
658 +
659 + qup->clk = devm_clk_get(qup->dev, "core");
660 + if (IS_ERR(qup->clk)) {
661 + dev_err(qup->dev, "Could not get core clock\n");
662 + return PTR_ERR(qup->clk);
663 + }
664 +
665 + qup->pclk = devm_clk_get(qup->dev, "iface");
666 + if (IS_ERR(qup->pclk)) {
667 + dev_err(qup->dev, "Could not get iface clock\n");
668 + return PTR_ERR(qup->pclk);
669 + }
670 +
671 + qup_i2c_enable_clocks(qup);
672 +
673 + /*
674 + * Bootloaders might leave a pending interrupt on certain QUP's,
675 + * so we reset the core before registering for interrupts.
676 + */
677 + writel(1, qup->base + QUP_SW_RESET);
678 + ret = qup_i2c_poll_state_valid(qup);
679 + if (ret)
680 + goto fail;
681 +
682 + ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
683 + IRQF_TRIGGER_HIGH, "i2c_qup", qup);
684 + if (ret) {
685 + dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
686 + goto fail;
687 + }
688 + disable_irq(qup->irq);
689 +
690 + hw_ver = readl(qup->base + QUP_HW_VERSION);
691 + dev_dbg(qup->dev, "Revision %x\n", hw_ver);
692 +
693 + io_mode = readl(qup->base + QUP_IO_MODE);
694 +
695 + /*
696 + * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
697 + * associated with each byte written/received
698 + */
699 + size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
700 + if (size > ARRAY_SIZE(blk_sizes))
701 + return -EIO;
702 + qup->out_blk_sz = blk_sizes[size] / 2;
703 +
704 + size = QUP_INPUT_BLOCK_SIZE(io_mode);
705 + if (size > ARRAY_SIZE(blk_sizes))
706 + return -EIO;
707 + qup->in_blk_sz = blk_sizes[size] / 2;
708 +
709 + size = QUP_OUTPUT_FIFO_SIZE(io_mode);
710 + qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
711 +
712 + size = QUP_INPUT_FIFO_SIZE(io_mode);
713 + qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
714 +
715 + src_clk_freq = clk_get_rate(qup->clk);
716 + fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
717 + hs_div = 3;
718 + qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
719 +
720 + /*
721 + * Time it takes for a byte to be clocked out on the bus.
722 + * Each byte takes 9 clock cycles (8 bits + 1 ack).
723 + */
724 + one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
725 + qup->one_byte_t = one_bit_t * 9;
726 +
727 + dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
728 + qup->in_blk_sz, qup->in_fifo_sz,
729 + qup->out_blk_sz, qup->out_fifo_sz);
730 +
731 + i2c_set_adapdata(&qup->adap, qup);
732 + qup->adap.algo = &qup_i2c_algo;
733 + qup->adap.dev.parent = qup->dev;
734 + qup->adap.dev.of_node = pdev->dev.of_node;
735 + strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
736 +
737 + ret = i2c_add_adapter(&qup->adap);
738 + if (ret)
739 + goto fail;
740 +
741 + pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
742 + pm_runtime_use_autosuspend(qup->dev);
743 + pm_runtime_set_active(qup->dev);
744 + pm_runtime_enable(qup->dev);
745 + return 0;
746 +
747 +fail:
748 + qup_i2c_disable_clocks(qup);
749 + return ret;
750 +}
751 +
752 +static int qup_i2c_remove(struct platform_device *pdev)
753 +{
754 + struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
755 +
756 + disable_irq(qup->irq);
757 + qup_i2c_disable_clocks(qup);
758 + i2c_del_adapter(&qup->adap);
759 + pm_runtime_disable(qup->dev);
760 + pm_runtime_set_suspended(qup->dev);
761 + return 0;
762 +}
763 +
764 +#ifdef CONFIG_PM
765 +static int qup_i2c_pm_suspend_runtime(struct device *device)
766 +{
767 + struct qup_i2c_dev *qup = dev_get_drvdata(device);
768 +
769 + dev_dbg(device, "pm_runtime: suspending...\n");
770 + qup_i2c_disable_clocks(qup);
771 + return 0;
772 +}
773 +
774 +static int qup_i2c_pm_resume_runtime(struct device *device)
775 +{
776 + struct qup_i2c_dev *qup = dev_get_drvdata(device);
777 +
778 + dev_dbg(device, "pm_runtime: resuming...\n");
779 + qup_i2c_enable_clocks(qup);
780 + return 0;
781 +}
782 +#endif
783 +
784 +#ifdef CONFIG_PM_SLEEP
785 +static int qup_i2c_suspend(struct device *device)
786 +{
787 + qup_i2c_pm_suspend_runtime(device);
788 + return 0;
789 +}
790 +
791 +static int qup_i2c_resume(struct device *device)
792 +{
793 + qup_i2c_pm_resume_runtime(device);
794 + pm_runtime_mark_last_busy(device);
795 + pm_request_autosuspend(device);
796 + return 0;
797 +}
798 +#endif
799 +
800 +static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
801 + SET_SYSTEM_SLEEP_PM_OPS(
802 + qup_i2c_suspend,
803 + qup_i2c_resume)
804 + SET_RUNTIME_PM_OPS(
805 + qup_i2c_pm_suspend_runtime,
806 + qup_i2c_pm_resume_runtime,
807 + NULL)
808 +};
809 +
810 +static const struct of_device_id qup_i2c_dt_match[] = {
811 + { .compatible = "qcom,i2c-qup-v1.1.1" },
812 + { .compatible = "qcom,i2c-qup-v2.1.1" },
813 + { .compatible = "qcom,i2c-qup-v2.2.1" },
814 + {}
815 +};
816 +MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
817 +
818 +static struct platform_driver qup_i2c_driver = {
819 + .probe = qup_i2c_probe,
820 + .remove = qup_i2c_remove,
821 + .driver = {
822 + .name = "i2c_qup",
823 + .owner = THIS_MODULE,
824 + .pm = &qup_i2c_qup_pm_ops,
825 + .of_match_table = qup_i2c_dt_match,
826 + },
827 +};
828 +
829 +module_platform_driver(qup_i2c_driver);
830 +
831 +MODULE_LICENSE("GPL v2");
832 +MODULE_ALIAS("platform:i2c_qup");
833 --
834 1.7.10.4
835
OpenWrt Source Repository