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[openwrt/openwrt.git] / target / linux / ipq806x / patches / 0065-spi-Add-Qualcomm-QUP-SPI-controller-support.patch
1 From 24884115a6029995dba2561b1ee810f28a34271a Mon Sep 17 00:00:00 2001
2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
3 Date: Thu, 13 Feb 2014 18:21:38 +0200
4 Subject: [PATCH 065/182] spi: Add Qualcomm QUP SPI controller support
5
6 Qualcomm Universal Peripheral (QUP) core is an AHB slave that
7 provides a common data path (an output FIFO and an input FIFO)
8 for serial peripheral interface (SPI) mini-core. SPI in master
9 mode supports up to 50MHz, up to four chip selects, programmable
10 data path from 4 bits to 32 bits and numerous protocol variants.
11
12 Cc: Alok Chauhan <alokc@codeaurora.org>
13 Cc: Gilad Avidov <gavidov@codeaurora.org>
14 Cc: Kiran Gunda <kgunda@codeaurora.org>
15 Cc: Sagar Dharia <sdharia@codeaurora.org>
16 Cc: dsneddon@codeaurora.org
17 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
18 Signed-off-by: Mark Brown <broonie@linaro.org>
19 ---
20 drivers/spi/Kconfig | 13 +
21 drivers/spi/Makefile | 1 +
22 drivers/spi/spi-qup.c | 837 +++++++++++++++++++++++++++++++++++++++++++++++++
23 3 files changed, 851 insertions(+)
24 create mode 100644 drivers/spi/spi-qup.c
25
26 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
27 index 581ee2a..9e9e3ed 100644
28 --- a/drivers/spi/Kconfig
29 +++ b/drivers/spi/Kconfig
30 @@ -381,6 +381,19 @@ config SPI_RSPI
31 help
32 SPI driver for Renesas RSPI and QSPI blocks.
33
34 +config SPI_QUP
35 + tristate "Qualcomm SPI controller with QUP interface"
36 + depends on ARCH_MSM_DT
37 + help
38 + Qualcomm Universal Peripheral (QUP) core is an AHB slave that
39 + provides a common data path (an output FIFO and an input FIFO)
40 + for serial peripheral interface (SPI) mini-core. SPI in master
41 + mode supports up to 50MHz, up to four chip selects, programmable
42 + data path from 4 bits to 32 bits and numerous protocol variants.
43 +
44 + This driver can also be built as a module. If so, the module
45 + will be called spi_qup.
46 +
47 config SPI_S3C24XX
48 tristate "Samsung S3C24XX series SPI"
49 depends on ARCH_S3C24XX
50 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
51 index 95af48d..e598147 100644
52 --- a/drivers/spi/Makefile
53 +++ b/drivers/spi/Makefile
54 @@ -59,6 +59,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
55 spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
56 obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
57 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
58 +obj-$(CONFIG_SPI_QUP) += spi-qup.o
59 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
60 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
61 spi-s3c24xx-hw-y := spi-s3c24xx.o
62 diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
63 new file mode 100644
64 index 0000000..b0bcc09
65 --- /dev/null
66 +++ b/drivers/spi/spi-qup.c
67 @@ -0,0 +1,837 @@
68 +/*
69 + * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
70 + *
71 + * This program is free software; you can redistribute it and/or modify
72 + * it under the terms of the GNU General Public License rev 2 and
73 + * only rev 2 as published by the free Software foundation.
74 + *
75 + * This program is distributed in the hope that it will be useful,
76 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
77 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
78 + * GNU General Public License for more details.
79 + */
80 +
81 +#include <linux/clk.h>
82 +#include <linux/delay.h>
83 +#include <linux/err.h>
84 +#include <linux/interrupt.h>
85 +#include <linux/io.h>
86 +#include <linux/list.h>
87 +#include <linux/module.h>
88 +#include <linux/of.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/pm_runtime.h>
91 +#include <linux/spi/spi.h>
92 +
93 +#define QUP_CONFIG 0x0000
94 +#define QUP_STATE 0x0004
95 +#define QUP_IO_M_MODES 0x0008
96 +#define QUP_SW_RESET 0x000c
97 +#define QUP_OPERATIONAL 0x0018
98 +#define QUP_ERROR_FLAGS 0x001c
99 +#define QUP_ERROR_FLAGS_EN 0x0020
100 +#define QUP_OPERATIONAL_MASK 0x0028
101 +#define QUP_HW_VERSION 0x0030
102 +#define QUP_MX_OUTPUT_CNT 0x0100
103 +#define QUP_OUTPUT_FIFO 0x0110
104 +#define QUP_MX_WRITE_CNT 0x0150
105 +#define QUP_MX_INPUT_CNT 0x0200
106 +#define QUP_MX_READ_CNT 0x0208
107 +#define QUP_INPUT_FIFO 0x0218
108 +
109 +#define SPI_CONFIG 0x0300
110 +#define SPI_IO_CONTROL 0x0304
111 +#define SPI_ERROR_FLAGS 0x0308
112 +#define SPI_ERROR_FLAGS_EN 0x030c
113 +
114 +/* QUP_CONFIG fields */
115 +#define QUP_CONFIG_SPI_MODE (1 << 8)
116 +#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
117 +#define QUP_CONFIG_NO_INPUT BIT(7)
118 +#define QUP_CONFIG_NO_OUTPUT BIT(6)
119 +#define QUP_CONFIG_N 0x001f
120 +
121 +/* QUP_STATE fields */
122 +#define QUP_STATE_VALID BIT(2)
123 +#define QUP_STATE_RESET 0
124 +#define QUP_STATE_RUN 1
125 +#define QUP_STATE_PAUSE 3
126 +#define QUP_STATE_MASK 3
127 +#define QUP_STATE_CLEAR 2
128 +
129 +#define QUP_HW_VERSION_2_1_1 0x20010001
130 +
131 +/* QUP_IO_M_MODES fields */
132 +#define QUP_IO_M_PACK_EN BIT(15)
133 +#define QUP_IO_M_UNPACK_EN BIT(14)
134 +#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
135 +#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
136 +#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
137 +#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
138 +
139 +#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
140 +#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
141 +#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
142 +#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
143 +
144 +#define QUP_IO_M_MODE_FIFO 0
145 +#define QUP_IO_M_MODE_BLOCK 1
146 +#define QUP_IO_M_MODE_DMOV 2
147 +#define QUP_IO_M_MODE_BAM 3
148 +
149 +/* QUP_OPERATIONAL fields */
150 +#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
151 +#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
152 +#define QUP_OP_IN_SERVICE_FLAG BIT(9)
153 +#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
154 +#define QUP_OP_IN_FIFO_FULL BIT(7)
155 +#define QUP_OP_OUT_FIFO_FULL BIT(6)
156 +#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
157 +#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
158 +
159 +/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
160 +#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
161 +#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
162 +#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
163 +#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
164 +
165 +/* SPI_CONFIG fields */
166 +#define SPI_CONFIG_HS_MODE BIT(10)
167 +#define SPI_CONFIG_INPUT_FIRST BIT(9)
168 +#define SPI_CONFIG_LOOPBACK BIT(8)
169 +
170 +/* SPI_IO_CONTROL fields */
171 +#define SPI_IO_C_FORCE_CS BIT(11)
172 +#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
173 +#define SPI_IO_C_MX_CS_MODE BIT(8)
174 +#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
175 +#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
176 +#define SPI_IO_C_CS_SELECT_MASK 0x000c
177 +#define SPI_IO_C_TRISTATE_CS BIT(1)
178 +#define SPI_IO_C_NO_TRI_STATE BIT(0)
179 +
180 +/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
181 +#define SPI_ERROR_CLK_OVER_RUN BIT(1)
182 +#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
183 +
184 +#define SPI_NUM_CHIPSELECTS 4
185 +
186 +/* high speed mode is when bus rate is greater then 26MHz */
187 +#define SPI_HS_MIN_RATE 26000000
188 +#define SPI_MAX_RATE 50000000
189 +
190 +#define SPI_DELAY_THRESHOLD 1
191 +#define SPI_DELAY_RETRY 10
192 +
193 +struct spi_qup_device {
194 + int select;
195 + u16 mode;
196 +};
197 +
198 +struct spi_qup {
199 + void __iomem *base;
200 + struct device *dev;
201 + struct clk *cclk; /* core clock */
202 + struct clk *iclk; /* interface clock */
203 + int irq;
204 + u32 max_speed_hz;
205 + spinlock_t lock;
206 +
207 + int in_fifo_sz;
208 + int out_fifo_sz;
209 + int in_blk_sz;
210 + int out_blk_sz;
211 +
212 + struct spi_transfer *xfer;
213 + struct completion done;
214 + int error;
215 + int w_size; /* bytes per SPI word */
216 + int tx_bytes;
217 + int rx_bytes;
218 +};
219 +
220 +
221 +static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
222 +{
223 + u32 opstate = readl_relaxed(controller->base + QUP_STATE);
224 +
225 + return opstate & QUP_STATE_VALID;
226 +}
227 +
228 +static int spi_qup_set_state(struct spi_qup *controller, u32 state)
229 +{
230 + unsigned long loop;
231 + u32 cur_state;
232 +
233 + loop = 0;
234 + while (!spi_qup_is_valid_state(controller)) {
235 +
236 + usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
237 +
238 + if (++loop > SPI_DELAY_RETRY)
239 + return -EIO;
240 + }
241 +
242 + if (loop)
243 + dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
244 + loop, state);
245 +
246 + cur_state = readl_relaxed(controller->base + QUP_STATE);
247 + /*
248 + * Per spec: for PAUSE_STATE to RESET_STATE, two writes
249 + * of (b10) are required
250 + */
251 + if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
252 + (state == QUP_STATE_RESET)) {
253 + writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
254 + writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
255 + } else {
256 + cur_state &= ~QUP_STATE_MASK;
257 + cur_state |= state;
258 + writel_relaxed(cur_state, controller->base + QUP_STATE);
259 + }
260 +
261 + loop = 0;
262 + while (!spi_qup_is_valid_state(controller)) {
263 +
264 + usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
265 +
266 + if (++loop > SPI_DELAY_RETRY)
267 + return -EIO;
268 + }
269 +
270 + return 0;
271 +}
272 +
273 +
274 +static void spi_qup_fifo_read(struct spi_qup *controller,
275 + struct spi_transfer *xfer)
276 +{
277 + u8 *rx_buf = xfer->rx_buf;
278 + u32 word, state;
279 + int idx, shift, w_size;
280 +
281 + w_size = controller->w_size;
282 +
283 + while (controller->rx_bytes < xfer->len) {
284 +
285 + state = readl_relaxed(controller->base + QUP_OPERATIONAL);
286 + if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
287 + break;
288 +
289 + word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
290 +
291 + if (!rx_buf) {
292 + controller->rx_bytes += w_size;
293 + continue;
294 + }
295 +
296 + for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
297 + /*
298 + * The data format depends on bytes per SPI word:
299 + * 4 bytes: 0x12345678
300 + * 2 bytes: 0x00001234
301 + * 1 byte : 0x00000012
302 + */
303 + shift = BITS_PER_BYTE;
304 + shift *= (w_size - idx - 1);
305 + rx_buf[controller->rx_bytes] = word >> shift;
306 + }
307 + }
308 +}
309 +
310 +static void spi_qup_fifo_write(struct spi_qup *controller,
311 + struct spi_transfer *xfer)
312 +{
313 + const u8 *tx_buf = xfer->tx_buf;
314 + u32 word, state, data;
315 + int idx, w_size;
316 +
317 + w_size = controller->w_size;
318 +
319 + while (controller->tx_bytes < xfer->len) {
320 +
321 + state = readl_relaxed(controller->base + QUP_OPERATIONAL);
322 + if (state & QUP_OP_OUT_FIFO_FULL)
323 + break;
324 +
325 + word = 0;
326 + for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
327 +
328 + if (!tx_buf) {
329 + controller->tx_bytes += w_size;
330 + break;
331 + }
332 +
333 + data = tx_buf[controller->tx_bytes];
334 + word |= data << (BITS_PER_BYTE * (3 - idx));
335 + }
336 +
337 + writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
338 + }
339 +}
340 +
341 +static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
342 +{
343 + struct spi_qup *controller = dev_id;
344 + struct spi_transfer *xfer;
345 + u32 opflags, qup_err, spi_err;
346 + unsigned long flags;
347 + int error = 0;
348 +
349 + spin_lock_irqsave(&controller->lock, flags);
350 + xfer = controller->xfer;
351 + controller->xfer = NULL;
352 + spin_unlock_irqrestore(&controller->lock, flags);
353 +
354 + qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
355 + spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
356 + opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
357 +
358 + writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
359 + writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
360 + writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
361 +
362 + if (!xfer) {
363 + dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
364 + qup_err, spi_err, opflags);
365 + return IRQ_HANDLED;
366 + }
367 +
368 + if (qup_err) {
369 + if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
370 + dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
371 + if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
372 + dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
373 + if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
374 + dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
375 + if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
376 + dev_warn(controller->dev, "INPUT_OVER_RUN\n");
377 +
378 + error = -EIO;
379 + }
380 +
381 + if (spi_err) {
382 + if (spi_err & SPI_ERROR_CLK_OVER_RUN)
383 + dev_warn(controller->dev, "CLK_OVER_RUN\n");
384 + if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
385 + dev_warn(controller->dev, "CLK_UNDER_RUN\n");
386 +
387 + error = -EIO;
388 + }
389 +
390 + if (opflags & QUP_OP_IN_SERVICE_FLAG)
391 + spi_qup_fifo_read(controller, xfer);
392 +
393 + if (opflags & QUP_OP_OUT_SERVICE_FLAG)
394 + spi_qup_fifo_write(controller, xfer);
395 +
396 + spin_lock_irqsave(&controller->lock, flags);
397 + controller->error = error;
398 + controller->xfer = xfer;
399 + spin_unlock_irqrestore(&controller->lock, flags);
400 +
401 + if (controller->rx_bytes == xfer->len || error)
402 + complete(&controller->done);
403 +
404 + return IRQ_HANDLED;
405 +}
406 +
407 +
408 +/* set clock freq ... bits per word */
409 +static int spi_qup_io_config(struct spi_qup *controller,
410 + struct spi_qup_device *chip,
411 + struct spi_transfer *xfer)
412 +{
413 + u32 config, iomode, mode;
414 + int ret, n_words, w_size;
415 +
416 + if (chip->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
417 + dev_err(controller->dev, "too big size for loopback %d > %d\n",
418 + xfer->len, controller->in_fifo_sz);
419 + return -EIO;
420 + }
421 +
422 + ret = clk_set_rate(controller->cclk, xfer->speed_hz);
423 + if (ret) {
424 + dev_err(controller->dev, "fail to set frequency %d",
425 + xfer->speed_hz);
426 + return -EIO;
427 + }
428 +
429 + if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
430 + dev_err(controller->dev, "cannot set RESET state\n");
431 + return -EIO;
432 + }
433 +
434 + w_size = 4;
435 + if (xfer->bits_per_word <= 8)
436 + w_size = 1;
437 + else if (xfer->bits_per_word <= 16)
438 + w_size = 2;
439 +
440 + n_words = xfer->len / w_size;
441 + controller->w_size = w_size;
442 +
443 + if (n_words <= controller->in_fifo_sz) {
444 + mode = QUP_IO_M_MODE_FIFO;
445 + writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
446 + writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
447 + /* must be zero for FIFO */
448 + writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
449 + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
450 + } else {
451 + mode = QUP_IO_M_MODE_BLOCK;
452 + writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
453 + writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
454 + /* must be zero for BLOCK and BAM */
455 + writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
456 + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
457 + }
458 +
459 + iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
460 + /* Set input and output transfer mode */
461 + iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
462 + iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
463 + iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
464 + iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
465 +
466 + writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
467 +
468 + config = readl_relaxed(controller->base + SPI_CONFIG);
469 +
470 + if (chip->mode & SPI_LOOP)
471 + config |= SPI_CONFIG_LOOPBACK;
472 + else
473 + config &= ~SPI_CONFIG_LOOPBACK;
474 +
475 + if (chip->mode & SPI_CPHA)
476 + config &= ~SPI_CONFIG_INPUT_FIRST;
477 + else
478 + config |= SPI_CONFIG_INPUT_FIRST;
479 +
480 + /*
481 + * HS_MODE improves signal stability for spi-clk high rates,
482 + * but is invalid in loop back mode.
483 + */
484 + if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(chip->mode & SPI_LOOP))
485 + config |= SPI_CONFIG_HS_MODE;
486 + else
487 + config &= ~SPI_CONFIG_HS_MODE;
488 +
489 + writel_relaxed(config, controller->base + SPI_CONFIG);
490 +
491 + config = readl_relaxed(controller->base + QUP_CONFIG);
492 + config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
493 + config |= xfer->bits_per_word - 1;
494 + config |= QUP_CONFIG_SPI_MODE;
495 + writel_relaxed(config, controller->base + QUP_CONFIG);
496 +
497 + writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
498 + return 0;
499 +}
500 +
501 +static void spi_qup_set_cs(struct spi_device *spi, bool enable)
502 +{
503 + struct spi_qup *controller = spi_master_get_devdata(spi->master);
504 + struct spi_qup_device *chip = spi_get_ctldata(spi);
505 +
506 + u32 iocontol, mask;
507 +
508 + iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
509 +
510 + /* Disable auto CS toggle and use manual */
511 + iocontol &= ~SPI_IO_C_MX_CS_MODE;
512 + iocontol |= SPI_IO_C_FORCE_CS;
513 +
514 + iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
515 + iocontol |= SPI_IO_C_CS_SELECT(chip->select);
516 +
517 + mask = SPI_IO_C_CS_N_POLARITY_0 << chip->select;
518 +
519 + if (enable)
520 + iocontol |= mask;
521 + else
522 + iocontol &= ~mask;
523 +
524 + writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
525 +}
526 +
527 +static int spi_qup_transfer_one(struct spi_master *master,
528 + struct spi_device *spi,
529 + struct spi_transfer *xfer)
530 +{
531 + struct spi_qup *controller = spi_master_get_devdata(master);
532 + struct spi_qup_device *chip = spi_get_ctldata(spi);
533 + unsigned long timeout, flags;
534 + int ret = -EIO;
535 +
536 + ret = spi_qup_io_config(controller, chip, xfer);
537 + if (ret)
538 + return ret;
539 +
540 + timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
541 + timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
542 + timeout = 100 * msecs_to_jiffies(timeout);
543 +
544 + reinit_completion(&controller->done);
545 +
546 + spin_lock_irqsave(&controller->lock, flags);
547 + controller->xfer = xfer;
548 + controller->error = 0;
549 + controller->rx_bytes = 0;
550 + controller->tx_bytes = 0;
551 + spin_unlock_irqrestore(&controller->lock, flags);
552 +
553 + if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
554 + dev_warn(controller->dev, "cannot set RUN state\n");
555 + goto exit;
556 + }
557 +
558 + if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
559 + dev_warn(controller->dev, "cannot set PAUSE state\n");
560 + goto exit;
561 + }
562 +
563 + spi_qup_fifo_write(controller, xfer);
564 +
565 + if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
566 + dev_warn(controller->dev, "cannot set EXECUTE state\n");
567 + goto exit;
568 + }
569 +
570 + if (!wait_for_completion_timeout(&controller->done, timeout))
571 + ret = -ETIMEDOUT;
572 +exit:
573 + spi_qup_set_state(controller, QUP_STATE_RESET);
574 + spin_lock_irqsave(&controller->lock, flags);
575 + controller->xfer = NULL;
576 + if (!ret)
577 + ret = controller->error;
578 + spin_unlock_irqrestore(&controller->lock, flags);
579 + return ret;
580 +}
581 +
582 +static int spi_qup_setup(struct spi_device *spi)
583 +{
584 + struct spi_qup *controller = spi_master_get_devdata(spi->master);
585 + struct spi_qup_device *chip = spi_get_ctldata(spi);
586 +
587 + if (spi->chip_select >= spi->master->num_chipselect) {
588 + dev_err(controller->dev, "invalid chip_select %d\n",
589 + spi->chip_select);
590 + return -EINVAL;
591 + }
592 +
593 + if (spi->max_speed_hz > controller->max_speed_hz) {
594 + dev_err(controller->dev, "invalid max_speed_hz %d\n",
595 + spi->max_speed_hz);
596 + return -EINVAL;
597 + }
598 +
599 + if (!chip) {
600 + /* First setup */
601 + chip = kzalloc(sizeof(*chip), GFP_KERNEL);
602 + if (!chip) {
603 + dev_err(controller->dev, "no memory for chip data\n");
604 + return -ENOMEM;
605 + }
606 +
607 + chip->mode = spi->mode;
608 + chip->select = spi->chip_select;
609 + spi_set_ctldata(spi, chip);
610 + }
611 +
612 + return 0;
613 +}
614 +
615 +static void spi_qup_cleanup(struct spi_device *spi)
616 +{
617 + struct spi_qup_device *chip = spi_get_ctldata(spi);
618 +
619 + if (!chip)
620 + return;
621 +
622 + spi_set_ctldata(spi, NULL);
623 + kfree(chip);
624 +}
625 +
626 +static int spi_qup_probe(struct platform_device *pdev)
627 +{
628 + struct spi_master *master;
629 + struct clk *iclk, *cclk;
630 + struct spi_qup *controller;
631 + struct resource *res;
632 + struct device *dev;
633 + void __iomem *base;
634 + u32 data, max_freq, iomode;
635 + int ret, irq, size;
636 +
637 + dev = &pdev->dev;
638 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
639 + base = devm_ioremap_resource(dev, res);
640 + if (IS_ERR(base))
641 + return PTR_ERR(base);
642 +
643 + irq = platform_get_irq(pdev, 0);
644 +
645 + if (irq < 0)
646 + return irq;
647 +
648 + cclk = devm_clk_get(dev, "core");
649 + if (IS_ERR(cclk))
650 + return PTR_ERR(cclk);
651 +
652 + iclk = devm_clk_get(dev, "iface");
653 + if (IS_ERR(iclk))
654 + return PTR_ERR(iclk);
655 +
656 + /* This is optional parameter */
657 + if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
658 + max_freq = SPI_MAX_RATE;
659 +
660 + if (!max_freq || max_freq > SPI_MAX_RATE) {
661 + dev_err(dev, "invalid clock frequency %d\n", max_freq);
662 + return -ENXIO;
663 + }
664 +
665 + ret = clk_prepare_enable(cclk);
666 + if (ret) {
667 + dev_err(dev, "cannot enable core clock\n");
668 + return ret;
669 + }
670 +
671 + ret = clk_prepare_enable(iclk);
672 + if (ret) {
673 + clk_disable_unprepare(cclk);
674 + dev_err(dev, "cannot enable iface clock\n");
675 + return ret;
676 + }
677 +
678 + data = readl_relaxed(base + QUP_HW_VERSION);
679 +
680 + if (data < QUP_HW_VERSION_2_1_1) {
681 + clk_disable_unprepare(cclk);
682 + clk_disable_unprepare(iclk);
683 + dev_err(dev, "v.%08x is not supported\n", data);
684 + return -ENXIO;
685 + }
686 +
687 + master = spi_alloc_master(dev, sizeof(struct spi_qup));
688 + if (!master) {
689 + clk_disable_unprepare(cclk);
690 + clk_disable_unprepare(iclk);
691 + dev_err(dev, "cannot allocate master\n");
692 + return -ENOMEM;
693 + }
694 +
695 + master->bus_num = pdev->id;
696 + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
697 + master->num_chipselect = SPI_NUM_CHIPSELECTS;
698 + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
699 + master->setup = spi_qup_setup;
700 + master->cleanup = spi_qup_cleanup;
701 + master->set_cs = spi_qup_set_cs;
702 + master->transfer_one = spi_qup_transfer_one;
703 + master->dev.of_node = pdev->dev.of_node;
704 + master->auto_runtime_pm = true;
705 +
706 + platform_set_drvdata(pdev, master);
707 +
708 + controller = spi_master_get_devdata(master);
709 +
710 + controller->dev = dev;
711 + controller->base = base;
712 + controller->iclk = iclk;
713 + controller->cclk = cclk;
714 + controller->irq = irq;
715 + controller->max_speed_hz = max_freq;
716 +
717 + spin_lock_init(&controller->lock);
718 + init_completion(&controller->done);
719 +
720 + iomode = readl_relaxed(base + QUP_IO_M_MODES);
721 +
722 + size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
723 + if (size)
724 + controller->out_blk_sz = size * 16;
725 + else
726 + controller->out_blk_sz = 4;
727 +
728 + size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
729 + if (size)
730 + controller->in_blk_sz = size * 16;
731 + else
732 + controller->in_blk_sz = 4;
733 +
734 + size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
735 + controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
736 +
737 + size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
738 + controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
739 +
740 + dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
741 + data, controller->in_blk_sz, controller->in_fifo_sz,
742 + controller->out_blk_sz, controller->out_fifo_sz);
743 +
744 + writel_relaxed(1, base + QUP_SW_RESET);
745 +
746 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
747 + if (ret) {
748 + dev_err(dev, "cannot set RESET state\n");
749 + goto error;
750 + }
751 +
752 + writel_relaxed(0, base + QUP_OPERATIONAL);
753 + writel_relaxed(0, base + QUP_IO_M_MODES);
754 + writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
755 + writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
756 + base + SPI_ERROR_FLAGS_EN);
757 +
758 + writel_relaxed(0, base + SPI_CONFIG);
759 + writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
760 +
761 + ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
762 + IRQF_TRIGGER_HIGH, pdev->name, controller);
763 + if (ret)
764 + goto error;
765 +
766 + ret = devm_spi_register_master(dev, master);
767 + if (ret)
768 + goto error;
769 +
770 + pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
771 + pm_runtime_use_autosuspend(dev);
772 + pm_runtime_set_active(dev);
773 + pm_runtime_enable(dev);
774 + return 0;
775 +
776 +error:
777 + clk_disable_unprepare(cclk);
778 + clk_disable_unprepare(iclk);
779 + spi_master_put(master);
780 + return ret;
781 +}
782 +
783 +#ifdef CONFIG_PM_RUNTIME
784 +static int spi_qup_pm_suspend_runtime(struct device *device)
785 +{
786 + struct spi_master *master = dev_get_drvdata(device);
787 + struct spi_qup *controller = spi_master_get_devdata(master);
788 + u32 config;
789 +
790 + /* Enable clocks auto gaiting */
791 + config = readl(controller->base + QUP_CONFIG);
792 + config |= QUP_CLOCK_AUTO_GATE;
793 + writel_relaxed(config, controller->base + QUP_CONFIG);
794 + return 0;
795 +}
796 +
797 +static int spi_qup_pm_resume_runtime(struct device *device)
798 +{
799 + struct spi_master *master = dev_get_drvdata(device);
800 + struct spi_qup *controller = spi_master_get_devdata(master);
801 + u32 config;
802 +
803 + /* Disable clocks auto gaiting */
804 + config = readl_relaxed(controller->base + QUP_CONFIG);
805 + config &= ~QUP_CLOCK_AUTO_GATE;
806 + writel_relaxed(config, controller->base + QUP_CONFIG);
807 + return 0;
808 +}
809 +#endif /* CONFIG_PM_RUNTIME */
810 +
811 +#ifdef CONFIG_PM_SLEEP
812 +static int spi_qup_suspend(struct device *device)
813 +{
814 + struct spi_master *master = dev_get_drvdata(device);
815 + struct spi_qup *controller = spi_master_get_devdata(master);
816 + int ret;
817 +
818 + ret = spi_master_suspend(master);
819 + if (ret)
820 + return ret;
821 +
822 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
823 + if (ret)
824 + return ret;
825 +
826 + clk_disable_unprepare(controller->cclk);
827 + clk_disable_unprepare(controller->iclk);
828 + return 0;
829 +}
830 +
831 +static int spi_qup_resume(struct device *device)
832 +{
833 + struct spi_master *master = dev_get_drvdata(device);
834 + struct spi_qup *controller = spi_master_get_devdata(master);
835 + int ret;
836 +
837 + ret = clk_prepare_enable(controller->iclk);
838 + if (ret)
839 + return ret;
840 +
841 + ret = clk_prepare_enable(controller->cclk);
842 + if (ret)
843 + return ret;
844 +
845 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
846 + if (ret)
847 + return ret;
848 +
849 + return spi_master_resume(master);
850 +}
851 +#endif /* CONFIG_PM_SLEEP */
852 +
853 +static int spi_qup_remove(struct platform_device *pdev)
854 +{
855 + struct spi_master *master = dev_get_drvdata(&pdev->dev);
856 + struct spi_qup *controller = spi_master_get_devdata(master);
857 + int ret;
858 +
859 + ret = pm_runtime_get_sync(&pdev->dev);
860 + if (ret)
861 + return ret;
862 +
863 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
864 + if (ret)
865 + return ret;
866 +
867 + clk_disable_unprepare(controller->cclk);
868 + clk_disable_unprepare(controller->iclk);
869 +
870 + pm_runtime_put_noidle(&pdev->dev);
871 + pm_runtime_disable(&pdev->dev);
872 + spi_master_put(master);
873 + return 0;
874 +}
875 +
876 +static struct of_device_id spi_qup_dt_match[] = {
877 + { .compatible = "qcom,spi-qup-v2.1.1", },
878 + { .compatible = "qcom,spi-qup-v2.2.1", },
879 + { }
880 +};
881 +MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
882 +
883 +static const struct dev_pm_ops spi_qup_dev_pm_ops = {
884 + SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
885 + SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
886 + spi_qup_pm_resume_runtime,
887 + NULL)
888 +};
889 +
890 +static struct platform_driver spi_qup_driver = {
891 + .driver = {
892 + .name = "spi_qup",
893 + .owner = THIS_MODULE,
894 + .pm = &spi_qup_dev_pm_ops,
895 + .of_match_table = spi_qup_dt_match,
896 + },
897 + .probe = spi_qup_probe,
898 + .remove = spi_qup_remove,
899 +};
900 +module_platform_driver(spi_qup_driver);
901 +
902 +MODULE_LICENSE("GPL v2");
903 +MODULE_VERSION("0.4");
904 +MODULE_ALIAS("platform:spi_qup");
905 --
906 1.7.10.4
907
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