1 From 07d7d95706c1bf373bd6b30c42f95c7b8dc8b9ce Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Thu, 3 Apr 2014 14:48:22 -0500
4 Subject: [PATCH 094/182] ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410
7 Add basic APQ8064 SoC include device tree and support for basic booting on
8 the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
11 Signed-off-by: Kumar Gala <galak@codeaurora.org>
13 arch/arm/boot/dts/Makefile | 8 +-
14 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
15 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
16 arch/arm/boot/dts/qcom-apq8064.dtsi | 170 ++++++++++++++++++++++++++++
17 arch/arm/mach-qcom/board.c | 3 +-
18 5 files changed, 194 insertions(+), 4 deletions(-)
19 create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
20 create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
21 create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
23 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
24 index 4a89023..ee3dfea 100644
25 --- a/arch/arm/boot/dts/Makefile
26 +++ b/arch/arm/boot/dts/Makefile
27 @@ -231,9 +231,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
29 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
30 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
31 -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
32 - qcom-msm8960-cdp.dtb \
33 - qcom-apq8074-dragonboard.dtb
34 +dtb-$(CONFIG_ARCH_QCOM) += \
35 + qcom-apq8064-ifc6410.dtb \
36 + qcom-apq8074-dragonboard.dtb \
37 + qcom-msm8660-surf.dtb \
38 + qcom-msm8960-cdp.dtb
39 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
40 ste-hrefprev60-stuib.dtb \
41 ste-hrefprev60-tvk.dtb \
42 diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
44 index 0000000..7c2441d
46 +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
48 +#include "qcom-apq8064-v2.0.dtsi"
51 + model = "Qualcomm APQ8064/IFC6410";
52 + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
57 + qcom,mode = <GSBI_PROT_I2C_UART>;
64 diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
66 index 0000000..935c394
68 +++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
70 +#include "qcom-apq8064.dtsi"
71 diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
73 index 0000000..92bf793
75 +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
79 +#include "skeleton.dtsi"
80 +#include <dt-bindings/clock/qcom,gcc-msm8960.h>
81 +#include <dt-bindings/soc/qcom,gsbi.h>
84 + model = "Qualcomm APQ8064";
85 + compatible = "qcom,apq8064";
86 + interrupt-parent = <&intc>;
89 + #address-cells = <1>;
93 + compatible = "qcom,krait";
94 + enable-method = "qcom,kpss-acc-v1";
95 + device_type = "cpu";
97 + next-level-cache = <&L2>;
103 + compatible = "qcom,krait";
104 + enable-method = "qcom,kpss-acc-v1";
105 + device_type = "cpu";
107 + next-level-cache = <&L2>;
108 + qcom,acc = <&acc1>;
109 + qcom,saw = <&saw1>;
113 + compatible = "qcom,krait";
114 + enable-method = "qcom,kpss-acc-v1";
115 + device_type = "cpu";
117 + next-level-cache = <&L2>;
118 + qcom,acc = <&acc2>;
119 + qcom,saw = <&saw2>;
123 + compatible = "qcom,krait";
124 + enable-method = "qcom,kpss-acc-v1";
125 + device_type = "cpu";
127 + next-level-cache = <&L2>;
128 + qcom,acc = <&acc3>;
129 + qcom,saw = <&saw3>;
133 + compatible = "cache";
139 + compatible = "qcom,krait-pmu";
140 + interrupts = <1 10 0x304>;
144 + #address-cells = <1>;
147 + compatible = "simple-bus";
149 + intc: interrupt-controller@2000000 {
150 + compatible = "qcom,msm-qgic2";
151 + interrupt-controller;
152 + #interrupt-cells = <3>;
153 + reg = <0x02000000 0x1000>,
154 + <0x02002000 0x1000>;
158 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
159 + interrupts = <1 1 0x301>,
162 + reg = <0x0200a000 0x100>;
163 + clock-frequency = <27000000>,
165 + cpu-offset = <0x80000>;
168 + acc0: clock-controller@2088000 {
169 + compatible = "qcom,kpss-acc-v1";
170 + reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
173 + acc1: clock-controller@2098000 {
174 + compatible = "qcom,kpss-acc-v1";
175 + reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
178 + acc2: clock-controller@20a8000 {
179 + compatible = "qcom,kpss-acc-v1";
180 + reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
183 + acc3: clock-controller@20b8000 {
184 + compatible = "qcom,kpss-acc-v1";
185 + reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
188 + saw0: regulator@2089000 {
189 + compatible = "qcom,saw2";
190 + reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
194 + saw1: regulator@2099000 {
195 + compatible = "qcom,saw2";
196 + reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
200 + saw2: regulator@20a9000 {
201 + compatible = "qcom,saw2";
202 + reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
206 + saw3: regulator@20b9000 {
207 + compatible = "qcom,saw2";
208 + reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
212 + gsbi7: gsbi@16600000 {
213 + status = "disabled";
214 + compatible = "qcom,gsbi-v1.0.0";
215 + reg = <0x16600000 0x100>;
216 + clocks = <&gcc GSBI7_H_CLK>;
217 + clock-names = "iface";
218 + #address-cells = <1>;
223 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
224 + reg = <0x16640000 0x1000>,
225 + <0x16600000 0x1000>;
226 + interrupts = <0 158 0x0>;
227 + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
228 + clock-names = "core", "iface";
229 + status = "disabled";
234 + compatible = "qcom,ssbi";
235 + reg = <0x00500000 0x1000>;
236 + qcom,controller-type = "pmic-arbiter";
239 + gcc: clock-controller@900000 {
240 + compatible = "qcom,gcc-apq8064";
241 + reg = <0x00900000 0x4000>;
242 + #clock-cells = <1>;
243 + #reset-cells = <1>;
247 diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
248 index bae617e..350fa8d 100644
249 --- a/arch/arm/mach-qcom/board.c
250 +++ b/arch/arm/mach-qcom/board.c
252 #include <asm/mach/arch.h>
254 static const char * const qcom_dt_match[] __initconst = {
256 + "qcom,apq8074-dragonboard",
259 - "qcom,apq8074-dragonboard",