1 From 07d7d95706c1bf373bd6b30c42f95c7b8dc8b9ce Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Thu, 3 Apr 2014 14:48:22 -0500
4 Subject: [PATCH 094/182] ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410
7 Add basic APQ8064 SoC include device tree and support for basic booting on
8 the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
11 Signed-off-by: Kumar Gala <galak@codeaurora.org>
13 arch/arm/boot/dts/Makefile | 8 +-
14 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
15 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
16 arch/arm/boot/dts/qcom-apq8064.dtsi | 170 ++++++++++++++++++++++++++++
17 arch/arm/mach-qcom/board.c | 3 +-
18 5 files changed, 194 insertions(+), 4 deletions(-)
19 create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
20 create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
21 create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
23 --- a/arch/arm/boot/dts/Makefile
24 +++ b/arch/arm/boot/dts/Makefile
25 @@ -231,9 +231,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420
27 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
28 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
29 -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
30 - qcom-msm8960-cdp.dtb \
31 - qcom-apq8074-dragonboard.dtb
32 +dtb-$(CONFIG_ARCH_QCOM) += \
33 + qcom-apq8064-ifc6410.dtb \
34 + qcom-apq8074-dragonboard.dtb \
35 + qcom-msm8660-surf.dtb \
36 + qcom-msm8960-cdp.dtb
37 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
38 ste-hrefprev60-stuib.dtb \
39 ste-hrefprev60-tvk.dtb \
41 +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
43 +#include "qcom-apq8064-v2.0.dtsi"
46 + model = "Qualcomm APQ8064/IFC6410";
47 + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
52 + qcom,mode = <GSBI_PROT_I2C_UART>;
60 +++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
62 +#include "qcom-apq8064.dtsi"
64 +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
68 +#include "skeleton.dtsi"
69 +#include <dt-bindings/clock/qcom,gcc-msm8960.h>
70 +#include <dt-bindings/soc/qcom,gsbi.h>
73 + model = "Qualcomm APQ8064";
74 + compatible = "qcom,apq8064";
75 + interrupt-parent = <&intc>;
78 + #address-cells = <1>;
82 + compatible = "qcom,krait";
83 + enable-method = "qcom,kpss-acc-v1";
84 + device_type = "cpu";
86 + next-level-cache = <&L2>;
92 + compatible = "qcom,krait";
93 + enable-method = "qcom,kpss-acc-v1";
94 + device_type = "cpu";
96 + next-level-cache = <&L2>;
102 + compatible = "qcom,krait";
103 + enable-method = "qcom,kpss-acc-v1";
104 + device_type = "cpu";
106 + next-level-cache = <&L2>;
107 + qcom,acc = <&acc2>;
108 + qcom,saw = <&saw2>;
112 + compatible = "qcom,krait";
113 + enable-method = "qcom,kpss-acc-v1";
114 + device_type = "cpu";
116 + next-level-cache = <&L2>;
117 + qcom,acc = <&acc3>;
118 + qcom,saw = <&saw3>;
122 + compatible = "cache";
128 + compatible = "qcom,krait-pmu";
129 + interrupts = <1 10 0x304>;
133 + #address-cells = <1>;
136 + compatible = "simple-bus";
138 + intc: interrupt-controller@2000000 {
139 + compatible = "qcom,msm-qgic2";
140 + interrupt-controller;
141 + #interrupt-cells = <3>;
142 + reg = <0x02000000 0x1000>,
143 + <0x02002000 0x1000>;
147 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
148 + interrupts = <1 1 0x301>,
151 + reg = <0x0200a000 0x100>;
152 + clock-frequency = <27000000>,
154 + cpu-offset = <0x80000>;
157 + acc0: clock-controller@2088000 {
158 + compatible = "qcom,kpss-acc-v1";
159 + reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
162 + acc1: clock-controller@2098000 {
163 + compatible = "qcom,kpss-acc-v1";
164 + reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
167 + acc2: clock-controller@20a8000 {
168 + compatible = "qcom,kpss-acc-v1";
169 + reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
172 + acc3: clock-controller@20b8000 {
173 + compatible = "qcom,kpss-acc-v1";
174 + reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
177 + saw0: regulator@2089000 {
178 + compatible = "qcom,saw2";
179 + reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
183 + saw1: regulator@2099000 {
184 + compatible = "qcom,saw2";
185 + reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
189 + saw2: regulator@20a9000 {
190 + compatible = "qcom,saw2";
191 + reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
195 + saw3: regulator@20b9000 {
196 + compatible = "qcom,saw2";
197 + reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
201 + gsbi7: gsbi@16600000 {
202 + status = "disabled";
203 + compatible = "qcom,gsbi-v1.0.0";
204 + reg = <0x16600000 0x100>;
205 + clocks = <&gcc GSBI7_H_CLK>;
206 + clock-names = "iface";
207 + #address-cells = <1>;
212 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
213 + reg = <0x16640000 0x1000>,
214 + <0x16600000 0x1000>;
215 + interrupts = <0 158 0x0>;
216 + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
217 + clock-names = "core", "iface";
218 + status = "disabled";
223 + compatible = "qcom,ssbi";
224 + reg = <0x00500000 0x1000>;
225 + qcom,controller-type = "pmic-arbiter";
228 + gcc: clock-controller@900000 {
229 + compatible = "qcom,gcc-apq8064";
230 + reg = <0x00900000 0x4000>;
231 + #clock-cells = <1>;
232 + #reset-cells = <1>;
236 --- a/arch/arm/mach-qcom/board.c
237 +++ b/arch/arm/mach-qcom/board.c
239 #include <asm/mach/arch.h>
241 static const char * const qcom_dt_match[] __initconst = {
243 + "qcom,apq8074-dragonboard",
246 - "qcom,apq8074-dragonboard",