1 From 37258bc8fe832e4c681593a864686f627f6d3455 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Tue, 10 Jun 2014 13:09:01 -0500
4 Subject: [PATCH 145/182] phy: qcom: Add device tree bindings information
6 Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
7 the IPQ806x family of SoCs.
9 Signed-off-by: Kumar Gala <galak@codeaurora.org>
11 Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++++++++++++++++++++
12 1 file changed, 23 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/phy/qcom-phy.txt
15 diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
17 index 0000000..76bfbd0
19 +++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
21 +Qualcomm IPQ806x SATA PHY Controller
22 +------------------------------------
24 +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
25 +Each SATA PHY controller should have its own node.
28 +- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
29 +- reg: offset and length of the SATA PHY register set;
30 +- #phy-cells: must be zero
31 +- clocks: must be exactly one entry
32 +- clock-names: must be "cfg"
35 + sata_phy: sata-phy@1b400000 {
36 + compatible = "qcom,ipq806x-sata-phy";
37 + reg = <0x1b400000 0x200>;
39 + clocks = <&gcc SATA_PHY_CFG_CLK>;
40 + clock-names = "cfg";