target/linux/ipq806x/patches/0158-usb-dwc3-qcom-Add-device-tree-binding.patch

   1 From c7045330c5976eb31bd79bc57c5db684588d595e Mon Sep 17 00:00:00 2001
   2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
   3 Date: Mon, 7 Oct 2013 10:44:55 +0300
   4 Subject: [PATCH 158/182] usb: dwc3: qcom: Add device tree binding
   5
   6 QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
   7 (SNPS) and HS, SS PHY's control and configuration registers.
   8
   9 It could operate in device mode (SS, HS, FS) and host
  10 mode (SS, HS, FS, LS).
  11
  12 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
  13 Acked-by: Stephen Warren <swarren@nvidia.com>
  14 ---
  15  .../devicetree/bindings/usb/qcom,dwc3.txt          |  104 ++++++++++++++++++++
  16  1 file changed, 104 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
  18
  19 diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
  20 new file mode 100644
  21 index 0000000..105b6b7
  22 --- /dev/null
  23 +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
  24 @@ -0,0 +1,104 @@
  25 +Qualcomm SuperSpeed DWC3 USB SoC controller
  26 +
  27 +
  28 +QCOM DWC3 Highspeed USB PHY
  29 +========================
  30 +Required properities:
  31 +- compatible:  should contain "qcom,dwc3-hsphy";
  32 +- reg:                 offset and length of the register set in the memory map
  33 +- clocks:              A list of phandle + clock-specifier pairs for the
  34 +                               clocks listed in clock-names
  35 +- clock-names: Should contain the following:
  36 +  "utmi"               UTMI clock
  37 +- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
  38 +- v3p3-supply: phandle to the regulator for the 3.3v supply to HSPHY.
  39 +- vbus-supply: phandle to the regulator for the vbus supply for host
  40 +               mode.
  41 +- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
  42 +                digital circuit operation.
  43 +
  44 +Optional clocks:
  45 +  "xo"                 External reference clock
  46 +
  47 +
  48 +QCOM DWC3 Superspeed USB PHY
  49 +=========================
  50 +Required properities:
  51 +- compatible:  should contain "qcom,dwc3-ssphy";
  52 +- reg:                 offset and length of the register set in the memory map
  53 +- clocks:              A list of phandle + clock-specifier pairs for the
  54 +                               clocks listed in clock-names
  55 +- clock-names: Should contain the following:
  56 +  "ref"                        Reference clock used in host mode.
  57 +- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
  58 +- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
  59 +                digital circuit operation.
  60 +
  61 +Optional clocks:
  62 +  "xo"                 External reference clock
  63 +
  64 +QCOM DWC3 controller wrapper
  65 +===========================
  66 +Required properties:
  67 +- compatible:  should contain "qcom,dwc3"
  68 +- clocks:              A list of phandle + clock-specifier pairs for the
  69 +                               clocks listed in clock-names
  70 +- clock-names: Should contain the following:
  71 +  "core"               Master/Core clock, have to be >= 125 MHz for SS
  72 +                               operation and >= 60MHz for HS operation
  73 +
  74 +Optional clocks:
  75 +  "iface"              System bus AXI clock.  Not present on all platforms
  76 +  "sleep"              Sleep clock, used when USB3 core goes into low
  77 +                               power mode (U3).
  78 +
  79 +Optional regulator:
  80 +- gdsc-supply: phandle to the regulator from globally distributed
  81 +                               switch controller
  82 +
  83 +Required child node:
  84 +A child node must exist to represent the core DWC3 IP block. The name of
  85 +the node is not important. The content of the node is defined in dwc3.txt.
  86 +
  87 +Example device nodes:
  88 +
  89 +               hs_phy_0: phy@110f8800 {
  90 +                       compatible = "qcom,dwc3-hsphy";
  91 +                       reg = <0x110f8800 0x30>;
  92 +                       clocks = <&gcc USB30_0_UTMI_CLK>;
  93 +                       clock-names = "utmi";
  94 +
  95 +                       status = "disabled";
  96 +               };
  97 +
  98 +               ss_phy_0: phy@110f8830 {
  99 +                       compatible = "qcom,dwc3-ssphy";
 100 +                       reg = <0x110f8830 0x30>;
 101 +
 102 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
 103 +                       clock-names = "ref";
 104 +
 105 +                       status = "disabled";
 106 +               };
 107 +
 108 +               usb3_0: usb30@0 {
 109 +                       compatible = "qcom,dwc3";
 110 +                       #address-cells = <1>;
 111 +                       #size-cells = <1>;
 112 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
 113 +                       clock-names = "core";
 114 +
 115 +                       ranges;
 116 +
 117 +                       status = "disabled";
 118 +
 119 +                       dwc3@11000000 {
 120 +                               compatible = "snps,dwc3";
 121 +                               reg = <0x11000000 0xcd00>;
 122 +                               interrupts = <0 110 0x4>;
 123 +                               usb-phy = <&hs_phy_0>, <&ss_phy_0>;
 124 +                               phy-names = "usb2-phy", "usb3-phy";
 125 +                               tx-fifo-resize;
 126 +                               dr_mode = "host";
 127 +                       };
 128 +               };
 129 --
 130 1.7.10.4
 131