1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
22 + pcie0_pins: pcie0_pinmux {
25 + function = "pcie1_rst";
26 + drive-strength = <12>;
31 + pcie1_pins: pcie1_pinmux {
34 + function = "pcie2_rst";
35 + drive-strength = <12>;
42 pins = "gpio18", "gpio19", "gpio21";
48 + pcie0: pci@1b500000 {
50 + reset-gpio = <&qcom_pinmux 3 0>;
51 + pinctrl-0 = <&pcie0_pins>;
52 + pinctrl-names = "default";
53 + phy-tx0-term-offset = <7>;
56 + pcie1: pci@1b700000 {
58 + reset-gpio = <&qcom_pinmux 48 0>;
59 + pinctrl-0 = <&pcie1_pins>;
60 + pinctrl-names = "default";
61 + phy-tx0-term-offset = <7>;
65 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
66 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
71 + pcie0_pins: pcie0_pinmux {
74 + function = "pcie1_rst";
75 + drive-strength = <12>;
80 + pcie1_pins: pcie1_pinmux {
83 + function = "pcie2_rst";
84 + drive-strength = <12>;
89 + pcie2_pins: pcie2_pinmux {
92 + function = "pcie3_rst";
93 + drive-strength = <12>;
100 pins = "gpio18", "gpio19", "gpio21";
106 + pcie0: pci@1b500000 {
108 + reset-gpio = <&qcom_pinmux 3 0>;
109 + pinctrl-0 = <&pcie0_pins>;
110 + pinctrl-names = "default";
113 + pcie1: pci@1b700000 {
115 + reset-gpio = <&qcom_pinmux 48 0>;
116 + pinctrl-0 = <&pcie1_pins>;
117 + pinctrl-names = "default";
120 + pcie2: pci@1b900000 {
122 + reset-gpio = <&qcom_pinmux 63 0>;
123 + pinctrl-0 = <&pcie2_pins>;
124 + pinctrl-names = "default";
128 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
129 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
131 #include "skeleton.dtsi"
132 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
133 #include <dt-bindings/soc/qcom,gsbi.h>
134 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
135 +#include <dt-bindings/interrupt-controller/arm-gic.h>
138 model = "Qualcomm IPQ8064";
139 @@ -311,6 +313,129 @@
140 reg = <0x01200600 0x100>;
143 + pcie0: pci@1b500000 {
144 + compatible = "qcom,pcie-v0";
145 + reg = <0x1b500000 0x1000
148 + 0x0ff00000 0x100000>;
149 + reg-names = "dbi", "elbi", "parf", "config";
150 + device_type = "pci";
151 + linux,pci-domain = <0>;
152 + bus-range = <0x00 0xff>;
154 + #address-cells = <3>;
157 + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
158 + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
160 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
161 + interrupt-names = "msi";
162 + #interrupt-cells = <1>;
163 + interrupt-map-mask = <0 0 0 0x7>;
164 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
165 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
166 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
167 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
169 + clocks = <&gcc PCIE_A_CLK>,
171 + <&gcc PCIE_PHY_CLK>;
172 + clock-names = "core", "iface", "phy";
174 + resets = <&gcc PCIE_ACLK_RESET>,
175 + <&gcc PCIE_HCLK_RESET>,
176 + <&gcc PCIE_POR_RESET>,
177 + <&gcc PCIE_PCI_RESET>,
178 + <&gcc PCIE_PHY_RESET>;
179 + reset-names = "axi", "ahb", "por", "pci", "phy";
181 + status = "disabled";
184 + pcie1: pci@1b700000 {
185 + compatible = "qcom,pcie-v0";
186 + reg = <0x1b700000 0x1000
189 + 0x31f00000 0x100000>;
190 + reg-names = "dbi", "elbi", "parf", "config";
191 + device_type = "pci";
192 + linux,pci-domain = <1>;
193 + bus-range = <0x00 0xff>;
195 + #address-cells = <3>;
198 + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
199 + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
201 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
202 + interrupt-names = "msi";
203 + #interrupt-cells = <1>;
204 + interrupt-map-mask = <0 0 0 0x7>;
205 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
206 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
207 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
208 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
210 + clocks = <&gcc PCIE_1_A_CLK>,
211 + <&gcc PCIE_1_H_CLK>,
212 + <&gcc PCIE_1_PHY_CLK>;
213 + clock-names = "core", "iface", "phy";
215 + resets = <&gcc PCIE_1_ACLK_RESET>,
216 + <&gcc PCIE_1_HCLK_RESET>,
217 + <&gcc PCIE_1_POR_RESET>,
218 + <&gcc PCIE_1_PCI_RESET>,
219 + <&gcc PCIE_1_PHY_RESET>;
220 + reset-names = "axi", "ahb", "por", "pci", "phy";
222 + status = "disabled";
225 + pcie2: pci@1b900000 {
226 + compatible = "qcom,pcie-v0";
227 + reg = <0x1b900000 0x1000
230 + 0x35f00000 0x100000>;
231 + reg-names = "dbi", "elbi", "parf", "config";
232 + device_type = "pci";
233 + linux,pci-domain = <2>;
234 + bus-range = <0x00 0xff>;
236 + #address-cells = <3>;
239 + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
240 + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
242 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
243 + interrupt-names = "msi";
244 + #interrupt-cells = <1>;
245 + interrupt-map-mask = <0 0 0 0x7>;
246 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
247 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
248 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
249 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
251 + clocks = <&gcc PCIE_2_A_CLK>,
252 + <&gcc PCIE_2_H_CLK>,
253 + <&gcc PCIE_2_PHY_CLK>;
254 + clock-names = "core", "iface", "phy";
256 + resets = <&gcc PCIE_2_ACLK_RESET>,
257 + <&gcc PCIE_2_HCLK_RESET>,
258 + <&gcc PCIE_2_POR_RESET>,
259 + <&gcc PCIE_2_PCI_RESET>,
260 + <&gcc PCIE_2_PHY_RESET>;
261 + reset-names = "axi", "ahb", "por", "pci", "phy";
263 + status = "disabled";
266 hs_phy_1: phy@100f8800 {
267 compatible = "qcom,dwc3-hs-usb-phy";
268 reg = <0x100f8800 0x30>;