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4 Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs
5 From: Stephen Boyd <sboyd@codeaurora.org>
6 X-Patchwork-Id: 6063241
7 Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org>
8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
10 linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
11 Viresh Kumar <viresh.kumar@linaro.org>
12 Date: Fri, 20 Mar 2015 23:45:27 -0700
14 Describe the HFPLLs present on IPQ806X devices.
16 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
19 drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++
20 1 file changed, 83 insertions(+)
22 --- a/drivers/clk/qcom/gcc-ipq806x.c
23 +++ b/drivers/clk/qcom/gcc-ipq806x.c
27 #include "clk-branch.h"
28 +#include "clk-hfpll.h"
31 static struct clk_pll pll0 = {
32 @@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
36 +static struct hfpll_data hfpll0_data = {
41 + .config_reg = 0x3204,
42 + .status_reg = 0x321c,
43 + .config_val = 0x7845c665,
44 + .droop_reg = 0x3214,
45 + .droop_val = 0x0108c000,
46 + .min_rate = 600000000UL,
47 + .max_rate = 1800000000UL,
50 +static struct clk_hfpll hfpll0 = {
52 + .clkr.hw.init = &(struct clk_init_data){
53 + .parent_names = (const char *[]){ "pxo" },
56 + .ops = &clk_ops_hfpll,
57 + .flags = CLK_IGNORE_UNUSED,
59 + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
62 +static struct hfpll_data hfpll1_data = {
67 + .config_reg = 0x3244,
68 + .status_reg = 0x325c,
69 + .config_val = 0x7845c665,
70 + .droop_reg = 0x3314,
71 + .droop_val = 0x0108c000,
72 + .min_rate = 600000000UL,
73 + .max_rate = 1800000000UL,
76 +static struct clk_hfpll hfpll1 = {
78 + .clkr.hw.init = &(struct clk_init_data){
79 + .parent_names = (const char *[]){ "pxo" },
82 + .ops = &clk_ops_hfpll,
83 + .flags = CLK_IGNORE_UNUSED,
85 + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
88 +static struct hfpll_data hfpll_l2_data = {
93 + .config_reg = 0x3304,
94 + .status_reg = 0x331c,
95 + .config_val = 0x7845c665,
96 + .droop_reg = 0x3314,
97 + .droop_val = 0x0108c000,
98 + .min_rate = 600000000UL,
99 + .max_rate = 1800000000UL,
102 +static struct clk_hfpll hfpll_l2 = {
103 + .d = &hfpll_l2_data,
104 + .clkr.hw.init = &(struct clk_init_data){
105 + .parent_names = (const char *[]){ "pxo" },
107 + .name = "hfpll_l2",
108 + .ops = &clk_ops_hfpll,
109 + .flags = CLK_IGNORE_UNUSED,
111 + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
115 static struct clk_pll pll14 = {
118 @@ -2261,6 +2341,9 @@ static struct clk_regmap *gcc_ipq806x_cl
119 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
120 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
121 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
122 + [PLL9] = &hfpll0.clkr,
123 + [PLL10] = &hfpll1.clkr,
124 + [PLL12] = &hfpll_l2.clkr,
127 static const struct qcom_reset_map gcc_ipq806x_resets[] = {