1 From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 9 Mar 2017 08:19:18 +0100
4 Subject: [PATCH 32/69] phy: add qcom dwc3 phy
6 Signed-off-by: Andy Gross <agross@codeaurora.org>
9 --- a/drivers/phy/qualcomm/Kconfig
10 +++ b/drivers/phy/qualcomm/Kconfig
11 @@ -65,3 +65,15 @@ config PHY_QCOM_USB_HSIC
14 Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
17 + tristate "QCOM DWC3 USB PHY support"
18 + depends on ARCH_QCOM
19 + depends on HAS_IOMEM
23 + This option enables support for the Synopsis PHYs present inside the
24 + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
27 --- a/drivers/phy/qualcomm/Makefile
28 +++ b/drivers/phy/qualcomm/Makefile
29 @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-
30 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
31 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
32 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
33 +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
35 +++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
37 +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License version 2 and
41 + * only version 2 as published by the Free Software Foundation.
43 +* This program is distributed in the hope that it will be useful,
44 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
45 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 +* GNU General Public License for more details.
49 +#include <linux/clk.h>
50 +#include <linux/err.h>
51 +#include <linux/io.h>
52 +#include <linux/module.h>
53 +#include <linux/of.h>
54 +#include <linux/phy/phy.h>
55 +#include <linux/platform_device.h>
56 +#include <linux/delay.h>
57 +#include <linux/regmap.h>
58 +#include <linux/mfd/syscon.h>
61 + * USB QSCRATCH Hardware registers
63 +#define QSCRATCH_GENERAL_CFG (0x08)
64 +#define HSUSB_PHY_CTRL_REG (0x10)
67 +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
68 +#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
69 +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
70 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
71 +#define HSUSB_CTRL_USE_CLKCORE BIT(18)
72 +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
73 +#define HSUSB_CTRL_COMMONONN BIT(11)
74 +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
75 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
76 +#define HSUSB_CTRL_CLAMP_EN BIT(7)
77 +#define HSUSB_CTRL_RETENABLEN BIT(1)
78 +#define HSUSB_CTRL_POR BIT(0)
80 +/* QSCRATCH_GENERAL_CFG */
81 +#define HSUSB_GCFG_XHCI_REV BIT(2)
84 + * USB QSCRATCH Hardware registers
86 +#define SSUSB_PHY_CTRL_REG (0x30)
87 +#define SSUSB_PHY_PARAM_CTRL_1 (0x34)
88 +#define SSUSB_PHY_PARAM_CTRL_2 (0x38)
89 +#define CR_PROTOCOL_DATA_IN_REG (0x3c)
90 +#define CR_PROTOCOL_DATA_OUT_REG (0x40)
91 +#define CR_PROTOCOL_CAP_ADDR_REG (0x44)
92 +#define CR_PROTOCOL_CAP_DATA_REG (0x48)
93 +#define CR_PROTOCOL_READ_REG (0x4c)
94 +#define CR_PROTOCOL_WRITE_REG (0x50)
97 +#define SSUSB_CTRL_REF_USE_PAD BIT(28)
98 +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
99 +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
100 +#define SSUSB_CTRL_SS_PHY_EN BIT(8)
101 +#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
103 +/* SSPHY control registers - Does this need 0x30? */
104 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
105 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
107 +/* SSPHY SoC version specific values */
108 +#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
109 +#define SSPHY_TX_DEEMPH_3_5DB 23 /* Override value for transmit
111 +#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */
113 +/* QSCRATCH PHY_PARAM_CTRL1 fields */
114 +#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u
115 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u
116 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u
117 +#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u
119 +#define PHY_PARAM_CTRL1_MASK \
120 + (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
121 + PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
122 + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
123 + PHY_PARAM_CTRL1_LOS_BIAS_MASK)
125 +#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
126 + (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
127 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
128 + (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
129 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
130 + (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
131 +#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
132 + (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
134 +/* RX OVRD IN HI bits */
135 +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
136 +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
137 +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
138 +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
139 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
140 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
141 +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
142 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
143 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
144 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
145 +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
147 +/* TX OVRD DRV LO register bits */
148 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
149 +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
150 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
151 +#define TX_OVRD_DRV_LO_EN BIT(14)
153 +/* SS CAP register bits */
154 +#define SS_CR_CAP_ADDR_REG BIT(0)
155 +#define SS_CR_CAP_DATA_REG BIT(0)
156 +#define SS_CR_READ_REG BIT(0)
157 +#define SS_CR_WRITE_REG BIT(0)
159 +struct qcom_dwc3_usb_phy {
160 + struct regmap *base;
161 + struct device *dev;
162 + struct clk *xo_clk;
163 + struct clk *ref_clk;
165 + u32 tx_deamp_3_5db;
169 +struct qcom_dwc3_phy_drvdata {
170 + struct phy_ops ops;
175 + * Write register and read back masked value to confirm it is written
177 + * @base - QCOM DWC3 PHY base virtual address.
178 + * @offset - register offset.
179 + * @mask - register bitmask specifying what should be updated
180 + * @val - value to write.
182 +static inline void qcom_dwc3_phy_write_readback(
183 + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
184 + const u32 mask, u32 val)
186 + u32 write_val, tmp;
188 + tmp = regmap_read(phy_dwc3->base, offset, &tmp);
189 + tmp &= ~mask; /* retain other bits */
190 + write_val = tmp | val;
192 + regmap_write(phy_dwc3->base, offset, write_val);
194 + /* Read back to see if val was written */
195 + regmap_read(phy_dwc3->base, offset, &tmp);
196 + tmp &= mask; /* clear other bits */
199 + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
203 +static int wait_for_latch(struct regmap *base, u32 addr)
205 + u32 retry = 10, data;
208 + regmap_read(base, addr, &data);
215 + usleep_range(10, 20);
222 + * Write SSPHY register
224 + * @base - QCOM DWC3 PHY base virtual address.
225 + * @addr - SSPHY address to write.
226 + * @val - value to write.
228 +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
233 + regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, addr);
234 + regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
236 + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG);
240 + regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, val);
241 + regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG, SS_CR_CAP_DATA_REG);
243 + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG);
247 + regmap_write(phy_dwc3->base, CR_PROTOCOL_WRITE_REG, SS_CR_WRITE_REG);
249 + ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_WRITE_REG);
253 + dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
258 + * Read SSPHY register.
260 + * @base - QCOM DWC3 PHY base virtual address.
261 + * @addr - SSPHY address to read.
263 +static int qcom_dwc3_ss_read_phycreg(struct regmap *base, u32 addr, u32 *val)
267 + regmap_write(base, CR_PROTOCOL_DATA_IN_REG, addr);
268 + regmap_write(base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
270 + ret = wait_for_latch(base, CR_PROTOCOL_CAP_ADDR_REG);
275 + * Due to hardware bug, first read of SSPHY register might be
276 + * incorrect. Hence as workaround, SW should perform SSPHY register
277 + * read twice, but use only second read and ignore first read.
279 + regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
281 + ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
285 + /* throwaway read */
286 + regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, &ret);
288 + regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
290 + ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
294 + regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, val);
300 +static int qcom_dwc3_hs_phy_init(struct phy *phy)
302 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
306 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
310 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
312 + clk_disable_unprepare(phy_dwc3->xo_clk);
317 + * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
318 + * enable clamping, and disable RETENTION (power-on default is ENABLED)
320 + val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
321 + HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
322 + HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
323 + HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
324 + HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
326 + /* use core clock if external reference is not present */
327 + if (!phy_dwc3->xo_clk)
328 + val |= HSUSB_CTRL_USE_CLKCORE;
330 + regmap_write(phy_dwc3->base, HSUSB_PHY_CTRL_REG, val);
331 + usleep_range(2000, 2200);
333 + /* Disable (bypass) VBUS and ID filters */
334 + regmap_write(phy_dwc3->base, QSCRATCH_GENERAL_CFG, HSUSB_GCFG_XHCI_REV);
339 +static int qcom_dwc3_hs_phy_exit(struct phy *phy)
341 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
343 + clk_disable_unprepare(phy_dwc3->ref_clk);
344 + clk_disable_unprepare(phy_dwc3->xo_clk);
349 +static int qcom_dwc3_ss_phy_init(struct phy *phy)
351 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
355 + ret = clk_prepare_enable(phy_dwc3->xo_clk);
359 + ret = clk_prepare_enable(phy_dwc3->ref_clk);
361 + clk_disable_unprepare(phy_dwc3->xo_clk);
366 + regmap_read(phy_dwc3->base, SSUSB_PHY_CTRL_REG, &data);
367 + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG,
368 + data | SSUSB_CTRL_SS_PHY_RESET);
369 + usleep_range(2000, 2200);
370 + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
372 + /* clear REF_PAD if we don't have XO clk */
373 + if (!phy_dwc3->xo_clk)
374 + data &= ~SSUSB_CTRL_REF_USE_PAD;
376 + data |= SSUSB_CTRL_REF_USE_PAD;
378 + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
380 + /* wait for ref clk to become stable, this can take up to 30ms */
383 + data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
384 + regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
387 + * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
388 + * in HS mode instead of SS mode. Workaround it by asserting
389 + * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
391 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
393 + goto err_phy_trans;
396 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
398 + goto err_phy_trans;
400 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
402 + goto err_phy_trans;
406 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
408 + goto err_phy_trans;
411 + * Fix RX Equalization setting as follows
412 + * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
413 + * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
414 + * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
415 + * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
417 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
418 + SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
420 + goto err_phy_trans;
422 + data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
423 + data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
424 + data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
425 + data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT;
426 + data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
427 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
428 + SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
430 + goto err_phy_trans;
433 + * Set EQ and TX launch amplitudes as follows
434 + * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
435 + * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
436 + * LANE0.TX_OVRD_DRV_LO.EN set to 1.
438 + ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
439 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
441 + goto err_phy_trans;
443 + data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
444 + data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
445 + data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
447 + data |= TX_OVRD_DRV_LO_EN;
448 + ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
449 + SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
451 + goto err_phy_trans;
453 + qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll);
456 + * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
457 + * TX_FULL_SWING [26:20] amplitude to 110
458 + * TX_DEEMPH_6DB [19:14] to 32
459 + * TX_DEEMPH_3_5DB [13:8] set based on SoC version
460 + * LOS_BIAS [7:3] to 9
462 + regmap_read(phy_dwc3->base, SSUSB_PHY_PARAM_CTRL_1, &data);
464 + data &= ~PHY_PARAM_CTRL1_MASK;
466 + data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
467 + PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
468 + PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
469 + PHY_PARAM_CTRL1_LOS_BIAS(0x9);
471 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
472 + PHY_PARAM_CTRL1_MASK, data);
478 +static int qcom_dwc3_ss_phy_exit(struct phy *phy)
480 + struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
482 + /* Sequence to put SSPHY in low power state:
483 + * 1. Clear REF_PHY_EN in PHY_CTRL_REG
484 + * 2. Clear REF_USE_PAD in PHY_CTRL_REG
485 + * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
487 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
488 + SSUSB_CTRL_SS_PHY_EN, 0x0);
489 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
490 + SSUSB_CTRL_REF_USE_PAD, 0x0);
491 + qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
492 + SSUSB_CTRL_TEST_POWERDOWN, 0x0);
494 + clk_disable_unprepare(phy_dwc3->ref_clk);
495 + clk_disable_unprepare(phy_dwc3->xo_clk);
500 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
502 + .init = qcom_dwc3_hs_phy_init,
503 + .exit = qcom_dwc3_hs_phy_exit,
504 + .owner = THIS_MODULE,
506 + .clk_rate = 60000000,
509 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
511 + .init = qcom_dwc3_ss_phy_init,
512 + .exit = qcom_dwc3_ss_phy_exit,
513 + .owner = THIS_MODULE,
515 + .clk_rate = 125000000,
518 +static const struct of_device_id qcom_dwc3_phy_table[] = {
519 + { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
520 + { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
523 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
525 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
527 + struct qcom_dwc3_usb_phy *phy_dwc3;
528 + struct phy_provider *phy_provider;
529 + struct phy *generic_phy;
530 + struct resource *res;
531 + const struct of_device_id *match;
532 + const struct qcom_dwc3_phy_drvdata *data;
533 + struct device_node *np;
535 + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
539 + match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
540 + data = match->data;
542 + phy_dwc3->dev = &pdev->dev;
544 + phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
545 + if (IS_ERR_OR_NULL(phy_dwc3->base))
546 + return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL;
548 + phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
549 + if (IS_ERR(phy_dwc3->ref_clk)) {
550 + dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
551 + return PTR_ERR(phy_dwc3->ref_clk);
554 + clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
556 + phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
557 + if (IS_ERR(phy_dwc3->xo_clk)) {
558 + dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
559 + phy_dwc3->xo_clk = NULL;
562 + /* Parse device node to probe HSIO settings */
563 + np = of_node_get(pdev->dev.of_node);
564 + if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy",
565 + strlen(match->compatible))) {
567 + if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) ||
568 + of_property_read_u32(np, "tx_deamp_3_5db",
569 + &phy_dwc3->tx_deamp_3_5db) ||
570 + of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) {
572 + dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n");
574 + /* Default HSIO settings */
575 + phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
576 + phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
577 + phy_dwc3->mpll = SSPHY_MPLL_VALUE;
581 + generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
584 + if (IS_ERR(generic_phy))
585 + return PTR_ERR(generic_phy);
587 + phy_set_drvdata(generic_phy, phy_dwc3);
588 + platform_set_drvdata(pdev, phy_dwc3);
590 + phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
591 + of_phy_simple_xlate);
593 + if (IS_ERR(phy_provider))
594 + return PTR_ERR(phy_provider);
599 +static struct platform_driver qcom_dwc3_phy_driver = {
600 + .probe = qcom_dwc3_phy_probe,
602 + .name = "qcom-dwc3-usb-phy",
603 + .owner = THIS_MODULE,
604 + .of_match_table = qcom_dwc3_phy_table,
608 +module_platform_driver(qcom_dwc3_phy_driver);
610 +MODULE_ALIAS("platform:phy-qcom-dwc3");
611 +MODULE_LICENSE("GPL v2");
612 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
613 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
614 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");