1 From bb5c4a85051e5e0be39c775b6df85521f2ae807d Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Tue, 14 Aug 2018 17:42:29 +0530
4 Subject: [PATCH 10/12] clk: qcom: Add Krait clock controller driver
6 The Krait CPU clocks are made up of a primary mux and secondary
7 mux for each CPU and the L2, controlled via cp15 accessors. For
8 Kraits within KPSSv1 each secondary mux accepts a different aux
9 source, but on KPSSv2 each secondary mux accepts the same aux
12 Cc: <devicetree@vger.kernel.org>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
15 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
16 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
18 drivers/clk/qcom/Kconfig | 8 +
19 drivers/clk/qcom/Makefile | 1 +
20 drivers/clk/qcom/clk-krait.c | 4 +-
21 drivers/clk/qcom/krait-cc.c | 341 +++++++++++++++++++++++++++++++++++
22 4 files changed, 352 insertions(+), 2 deletions(-)
23 create mode 100644 drivers/clk/qcom/krait-cc.c
25 --- a/drivers/clk/qcom/Kconfig
26 +++ b/drivers/clk/qcom/Kconfig
27 @@ -292,3 +292,11 @@ config KPSS_XCC
28 Support for the Krait ACC and GCC clock controllers. Say Y
29 if you want to support CPU frequency scaling on devices such
30 as MSM8960, APQ8064, etc.
33 + tristate "Krait Clock Controller"
34 + depends on COMMON_CLK_QCOM && ARM
37 + Support for the Krait CPU clocks on Qualcomm devices.
38 + Say Y if you want to support CPU frequency scaling.
39 --- a/drivers/clk/qcom/Makefile
40 +++ b/drivers/clk/qcom/Makefile
41 @@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc
42 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
43 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
44 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
45 +obj-$(CONFIG_KRAITCC) += krait-cc.o
46 --- a/drivers/clk/qcom/clk-krait.c
47 +++ b/drivers/clk/qcom/clk-krait.c
48 @@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct c
49 struct krait_mux_clk *mux = to_krait_mux_clk(hw);
52 - sel = clk_mux_reindex(index, mux->parent_map, 0);
53 + sel = clk_mux_index_to_val(mux->parent_map, 0, index);
55 /* Don't touch mux if CPU is off as it won't work */
56 if (__clk_is_enabled(hw->clk))
57 @@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct cl
61 - return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
62 + return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
65 const struct clk_ops krait_mux_clk_ops = {
67 +++ b/drivers/clk/qcom/krait-cc.c
69 +// SPDX-License-Identifier: GPL-2.0
70 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
72 +#include <linux/kernel.h>
73 +#include <linux/init.h>
74 +#include <linux/module.h>
75 +#include <linux/platform_device.h>
76 +#include <linux/err.h>
77 +#include <linux/io.h>
78 +#include <linux/of.h>
79 +#include <linux/of_device.h>
80 +#include <linux/clk.h>
81 +#include <linux/clk-provider.h>
82 +#include <linux/slab.h>
84 +#include "clk-krait.h"
86 +static unsigned int sec_mux_map[] = {
91 +static unsigned int pri_mux_map[] = {
98 +krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
100 + struct krait_div2_clk *div;
101 + struct clk_init_data init = {
103 + .ops = &krait_div2_clk_ops,
104 + .flags = CLK_SET_RATE_PARENT,
106 + const char *p_names[1];
109 + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
115 + div->lpl = id >= 0;
116 + div->offset = offset;
117 + div->hw.init = &init;
119 + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
123 + init.parent_names = p_names;
124 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
130 + clk = devm_clk_register(dev, &div->hw);
134 + return PTR_ERR_OR_ZERO(clk);
138 +krait_add_sec_mux(struct device *dev, int id, const char *s,
139 + unsigned int offset, bool unique_aux)
141 + struct krait_mux_clk *mux;
142 + static const char *sec_mux_list[] = {
146 + struct clk_init_data init = {
147 + .parent_names = sec_mux_list,
148 + .num_parents = ARRAY_SIZE(sec_mux_list),
149 + .ops = &krait_mux_clk_ops,
150 + .flags = CLK_SET_RATE_PARENT,
154 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
158 + mux->offset = offset;
159 + mux->lpl = id >= 0;
162 + mux->parent_map = sec_mux_map;
163 + mux->hw.init = &init;
165 + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
170 + sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
171 + if (!sec_mux_list[0]) {
172 + clk = ERR_PTR(-ENOMEM);
177 + clk = devm_clk_register(dev, &mux->hw);
180 + kfree(sec_mux_list[0]);
183 + return PTR_ERR_OR_ZERO(clk);
187 +krait_add_pri_mux(struct device *dev, int id, const char *s,
188 + unsigned int offset)
190 + struct krait_mux_clk *mux;
191 + const char *p_names[3];
192 + struct clk_init_data init = {
193 + .parent_names = p_names,
194 + .num_parents = ARRAY_SIZE(p_names),
195 + .ops = &krait_mux_clk_ops,
196 + .flags = CLK_SET_RATE_PARENT,
200 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
202 + return ERR_PTR(-ENOMEM);
206 + mux->offset = offset;
207 + mux->lpl = id >= 0;
208 + mux->parent_map = pri_mux_map;
209 + mux->hw.init = &init;
211 + init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
213 + return ERR_PTR(-ENOMEM);
215 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
217 + clk = ERR_PTR(-ENOMEM);
221 + p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
223 + clk = ERR_PTR(-ENOMEM);
227 + p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
229 + clk = ERR_PTR(-ENOMEM);
233 + clk = devm_clk_register(dev, &mux->hw);
245 +/* id < 0 for L2, otherwise id == physical CPU number */
246 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
249 + unsigned int offset;
255 + offset = 0x4501 + (0x1000 * id);
256 + s = p = kasprintf(GFP_KERNEL, "%d", id);
258 + return ERR_PTR(-ENOMEM);
264 + ret = krait_add_div(dev, id, s, offset);
266 + clk = ERR_PTR(ret);
270 + ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
272 + clk = ERR_PTR(ret);
276 + clk = krait_add_pri_mux(dev, id, s, offset);
282 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
284 + unsigned int idx = clkspec->args[0];
285 + struct clk **clks = data;
288 + pr_err("%s: invalid clock index %d\n", __func__, idx);
289 + return ERR_PTR(-EINVAL);
292 + return clks[idx] ? : ERR_PTR(-ENODEV);
295 +static const struct of_device_id krait_cc_match_table[] = {
296 + { .compatible = "qcom,krait-cc-v1", (void *)1UL },
297 + { .compatible = "qcom,krait-cc-v2" },
300 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
302 +static int krait_cc_probe(struct platform_device *pdev)
304 + struct device *dev = &pdev->dev;
305 + const struct of_device_id *id;
306 + unsigned long cur_rate, aux_rate;
310 + struct clk *l2_pri_mux_clk;
312 + id = of_match_device(krait_cc_match_table, dev);
316 + /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
317 + clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
319 + return PTR_ERR(clk);
322 + clk = clk_register_fixed_factor(dev, "acpu_aux",
323 + "gpll0_vote", 0, 1, 2);
325 + return PTR_ERR(clk);
328 + /* Krait configurations have at most 4 CPUs and one L2 */
329 + clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
333 + for_each_possible_cpu(cpu) {
334 + clk = krait_add_clks(dev, cpu, id->data);
336 + return PTR_ERR(clk);
340 + l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
341 + if (IS_ERR(l2_pri_mux_clk))
342 + return PTR_ERR(l2_pri_mux_clk);
343 + clks[4] = l2_pri_mux_clk;
346 + * We don't want the CPU or L2 clocks to be turned off at late init
347 + * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
348 + * refcount of these clocks. Any cpufreq/hotplug manager can assume
349 + * that the clocks have already been prepared and enabled by the time
352 + for_each_online_cpu(cpu) {
353 + clk_prepare_enable(l2_pri_mux_clk);
354 + WARN(clk_prepare_enable(clks[cpu]),
355 + "Unable to turn on CPU%d clock", cpu);
359 + * Force reinit of HFPLLs and muxes to overwrite any potential
360 + * incorrect configuration of HFPLLs and muxes by the bootloader.
361 + * While at it, also make sure the cores are running at known rates
362 + * and print the current rate.
364 + * The clocks are set to aux clock rate first to make sure the
365 + * secondary mux is not sourcing off of QSB. The rate is then set to
366 + * two different rates to force a HFPLL reinit under all
369 + cur_rate = clk_get_rate(l2_pri_mux_clk);
370 + aux_rate = 384000000;
371 + if (cur_rate == 1) {
372 + pr_info("L2 @ QSB rate. Forcing new rate.\n");
373 + cur_rate = aux_rate;
375 + clk_set_rate(l2_pri_mux_clk, aux_rate);
376 + clk_set_rate(l2_pri_mux_clk, 2);
377 + clk_set_rate(l2_pri_mux_clk, cur_rate);
378 + pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
379 + for_each_possible_cpu(cpu) {
381 + cur_rate = clk_get_rate(clk);
382 + if (cur_rate == 1) {
383 + pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
384 + cur_rate = aux_rate;
387 + clk_set_rate(clk, aux_rate);
388 + clk_set_rate(clk, 2);
389 + clk_set_rate(clk, cur_rate);
390 + pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
393 + of_clk_add_provider(dev->of_node, krait_of_get, clks);
398 +static struct platform_driver krait_cc_driver = {
399 + .probe = krait_cc_probe,
401 + .name = "krait-cc",
402 + .of_match_table = krait_cc_match_table,
405 +module_platform_driver(krait_cc_driver);
407 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
408 +MODULE_LICENSE("GPL v2");
409 +MODULE_ALIAS("platform:krait-cc");