1 From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001
2 From: Sham Muthayyan <smuthayy@codeaurora.org>
3 Date: Tue, 19 Jul 2016 19:58:22 +0530
4 Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
6 Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
7 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
10 --- a/drivers/pci/controller/dwc/pcie-qcom.c
11 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
13 #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
15 #define PCIE20_PARF_PHY_CTRL 0x40
16 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
17 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
19 #define PCIE20_PARF_PHY_REFCLK 0x4C
20 +#define REF_SSP_EN BIT(16)
21 +#define REF_USE_PAD BIT(12)
23 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
24 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
25 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
27 #define DBI_RO_WR_EN 1
29 #define PERST_DELAY_US 1000
31 +#define PCIE20_PARF_PCS_DEEMPH 0x34
32 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
33 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
34 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
36 +#define PCIE20_PARF_PCS_SWING 0x38
37 +#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
38 +#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
40 +#define PCIE20_PARF_CONFIG_BITS 0x50
41 +#define PHY_RX0_EQ(x) (x << 24)
43 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
44 #define SLV_ADDR_SPACE_SZ 0x10000000
45 @@ -94,6 +112,7 @@ struct qcom_pcie_resources_2_1_0 {
46 struct reset_control *phy_reset;
47 struct reset_control *ext_reset;
48 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
49 + uint8_t phy_tx0_term_offset;
52 struct qcom_pcie_resources_1_0_0 {
53 @@ -173,6 +192,16 @@ struct qcom_pcie {
55 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
58 +writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
60 + u32 val = readl(addr);
67 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
69 gpiod_set_value_cansleep(pcie->reset, 1);
70 @@ -266,6 +295,10 @@ static int qcom_pcie_get_resources_2_1_0
71 if (IS_ERR(res->ext_reset))
72 return PTR_ERR(res->ext_reset);
74 + if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
75 + &res->phy_tx0_term_offset))
76 + res->phy_tx0_term_offset = 0;
78 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
79 return PTR_ERR_OR_ZERO(res->phy_reset);
81 @@ -293,7 +326,6 @@ static int qcom_pcie_init_2_1_0(struct q
82 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
83 struct dw_pcie *pci = pcie->pci;
84 struct device *dev = pci->dev;
88 ret = reset_control_assert(res->ahb_reset);
89 @@ -350,15 +382,26 @@ static int qcom_pcie_init_2_1_0(struct q
90 goto err_deassert_ahb;
93 - /* enable PCIe clocks and resets */
94 - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
96 - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
98 - /* enable external reference clock */
99 - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
101 - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
102 + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
104 + /* Set Tx termination offset */
105 + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
106 + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
107 + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
109 + /* PARF programming */
110 + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
111 + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
112 + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
113 + pcie->parf + PCIE20_PARF_PCS_DEEMPH);
114 + writel(PCS_SWING_TX_SWING_FULL(0x78) |
115 + PCS_SWING_TX_SWING_LOW(0x78),
116 + pcie->parf + PCIE20_PARF_PCS_SWING);
117 + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
119 + /* Enable reference clock */
120 + writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
121 + REF_USE_PAD, REF_SSP_EN);
123 ret = reset_control_deassert(res->phy_reset);