1 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
2 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
8 + phy@100f8800 { /* USB3 port 1 HS phy */
12 + phy@100f8830 { /* USB3 port 1 SS phy */
16 + phy@110f8800 { /* USB3 port 0 HS phy */
20 + phy@110f8830 { /* USB3 port 0 SS phy */
33 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
34 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
36 compatible = "syscon";
37 reg = <0x01200600 0x100>;
40 + hs_phy_1: phy@100f8800 {
41 + compatible = "qcom,dwc3-hs-usb-phy";
42 + reg = <0x100f8800 0x30>;
43 + clocks = <&gcc USB30_1_UTMI_CLK>;
44 + clock-names = "ref";
47 + status = "disabled";
50 + ss_phy_1: phy@100f8830 {
51 + compatible = "qcom,dwc3-ss-usb-phy";
52 + reg = <0x100f8830 0x30>;
53 + clocks = <&gcc USB30_1_MASTER_CLK>;
54 + clock-names = "ref";
57 + status = "disabled";
60 + hs_phy_0: phy@110f8800 {
61 + compatible = "qcom,dwc3-hs-usb-phy";
62 + reg = <0x110f8800 0x30>;
63 + clocks = <&gcc USB30_0_UTMI_CLK>;
64 + clock-names = "ref";
67 + status = "disabled";
70 + ss_phy_0: phy@110f8830 {
71 + compatible = "qcom,dwc3-ss-usb-phy";
72 + reg = <0x110f8830 0x30>;
73 + clocks = <&gcc USB30_0_MASTER_CLK>;
74 + clock-names = "ref";
77 + status = "disabled";
81 + compatible = "qcom,dwc3";
82 + #address-cells = <1>;
84 + clocks = <&gcc USB30_0_MASTER_CLK>;
85 + clock-names = "core";
89 + status = "disabled";
92 + compatible = "snps,dwc3";
93 + reg = <0x11000000 0xcd00>;
94 + interrupts = <0 110 0x4>;
95 + phys = <&hs_phy_0>, <&ss_phy_0>;
96 + phy-names = "usb2-phy", "usb3-phy";
103 + compatible = "qcom,dwc3";
104 + #address-cells = <1>;
106 + clocks = <&gcc USB30_1_MASTER_CLK>;
107 + clock-names = "core";
111 + status = "disabled";
114 + compatible = "snps,dwc3";
115 + reg = <0x10000000 0xcd00>;
116 + interrupts = <0 205 0x4>;
117 + phys = <&hs_phy_1>, <&ss_phy_1>;
118 + phy-names = "usb2-phy", "usb3-phy";
125 sfpb_mutex: sfpb-mutex {