1 From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Mon, 11 May 2015 12:29:18 -0700
4 Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
6 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
10 arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
11 3 files changed, 160 insertions(+)
13 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
14 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
20 + rgmii2_pins: rgmii2_pins {
22 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
23 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
24 + function = "rgmii2";
25 + drive-strength = <8>;
37 + gmac1: ethernet@37200000 {
42 + pinctrl-0 = <&rgmii2_pins>;
43 + pinctrl-names = "default";
51 + gmac2: ethernet@37400000 {
64 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
65 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
71 + rgmii0_pins: rgmii0_pins {
73 + pins = "gpio2", "gpio66";
74 + drive-strength = <8>;
80 gsbi2: gsbi@12480000 {
86 + gmac0: ethernet@37000000 {
90 + phy-handle = <&phy4>;
92 + pinctrl-0 = <&rgmii0_pins>;
93 + pinctrl-names = "default";
96 + gmac1: ethernet@37200000 {
107 + gmac2: ethernet@37400000 {
109 + phy-mode = "sgmii";
111 + phy-handle = <&phy6>;
114 + gmac3: ethernet@37600000 {
116 + phy-mode = "sgmii";
118 + phy-handle = <&phy7>;
122 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
123 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
129 + nss_common: syscon@03000000 {
130 + compatible = "syscon";
131 + reg = <0x03000000 0x0000FFFF>;
134 + qsgmii_csr: syscon@1bb00000 {
135 + compatible = "syscon";
136 + reg = <0x1bb00000 0x000001FF>;
139 + gmac0: ethernet@37000000 {
140 + device_type = "network";
141 + compatible = "qcom,ipq806x-gmac";
142 + reg = <0x37000000 0x200000>;
143 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
144 + interrupt-names = "macirq";
146 + qcom,nss-common = <&nss_common>;
147 + qcom,qsgmii-csr = <&qsgmii_csr>;
149 + clocks = <&gcc GMAC_CORE1_CLK>;
150 + clock-names = "stmmaceth";
152 + resets = <&gcc GMAC_CORE1_RESET>;
153 + reset-names = "stmmaceth";
155 + status = "disabled";
158 + gmac1: ethernet@37200000 {
159 + device_type = "network";
160 + compatible = "qcom,ipq806x-gmac";
161 + reg = <0x37200000 0x200000>;
162 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
163 + interrupt-names = "macirq";
165 + qcom,nss-common = <&nss_common>;
166 + qcom,qsgmii-csr = <&qsgmii_csr>;
168 + clocks = <&gcc GMAC_CORE2_CLK>;
169 + clock-names = "stmmaceth";
171 + resets = <&gcc GMAC_CORE2_RESET>;
172 + reset-names = "stmmaceth";
174 + status = "disabled";
177 + gmac2: ethernet@37400000 {
178 + device_type = "network";
179 + compatible = "qcom,ipq806x-gmac";
180 + reg = <0x37400000 0x200000>;
181 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
182 + interrupt-names = "macirq";
184 + qcom,nss-common = <&nss_common>;
185 + qcom,qsgmii-csr = <&qsgmii_csr>;
187 + clocks = <&gcc GMAC_CORE3_CLK>;
188 + clock-names = "stmmaceth";
190 + resets = <&gcc GMAC_CORE3_RESET>;
191 + reset-names = "stmmaceth";
193 + status = "disabled";
196 + gmac3: ethernet@37600000 {
197 + device_type = "network";
198 + compatible = "qcom,ipq806x-gmac";
199 + reg = <0x37600000 0x200000>;
200 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
201 + interrupt-names = "macirq";
203 + qcom,nss-common = <&nss_common>;
204 + qcom,qsgmii-csr = <&qsgmii_csr>;
206 + clocks = <&gcc GMAC_CORE4_CLK>;
207 + clock-names = "stmmaceth";
209 + resets = <&gcc GMAC_CORE4_RESET>;
210 + reset-names = "stmmaceth";
212 + status = "disabled";
216 sfpb_mutex: sfpb-mutex {