target/linux/ipq806x/patches-5.4/700-net-mdio-add-ipq8064-mdio-driver.patch

   1 From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001
   2 From: Christian Lamparter <chunkeey@gmail.com>
   3 Date: Sat, 2 Feb 2019 02:48:35 +0100
   4 Subject: [PATCH] net: mdio: add ipq8064 mdio driver
   5
   6 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
   7 ---
   8  drivers/net/phy/Kconfig        |   8 ++
   9  drivers/net/phy/Makefile       |   1 +
  10  drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++
  11  3 files changed, 172 insertions(+)
  12  create mode 100644 drivers/net/phy/mdio-ipq8064.c
  13
  14 --- a/drivers/net/phy/Kconfig
  15 +++ b/drivers/net/phy/Kconfig
  16 @@ -156,6 +156,14 @@ config MDIO_I2C
  17
  18           This is library mode.
  19
  20 +config MDIO_IPQ8064
  21 +       tristate "Qualcomm IPQ8064 MDIO interface support"
  22 +       depends on HAS_IOMEM && OF_MDIO
  23 +       depends on MFD_SYSCON
  24 +       help
  25 +         This driver supports the MDIO interface found in the network
  26 +         interface units of the IPQ8064 SoC
  27 +
  28  config MDIO_MOXART
  29         tristate "MOXA ART MDIO interface support"
  30         depends on ARCH_MOXART || COMPILE_TEST
  31 --- a/drivers/net/phy/Makefile
  32 +++ b/drivers/net/phy/Makefile
  33 @@ -51,6 +51,7 @@ obj-$(CONFIG_MDIO_CAVIUM)     += mdio-cavium
  34  obj-$(CONFIG_MDIO_GPIO)                += mdio-gpio.o
  35  obj-$(CONFIG_MDIO_HISI_FEMAC)  += mdio-hisi-femac.o
  36  obj-$(CONFIG_MDIO_I2C)         += mdio-i2c.o
  37 +obj-$(CONFIG_MDIO_IPQ8064)     += mdio-ipq8064.o
  38  obj-$(CONFIG_MDIO_MOXART)      += mdio-moxart.o
  39  obj-$(CONFIG_MDIO_MSCC_MIIM)   += mdio-mscc-miim.o
  40  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  41 --- /dev/null
  42 +++ b/drivers/net/phy/mdio-ipq8064.c
  43 @@ -0,0 +1,163 @@
  44 +// SPDX-License-Identifier: GPL-2.0
  45 +//
  46 +// Qualcomm IPQ8064 MDIO interface driver
  47 +//
  48 +// Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
  49 +
  50 +#include <linux/delay.h>
  51 +#include <linux/kernel.h>
  52 +#include <linux/module.h>
  53 +#include <linux/regmap.h>
  54 +#include <linux/of_mdio.h>
  55 +#include <linux/phy.h>
  56 +#include <linux/platform_device.h>
  57 +#include <linux/mfd/syscon.h>
  58 +
  59 +/* MII address register definitions */
  60 +#define MII_ADDR_REG_ADDR                       0x10
  61 +#define MII_BUSY                                BIT(0)
  62 +#define MII_WRITE                               BIT(1)
  63 +#define MII_CLKRANGE_60_100M                    (0 << 2)
  64 +#define MII_CLKRANGE_100_150M                   (1 << 2)
  65 +#define MII_CLKRANGE_20_35M                     (2 << 2)
  66 +#define MII_CLKRANGE_35_60M                     (3 << 2)
  67 +#define MII_CLKRANGE_150_250M                   (4 << 2)
  68 +#define MII_CLKRANGE_250_300M                   (5 << 2)
  69 +#define MII_CLKRANGE_MASK                      GENMASK(4, 2)
  70 +#define MII_REG_SHIFT                          6
  71 +#define MII_REG_MASK                           GENMASK(10, 6)
  72 +#define MII_ADDR_SHIFT                         11
  73 +#define MII_ADDR_MASK                          GENMASK(15, 11)
  74 +
  75 +#define MII_DATA_REG_ADDR                       0x14
  76 +
  77 +#define MII_MDIO_DELAY                          (1000)
  78 +#define MII_MDIO_RETRY                          (10)
  79 +
  80 +struct ipq8064_mdio {
  81 +       struct regmap *base; /* NSS_GMAC0_BASE */
  82 +};
  83 +
  84 +static int
  85 +ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
  86 +{
  87 +       int i;
  88 +
  89 +       for (i = 0; i < MII_MDIO_RETRY; i++) {
  90 +               unsigned int busy;
  91 +
  92 +               regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy);
  93 +               if (!(busy & MII_BUSY))
  94 +                       return 0;
  95 +
  96 +               udelay(MII_MDIO_DELAY);
  97 +       }
  98 +
  99 +       return -ETIMEDOUT;
 100 +}
 101 +
 102 +static int
 103 +ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
 104 +{
 105 +       struct ipq8064_mdio *priv = bus->priv;
 106 +       u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
 107 +       u32 ret_val;
 108 +       int err;
 109 +
 110 +       miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
 111 +                  ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
 112 +
 113 +       regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
 114 +       udelay(10);
 115 +
 116 +       err = ipq8064_mdio_wait_busy(priv);
 117 +       if (err)
 118 +               return err;
 119 +
 120 +       regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val);
 121 +       return (int)ret_val;
 122 +}
 123 +
 124 +static int
 125 +ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
 126 +{
 127 +       struct ipq8064_mdio *priv = bus->priv;
 128 +       u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
 129 +
 130 +       regmap_write(priv->base, MII_DATA_REG_ADDR, data);
 131 +
 132 +       miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
 133 +                  ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
 134 +
 135 +       regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
 136 +       udelay(10);
 137 +
 138 +       return ipq8064_mdio_wait_busy(priv);
 139 +}
 140 +
 141 +static int
 142 +ipq8064_mdio_probe(struct platform_device *pdev)
 143 +{
 144 +       struct device_node *np = pdev->dev.of_node;
 145 +       struct ipq8064_mdio *priv;
 146 +       struct mii_bus *bus;
 147 +       int ret;
 148 +
 149 +       bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
 150 +       if (!bus)
 151 +               return -ENOMEM;
 152 +
 153 +       bus->name = "ipq8064_mdio_bus";
 154 +       bus->read = ipq8064_mdio_read;
 155 +       bus->write = ipq8064_mdio_write;
 156 +       snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
 157 +       bus->parent = &pdev->dev;
 158 +
 159 +       priv = bus->priv;
 160 +       priv->base = syscon_node_to_regmap(np);
 161 +       if (IS_ERR_OR_NULL(priv->base)) {
 162 +               priv->base = syscon_regmap_lookup_by_phandle(np, "master");
 163 +               if (IS_ERR_OR_NULL(priv->base)) {
 164 +                       pr_err("master phandle not found\n");
 165 +                       return -EINVAL;
 166 +               }
 167 +       }
 168 +
 169 +       ret = of_mdiobus_register(bus, np);
 170 +       if (ret)
 171 +               return ret;
 172 +
 173 +       platform_set_drvdata(pdev, bus);
 174 +       return 0;
 175 +}
 176 +
 177 +static int
 178 +ipq8064_mdio_remove(struct platform_device *pdev)
 179 +{
 180 +       struct mii_bus *bus = platform_get_drvdata(pdev);
 181 +
 182 +       mdiobus_unregister(bus);
 183 +
 184 +       return 0;
 185 +}
 186 +
 187 +static const struct of_device_id ipq8064_mdio_dt_ids[] = {
 188 +       { .compatible = "qcom,ipq8064-mdio" },
 189 +       { }
 190 +};
 191 +MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids);
 192 +
 193 +static struct platform_driver ipq8064_mdio_driver = {
 194 +       .probe = ipq8064_mdio_probe,
 195 +       .remove = ipq8064_mdio_remove,
 196 +       .driver = {
 197 +               .name = "ipq8064-mdio",
 198 +               .of_match_table = ipq8064_mdio_dt_ids,
 199 +       },
 200 +};
 201 +
 202 +module_platform_driver(ipq8064_mdio_driver);
 203 +
 204 +MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
 205 +MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
 206 +MODULE_LICENSE("GPL");