target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch

   1 From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sun, 15 May 2022 23:00:42 +0200
   4 Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
   5
   6 The built-in PPE engine has a dedicated clock for the EIP-197 crypto
   7 engine.
   8
   9 So, since the required clock currently missing add support for it.
  10
  11 Signed-off-by: Robert Marko <robimarko@gmail.com>
  12 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  13 Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
  14 ---
  15  drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
  16  1 file changed, 19 insertions(+)
  17
  18 --- a/drivers/clk/qcom/gcc-ipq8074.c
  19 +++ b/drivers/clk/qcom/gcc-ipq8074.c
  20 @@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref
  21         },
  22  };
  23
  24 +static struct clk_branch gcc_crypto_ppe_clk = {
  25 +       .halt_reg = 0x68310,
  26 +       .halt_bit = 31,
  27 +       .clkr = {
  28 +               .enable_reg = 0x68310,
  29 +               .enable_mask = BIT(0),
  30 +               .hw.init = &(struct clk_init_data){
  31 +                       .name = "gcc_crypto_ppe_clk",
  32 +                       .parent_names = (const char *[]){
  33 +                               "nss_ppe_clk_src"
  34 +                       },
  35 +                       .num_parents = 1,
  36 +                       .flags = CLK_SET_RATE_PARENT,
  37 +                       .ops = &clk_branch2_ops,
  38 +               },
  39 +       },
  40 +};
  41 +
  42  static struct clk_branch gcc_nssnoc_ce_apb_clk = {
  43         .halt_reg = 0x6830c,
  44         .clkr = {
  45 @@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl
  46         [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
  47         [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
  48         [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
  49 +       [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
  50  };
  51
  52  static const struct qcom_reset_map gcc_ipq8074_resets[] = {