1 From 6f49bc0ee169c90b5c26a1e3d27a4728142f0ddb Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Wed, 16 Nov 2022 22:48:34 +0100
4 Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY
6 IPQ8074 comes in 2 silicon versions:
7 * v1 with 2x Gen2 PCIe ports and QMP PHY-s
8 * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
10 v2 is the final and production version that is actually supported by the
11 kernel, however it looks like PCIe related nodes were added for the v1 SoC.
13 Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support
14 by fixing the Gen3 QMP PHY node first.
16 Change the compatible to the Gen3 QMP PHY, correct the register space start
17 and size, add the missing misc PCS register space.
19 Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
20 Signed-off-by: Robert Marko <robimarko@gmail.com>
22 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++-------
23 1 file changed, 8 insertions(+), 7 deletions(-)
25 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
26 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
31 - pcie_qmp0: phy@86000 {
32 - compatible = "qcom,ipq8074-qmp-pcie-phy";
33 - reg = <0x00086000 0x1c4>;
34 + pcie_qmp0: phy@84000 {
35 + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
36 + reg = <0x00084000 0x1bc>;
44 - pcie_phy0: phy@86200 {
45 - reg = <0x86200 0x16c>,
48 + pcie_phy0: phy@84200 {
49 + reg = <0x84200 0x16c>,
55 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;