lantiq: dts: define the SPI pins in {amazonse,ar9,vr9}.dtsi
[openwrt/openwrt.git] / target / linux / lantiq / files / arch / mips / boot / dts / FRITZ7362SL.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include "FRITZ736X.dtsi"
5
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
8
9 / {
10 compatible = "avm,fritz7362sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9";
11 model = "AVM FRITZ!Box 7362 SL";
12 };
13
14 &power_green {
15 label = "fritz7362sl:green:power";
16 };
17
18 &power_red {
19 label = "fritz7362sl:red:power";
20 };
21
22 &info_green {
23 label = "fritz7362sl:green:info";
24 };
25
26 &wifi {
27 label = "fritz7362sl:green:wlan";
28 };
29
30 &info_red {
31 label = "fritz7362sl:red:info";
32 };
33
34 &dect {
35 label = "fritz7362sl:green:dect";
36 };
37
38 &state_default {
39 nand {
40 lantiq,groups = "nand ale", "nand cle",
41 "nand cs1", "nand rd", "nand rdy";
42 lantiq,function = "ebu";
43 };
44
45 pcie-rst {
46 lantiq,pins = "io21";
47 lantiq,open-drain = <1>;
48 lantiq,output = <1>;
49 };
50 };
51
52 &spi {
53 status = "okay";
54
55 flash@4 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "jedec,spi-nor";
59 reg = <4 0>;
60 spi-max-frequency = <1000000>;
61
62 urlader: partition@0 {
63 reg = <0x0 0x40000>;
64 label = "urlader";
65 read-only;
66 };
67
68 partition@40000 {
69 reg = <0x40000 0x60000>;
70 label = "tffs (1)";
71 read-only;
72 };
73
74 partition@A0000 {
75 reg = <0xA0000 0x60000>;
76 label = "tffs (2)";
77 read-only;
78 };
79 };
80 };
81
82 &localbus {
83 flash@1 {
84 compatible = "lantiq,nand-xway";
85 lantiq,cs1 = <1>;
86 bank-width = <1>;
87 reg = <1 0x0 0x2000000>;
88 nand-ecc-mode = "on-die";
89
90 partitions {
91 compatible = "fixed-partitions";
92 #address-cells = <1>;
93 #size-cells = <1>;
94
95 partition@0 {
96 label = "kernel";
97 reg = <0x0 0x400000>;
98 };
99
100 partition@400000 {
101 label = "ubi";
102 reg = <0x400000 0x7c00000>;
103 };
104 };
105 };
106 };
107
108 &pcie0 {
109 gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
110
111 pcie@0 {
112 #size-cells = <1>;
113 #address-cells = <2>;
114 };
115 };