target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts

   1 #include "vr9_zyxel_p-2812hnu-fx.dtsi"
   2
   3 / {
   4         compatible = "zyxel,p-2812hnu-f3", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9";
   5         model = "ZyXEL P-2812HNU-F3";
   6 };
   7
   8 &state_default {
   9         pcie-rst {
  10                 lantiq,pins = "io38";
  11                 lantiq,pull = <0>;
  12                 lantiq,output = <1>;
  13         };
  14 };
  15
  16 &pci0 {
  17         wifi@e,0 {
  18                 compatible = "pci1814,3092";
  19                 reg = <0x7000 0 0 0 0>;
  20                 ralink,eeprom = "RT3092.eeprom";
  21         };
  22 };
  23
  24 &localbus {
  25         flash@0 {
  26                 compatible = "lantiq,nor";
  27                 bank-width = <2>;
  28                 reg = <0 0x0 0x800000>;
  29
  30                 pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
  31                 pinctrl-names = "default";
  32
  33                 partitions {
  34                         compatible = "fixed-partitions";
  35                         #address-cells = <1>;
  36                         #size-cells = <1>;
  37
  38                         partition@0 {
  39                                 label = "uboot";
  40                                 reg = <0x0 0x50000>;
  41                                 read-only;
  42                         };
  43                         partition@50000 {
  44                                 label = "u-boot-env";
  45                                 reg = <0x50000 0x10000>;
  46                         };
  47                         partition@60000 {
  48                                 label = "unused";
  49                                 reg = <0x60000 0x7a0000>;
  50                         };
  51                 };
  52         };
  53
  54         flash@1 {
  55                 compatible = "lantiq,nand-xway";
  56                 lantiq,cs = <1>;
  57                 bank-width = <2>;
  58                 reg = <1 0x0 0x2000000>;
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 partition@0 {
  63                         label = "kernel";
  64                         reg = <0x0 0x200000>;
  65                 };
  66                 partition@200000 {
  67                         label = "ubi";
  68                         reg = <0x200000 0x7e00000>;
  69                 };
  70         };
  71 };
  72
  73 &pcie0 {
  74         status = "okay";
  75         gpio-reset = <&gpio 38 GPIO_ACTIVE_LOW>;
  76 };