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[openwrt/staging/mkresin.git] / target / linux / lantiq / patches-3.0 / 0014-MIPS-lantiq-adds-xway-spi.patch
1 From e29263339db41d49d79482c93463c4c0cbe764d7 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 30 Sep 2011 14:23:42 +0200
4 Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
5
6 ---
7 .../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 +
8 .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 +
9 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 +
10 drivers/spi/Kconfig | 8 +
11 drivers/spi/Makefile | 2 +-
12 drivers/spi/spi-xway.c | 1062 ++++++++++++++++++++
13 6 files changed, 1083 insertions(+), 1 deletions(-)
14 create mode 100644 drivers/spi/spi-xway.c
15
16 Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
17 ===================================================================
18 --- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/lantiq_platform.h 2011-08-17 19:57:16.000000000 +0200
19 +++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/lantiq_platform.h 2011-10-04 20:05:23.962311503 +0200
20 @@ -50,4 +50,13 @@
21 int mii_mode;
22 };
23
24 +
25 +struct ltq_spi_platform_data {
26 + u16 num_chipselect;
27 +};
28 +
29 +struct ltq_spi_controller_data {
30 + unsigned gpio;
31 +};
32 +
33 #endif
34 Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
35 ===================================================================
36 --- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2011-08-17 19:57:16.000000000 +0200
37 +++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2011-10-04 20:05:23.962311503 +0200
38 @@ -27,6 +27,8 @@
39
40 #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
41 #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
42 +#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14)
43 +#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15)
44 #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
45
46 #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
47 Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
48 ===================================================================
49 --- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2011-10-04 20:03:54.934307699 +0200
50 +++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h 2011-10-04 20:05:23.966311504 +0200
51 @@ -81,6 +81,7 @@
52
53 #define PMU_DMA 0x0020
54 #define PMU_USB 0x8041
55 +#define PMU_SPI 0x0100
56 #define PMU_LED 0x0800
57 #define PMU_GPT 0x1000
58 #define PMU_PPE 0x2000
59 Index: linux-3.0.3/drivers/spi/Kconfig
60 ===================================================================
61 --- linux-3.0.3.orig/drivers/spi/Kconfig 2011-10-04 20:05:07.030310779 +0200
62 +++ linux-3.0.3/drivers/spi/Kconfig 2011-10-04 20:05:23.966311504 +0200
63 @@ -433,6 +433,14 @@
64 help
65 SPI driver for Nuvoton NUC900 series ARM SoCs
66
67 +config SPI_XWAY
68 + tristate "Lantiq XWAY SPI controller"
69 + depends on LANTIQ && SOC_TYPE_XWAY
70 + select SPI_BITBANG
71 + help
72 + This driver supports the Lantiq SoC SPI controller in master
73 + mode.
74 +
75 #
76 # Add new SPI master controllers in alphabetical order above this line
77 #
78 Index: linux-3.0.3/drivers/spi/Makefile
79 ===================================================================
80 --- linux-3.0.3.orig/drivers/spi/Makefile 2011-10-04 20:05:20.000000000 +0200
81 +++ linux-3.0.3/drivers/spi/Makefile 2011-10-04 20:05:35.802312011 +0200
82 @@ -57,6 +57,7 @@
83 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
84 obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
85 obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
86 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o
87
88 # special build for s3c24xx spi driver with fiq support
89 spi_s3c24xx_hw-y := spi_s3c24xx.o
90 Index: linux-3.0.3/drivers/spi/spi-xway.c
91 ===================================================================
92 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
93 +++ linux-3.0.3/drivers/spi/spi-xway.c 2011-10-04 20:05:23.966311504 +0200
94 @@ -0,0 +1,1062 @@
95 +/*
96 + * Lantiq SoC SPI controller
97 + *
98 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
99 + *
100 + * This program is free software; you can distribute it and/or modify it
101 + * under the terms of the GNU General Public License (Version 2) as
102 + * published by the Free Software Foundation.
103 + */
104 +
105 +#include <linux/init.h>
106 +#include <linux/module.h>
107 +#include <linux/workqueue.h>
108 +#include <linux/platform_device.h>
109 +#include <linux/io.h>
110 +#include <linux/sched.h>
111 +#include <linux/delay.h>
112 +#include <linux/interrupt.h>
113 +#include <linux/completion.h>
114 +#include <linux/spinlock.h>
115 +#include <linux/err.h>
116 +#include <linux/clk.h>
117 +#include <linux/gpio.h>
118 +#include <linux/spi/spi.h>
119 +#include <linux/spi/spi_bitbang.h>
120 +
121 +#include <lantiq_soc.h>
122 +#include <lantiq_platform.h>
123 +
124 +#define LTQ_SPI_CLC 0x00 /* Clock control */
125 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
126 +#define LTQ_SPI_ID 0x08 /* Identification */
127 +#define LTQ_SPI_CON 0x10 /* Control */
128 +#define LTQ_SPI_STAT 0x14 /* Status */
129 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
130 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
131 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
132 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
133 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
134 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
135 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
136 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
137 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
138 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
139 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
140 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
141 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
142 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
143 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
144 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
145 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
146 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
147 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
148 +
149 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
150 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
151 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
152 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
153 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
154 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
155 +
156 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
157 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
158 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
159 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
160 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
161 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
162 +
163 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
164 +#define LTQ_SPI_CON_BM_MASK 0x1F
165 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
166 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
167 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
168 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
169 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
170 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
171 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
172 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
173 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
174 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
175 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
176 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
177 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
178 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
179 +
180 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
181 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
182 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
183 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
184 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
185 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
186 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
187 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
188 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
189 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
190 +
191 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
192 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
193 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
194 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
195 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
196 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
197 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
198 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
199 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
200 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
201 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
202 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
203 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
204 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
205 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
206 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
207 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
208 +
209 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
210 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
211 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
212 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
213 +
214 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
215 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
216 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
217 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
218 +
219 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
220 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
221 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
222 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
223 +
224 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
225 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
226 +
227 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
228 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
229 +
230 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
231 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
232 +
233 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
234 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
235 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
236 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
237 +#define LTQ_SPI_IRNEN_ALL 0xF
238 +
239 +/* Hard-wired GPIOs used by SPI controller */
240 +#define LTQ_SPI_GPIO_DI 16
241 +#define LTQ_SPI_GPIO_DO 17
242 +#define LTQ_SPI_GPIO_CLK 18
243 +
244 +struct ltq_spi {
245 + struct spi_bitbang bitbang;
246 + struct completion done;
247 + spinlock_t lock;
248 +
249 + struct device *dev;
250 + void __iomem *base;
251 + struct clk *clk;
252 +
253 + int status;
254 + int irq[3];
255 +
256 + const u8 *tx;
257 + u8 *rx;
258 + u32 tx_cnt;
259 + u32 rx_cnt;
260 + u32 len;
261 + struct spi_transfer *curr_transfer;
262 +
263 + u32 (*get_tx) (struct ltq_spi *);
264 +
265 + u16 txfs;
266 + u16 rxfs;
267 + unsigned dma_support:1;
268 + unsigned cfg_mode:1;
269 +
270 +};
271 +
272 +struct ltq_spi_controller_state {
273 + void (*cs_activate) (struct spi_device *);
274 + void (*cs_deactivate) (struct spi_device *);
275 +};
276 +
277 +struct ltq_spi_irq_map {
278 + char *name;
279 + irq_handler_t handler;
280 +};
281 +
282 +struct ltq_spi_cs_gpio_map {
283 + unsigned gpio;
284 + unsigned altsel0;
285 + unsigned altsel1;
286 +};
287 +
288 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
289 +{
290 + return spi_master_get_devdata(spi->master);
291 +}
292 +
293 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
294 +{
295 + return ioread32be(hw->base + reg);
296 +}
297 +
298 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
299 +{
300 + iowrite32be(val, hw->base + reg);
301 +}
302 +
303 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
304 +{
305 + u32 val;
306 +
307 + val = ltq_spi_reg_read(hw, reg);
308 + val |= bits;
309 + ltq_spi_reg_write(hw, val, reg);
310 +}
311 +
312 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
313 +{
314 + u32 val;
315 +
316 + val = ltq_spi_reg_read(hw, reg);
317 + val &= ~bits;
318 + ltq_spi_reg_write(hw, val, reg);
319 +}
320 +
321 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
322 +{
323 + u32 clc;
324 +
325 + /* Power-up mdule */
326 + ltq_pmu_enable(PMU_SPI);
327 +
328 + /*
329 + * Set clock divider for run mode to 1 to
330 + * run at same frequency as FPI bus
331 + */
332 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
333 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
334 +}
335 +
336 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
337 +{
338 + /* Set clock divider to 0 and set module disable bit */
339 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
340 +
341 + /* Power-down mdule */
342 + ltq_pmu_disable(PMU_SPI);
343 +}
344 +
345 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
346 +{
347 + u32 val;
348 +
349 + /*
350 + * Enable and flush FIFOs. Set interrupt trigger level to
351 + * half of FIFO count implemented in hardware.
352 + */
353 + if (hw->txfs > 1) {
354 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
355 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
356 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
357 + }
358 +
359 + if (hw->rxfs > 1) {
360 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
361 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
362 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
363 + }
364 +}
365 +
366 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
367 +{
368 + u32 stat;
369 + unsigned long timeout;
370 +
371 + timeout = jiffies + msecs_to_jiffies(200);
372 +
373 + do {
374 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
375 + if (!(stat & LTQ_SPI_STAT_BSY))
376 + return 0;
377 +
378 + cond_resched();
379 + } while (!time_after_eq(jiffies, timeout));
380 +
381 + dev_err(hw->dev, "SPI wait ready timed out\n");
382 +
383 + return -ETIMEDOUT;
384 +}
385 +
386 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
387 +{
388 + if (hw->cfg_mode)
389 + return;
390 +
391 + /*
392 + * Putting the SPI module in config mode is only safe if no
393 + * transfer is in progress as indicated by busy flag STATE.BSY.
394 + */
395 + if (ltq_spi_wait_ready(hw)) {
396 + ltq_spi_reset_fifos(hw);
397 + hw->status = -ETIMEDOUT;
398 + }
399 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
400 +
401 + hw->cfg_mode = 1;
402 +}
403 +
404 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
405 +{
406 + if (!hw->cfg_mode)
407 + return;
408 +
409 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
410 +
411 + hw->cfg_mode = 0;
412 +}
413 +
414 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
415 +{
416 + const u8 *tx = hw->tx;
417 + u32 data = *tx++;
418 +
419 + hw->tx_cnt++;
420 + hw->tx++;
421 +
422 + return data;
423 +}
424 +
425 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
426 +{
427 + const u16 *tx = (u16 *) hw->tx;
428 + u32 data = *tx++;
429 +
430 + hw->tx_cnt += 2;
431 + hw->tx += 2;
432 +
433 + return data;
434 +}
435 +
436 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
437 +{
438 + const u32 *tx = (u32 *) hw->tx;
439 + u32 data = *tx++;
440 +
441 + hw->tx_cnt += 4;
442 + hw->tx += 4;
443 +
444 + return data;
445 +}
446 +
447 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
448 +{
449 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
450 + u32 bm;
451 + u8 bits_per_word = spi->bits_per_word;
452 +
453 + /*
454 + * Use either default value of SPI device or value
455 + * from current transfer.
456 + */
457 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
458 + bits_per_word = hw->curr_transfer->bits_per_word;
459 +
460 + if (bits_per_word <= 8)
461 + hw->get_tx = ltq_spi_tx_word_u8;
462 + else if (bits_per_word <= 16)
463 + hw->get_tx = ltq_spi_tx_word_u16;
464 + else if (bits_per_word <= 32)
465 + hw->get_tx = ltq_spi_tx_word_u32;
466 +
467 + /* CON.BM value = bits_per_word - 1 */
468 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
469 +
470 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
471 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
472 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
473 +}
474 +
475 +static void ltq_spi_speed_set(struct spi_device *spi)
476 +{
477 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
478 + u32 br, max_speed_hz, spi_clk;
479 + u32 speed_hz = spi->max_speed_hz;
480 +
481 + /*
482 + * Use either default value of SPI device or value
483 + * from current transfer.
484 + */
485 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
486 + speed_hz = hw->curr_transfer->speed_hz;
487 +
488 + /*
489 + * SPI module clock is derived from FPI bus clock dependent on
490 + * divider value in CLC.RMS which is always set to 1.
491 + */
492 + spi_clk = clk_get_rate(hw->clk);
493 +
494 + /*
495 + * Maximum SPI clock frequency in master mode is half of
496 + * SPI module clock frequency. Maximum reload value of
497 + * baudrate generator BR is 2^16.
498 + */
499 + max_speed_hz = spi_clk / 2;
500 + if (speed_hz >= max_speed_hz)
501 + br = 0;
502 + else
503 + br = (max_speed_hz / speed_hz) - 1;
504 +
505 + if (br > 0xFFFF)
506 + br = 0xFFFF;
507 +
508 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
509 +}
510 +
511 +static void ltq_spi_clockmode_set(struct spi_device *spi)
512 +{
513 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
514 + u32 con;
515 +
516 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
517 +
518 + /*
519 + * SPI mode mapping in CON register:
520 + * Mode CPOL CPHA CON.PO CON.PH
521 + * 0 0 0 0 1
522 + * 1 0 1 0 0
523 + * 2 1 0 1 1
524 + * 3 1 1 1 0
525 + */
526 + if (spi->mode & SPI_CPHA)
527 + con &= ~LTQ_SPI_CON_PH;
528 + else
529 + con |= LTQ_SPI_CON_PH;
530 +
531 + if (spi->mode & SPI_CPOL)
532 + con |= LTQ_SPI_CON_PO;
533 + else
534 + con &= ~LTQ_SPI_CON_PO;
535 +
536 + /* Set heading control */
537 + if (spi->mode & SPI_LSB_FIRST)
538 + con &= ~LTQ_SPI_CON_HB;
539 + else
540 + con |= LTQ_SPI_CON_HB;
541 +
542 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
543 +}
544 +
545 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
546 +{
547 + u32 con;
548 +
549 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
550 +
551 + if (t) {
552 + if (t->tx_buf && t->rx_buf) {
553 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
554 + } else if (t->rx_buf) {
555 + con &= ~LTQ_SPI_CON_RXOFF;
556 + con |= LTQ_SPI_CON_TXOFF;
557 + } else if (t->tx_buf) {
558 + con &= ~LTQ_SPI_CON_TXOFF;
559 + con |= LTQ_SPI_CON_RXOFF;
560 + }
561 + } else
562 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
563 +
564 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
565 +}
566 +
567 +static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
568 +{
569 + struct ltq_spi_controller_data *cdata = spi->controller_data;
570 + int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
571 +
572 + gpio_set_value(cdata->gpio, val);
573 +}
574 +
575 +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
576 +{
577 + struct ltq_spi_controller_data *cdata = spi->controller_data;
578 + int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
579 +
580 + gpio_set_value(cdata->gpio, val);
581 +}
582 +
583 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
584 +{
585 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
586 + u32 fgpo;
587 +
588 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
589 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
590 +}
591 +
592 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
593 +{
594 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
595 + u32 fgpo;
596 +
597 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
598 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
599 +}
600 +
601 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
602 +{
603 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
604 + struct ltq_spi_controller_state *cstate = spi->controller_state;
605 +
606 + switch (cs) {
607 + case BITBANG_CS_ACTIVE:
608 + ltq_spi_bits_per_word_set(spi);
609 + ltq_spi_speed_set(spi);
610 + ltq_spi_clockmode_set(spi);
611 + ltq_spi_run_mode_set(hw);
612 +
613 + cstate->cs_activate(spi);
614 + break;
615 +
616 + case BITBANG_CS_INACTIVE:
617 + cstate->cs_deactivate(spi);
618 +
619 + ltq_spi_config_mode_set(hw);
620 +
621 + break;
622 + }
623 +}
624 +
625 +static int ltq_spi_setup_transfer(struct spi_device *spi,
626 + struct spi_transfer *t)
627 +{
628 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
629 + u8 bits_per_word = spi->bits_per_word;
630 +
631 + hw->curr_transfer = t;
632 +
633 + if (t && t->bits_per_word)
634 + bits_per_word = t->bits_per_word;
635 +
636 + if (bits_per_word > 32)
637 + return -EINVAL;
638 +
639 + ltq_spi_config_mode_set(hw);
640 +
641 + return 0;
642 +}
643 +
644 +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
645 + { 15, 1, 0 },
646 + { 22, 1, 0 },
647 + { 13, 0, 1 },
648 + { 10, 0, 1 },
649 + { 9, 0, 1 },
650 + { 11, 1, 1 },
651 +};
652 +
653 +static int ltq_spi_setup(struct spi_device *spi)
654 +{
655 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
656 + struct ltq_spi_controller_data *cdata = spi->controller_data;
657 + struct ltq_spi_controller_state *cstate;
658 + u32 gpocon, fgpo;
659 + int ret;
660 +
661 + /* Set default word length to 8 if not set */
662 + if (!spi->bits_per_word)
663 + spi->bits_per_word = 8;
664 +
665 + if (spi->bits_per_word > 32)
666 + return -EINVAL;
667 +
668 + if (!spi->controller_state) {
669 + cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
670 + GFP_KERNEL);
671 + if (!cstate)
672 + return -ENOMEM;
673 +
674 + spi->controller_state = cstate;
675 + } else
676 + return 0;
677 +
678 + /*
679 + * Up to six GPIOs can be connected to the SPI module
680 + * via GPIO alternate function to control the chip select lines.
681 + * For more flexibility in board layout this driver can also control
682 + * the CS lines via GPIO API. If GPIOs should be used, board setup code
683 + * have to register the SPI device with struct ltq_spi_controller_data
684 + * attached.
685 + */
686 + if (cdata && cdata->gpio) {
687 + ret = gpio_request(cdata->gpio, "spi-cs");
688 + if (ret)
689 + return -EBUSY;
690 +
691 + ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
692 + gpio_direction_output(cdata->gpio, ret);
693 +
694 + cstate->cs_activate = ltq_spi_gpio_cs_activate;
695 + cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
696 + } else {
697 + ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio,
698 + ltq_spi_cs[spi->chip_select].altsel0,
699 + ltq_spi_cs[spi->chip_select].altsel1,
700 + 1, "spi-cs");
701 + if (ret)
702 + return -EBUSY;
703 +
704 + gpocon = (1 << (spi->chip_select +
705 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
706 +
707 + if (spi->mode & SPI_CS_HIGH)
708 + gpocon |= (1 << spi->chip_select);
709 +
710 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
711 +
712 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
713 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
714 +
715 + cstate->cs_activate = ltq_spi_internal_cs_activate;
716 + cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
717 + }
718 +
719 + return 0;
720 +}
721 +
722 +static void ltq_spi_cleanup(struct spi_device *spi)
723 +{
724 + struct ltq_spi_controller_data *cdata = spi->controller_data;
725 + struct ltq_spi_controller_state *cstate = spi->controller_state;
726 + unsigned gpio;
727 +
728 + if (cdata && cdata->gpio)
729 + gpio = cdata->gpio;
730 + else
731 + gpio = ltq_spi_cs[spi->chip_select].gpio;
732 +
733 + gpio_free(gpio);
734 + kfree(cstate);
735 +}
736 +
737 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
738 +{
739 + u32 fstat, data;
740 + u16 fifo_space;
741 +
742 + /* Determine how much FIFOs are free for TX data */
743 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
744 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
745 + LTQ_SPI_FSTAT_TXFFL_MASK);
746 +
747 + if (!fifo_space)
748 + return;
749 +
750 + while (hw->tx_cnt < hw->len && fifo_space) {
751 + data = hw->get_tx(hw);
752 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
753 + fifo_space--;
754 + }
755 +}
756 +
757 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
758 +{
759 + u32 fstat, data, *rx32;
760 + u16 fifo_fill;
761 + u8 rxbv, shift, *rx8;
762 +
763 + /* Determine how much FIFOs are filled with RX data */
764 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
765 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
766 + & LTQ_SPI_FSTAT_RXFFL_MASK);
767 +
768 + if (!fifo_fill)
769 + return;
770 +
771 + /*
772 + * The 32 bit FIFO is always used completely independent from the
773 + * bits_per_word value. Thus four bytes have to be read at once
774 + * per FIFO.
775 + */
776 + rx32 = (u32 *) hw->rx;
777 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
778 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
779 + hw->rx_cnt += 4;
780 + hw->rx += 4;
781 + fifo_fill--;
782 + }
783 +
784 + /*
785 + * If there are remaining bytes, read byte count from STAT.RXBV
786 + * register and read the data byte-wise.
787 + */
788 + while (fifo_fill && hw->rx_cnt < hw->len) {
789 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
790 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
791 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
792 +
793 + shift = (rxbv - 1) * 8;
794 + rx8 = hw->rx;
795 +
796 + while (rxbv) {
797 + *rx8++ = (data >> shift) & 0xFF;
798 + rxbv--;
799 + shift -= 8;
800 + hw->rx_cnt++;
801 + hw->rx++;
802 + }
803 +
804 + fifo_fill--;
805 + }
806 +}
807 +
808 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
809 +{
810 + u32 rxreq, rxreq_max, rxtodo;
811 +
812 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
813 +
814 + /*
815 + * In RX-only mode the serial clock is activated only after writing
816 + * the expected amount of RX bytes into RXREQ register.
817 + * To avoid receive overflows at high clocks it is better to request
818 + * only the amount of bytes that fits into all FIFOs. This value
819 + * depends on the FIFO size implemented in hardware.
820 + */
821 + rxreq = hw->len - hw->rx_cnt;
822 + rxreq_max = hw->rxfs << 2;
823 + rxreq = min(rxreq_max, rxreq);
824 +
825 + if (!rxtodo && rxreq)
826 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
827 +}
828 +
829 +static inline void ltq_spi_complete(struct ltq_spi *hw)
830 +{
831 + complete(&hw->done);
832 +}
833 +
834 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
835 +{
836 + struct ltq_spi *hw = data;
837 + unsigned long flags;
838 + int completed = 0;
839 +
840 + spin_lock_irqsave(&hw->lock, flags);
841 +
842 + if (hw->tx_cnt < hw->len)
843 + ltq_spi_txfifo_write(hw);
844 +
845 + if (hw->tx_cnt == hw->len)
846 + completed = 1;
847 +
848 + spin_unlock_irqrestore(&hw->lock, flags);
849 +
850 + if (completed)
851 + ltq_spi_complete(hw);
852 +
853 + return IRQ_HANDLED;
854 +}
855 +
856 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
857 +{
858 + struct ltq_spi *hw = data;
859 + unsigned long flags;
860 + int completed = 0;
861 +
862 + spin_lock_irqsave(&hw->lock, flags);
863 +
864 + if (hw->rx_cnt < hw->len) {
865 + ltq_spi_rxfifo_read(hw);
866 +
867 + if (hw->tx && hw->tx_cnt < hw->len)
868 + ltq_spi_txfifo_write(hw);
869 + }
870 +
871 + if (hw->rx_cnt == hw->len)
872 + completed = 1;
873 + else if (!hw->tx)
874 + ltq_spi_rxreq_set(hw);
875 +
876 + spin_unlock_irqrestore(&hw->lock, flags);
877 +
878 + if (completed)
879 + ltq_spi_complete(hw);
880 +
881 + return IRQ_HANDLED;
882 +}
883 +
884 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
885 +{
886 + struct ltq_spi *hw = data;
887 + unsigned long flags;
888 +
889 + spin_lock_irqsave(&hw->lock, flags);
890 +
891 + /* Disable all interrupts */
892 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
893 +
894 + /* Clear all error flags */
895 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
896 +
897 + /* Flush FIFOs */
898 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
899 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
900 +
901 + hw->status = -EIO;
902 + spin_unlock_irqrestore(&hw->lock, flags);
903 +
904 + ltq_spi_complete(hw);
905 +
906 + return IRQ_HANDLED;
907 +}
908 +
909 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
910 +{
911 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
912 + u32 irq_flags = 0;
913 +
914 + hw->tx = t->tx_buf;
915 + hw->rx = t->rx_buf;
916 + hw->len = t->len;
917 + hw->tx_cnt = 0;
918 + hw->rx_cnt = 0;
919 + hw->status = 0;
920 + INIT_COMPLETION(hw->done);
921 +
922 + ltq_spi_xmit_set(hw, t);
923 +
924 + /* Enable error interrupts */
925 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
926 +
927 + if (hw->tx) {
928 + /* Initially fill TX FIFO with as much data as possible */
929 + ltq_spi_txfifo_write(hw);
930 + irq_flags |= LTQ_SPI_IRNEN_T;
931 +
932 + /* Always enable RX interrupt in Full Duplex mode */
933 + if (hw->rx)
934 + irq_flags |= LTQ_SPI_IRNEN_R;
935 + } else if (hw->rx) {
936 + /* Start RX clock */
937 + ltq_spi_rxreq_set(hw);
938 +
939 + /* Enable RX interrupt to receive data from RX FIFOs */
940 + irq_flags |= LTQ_SPI_IRNEN_R;
941 + }
942 +
943 + /* Enable TX or RX interrupts */
944 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
945 + wait_for_completion_interruptible(&hw->done);
946 +
947 + /* Disable all interrupts */
948 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
949 +
950 + /*
951 + * Return length of current transfer for bitbang utility code if
952 + * no errors occured during transmission.
953 + */
954 + if (!hw->status)
955 + hw->status = hw->len;
956 +
957 + return hw->status;
958 +}
959 +
960 +static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
961 + { "spi_tx", ltq_spi_tx_irq },
962 + { "spi_rx", ltq_spi_rx_irq },
963 + { "spi_err", ltq_spi_err_irq },
964 +};
965 +
966 +static int __init ltq_spi_probe(struct platform_device *pdev)
967 +{
968 + struct spi_master *master;
969 + struct resource *r;
970 + struct ltq_spi *hw;
971 + struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
972 + int ret, i;
973 + u32 data, id;
974 +
975 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
976 + if (!master) {
977 + dev_err(&pdev->dev, "spi_alloc_master\n");
978 + ret = -ENOMEM;
979 + goto err;
980 + }
981 +
982 + hw = spi_master_get_devdata(master);
983 +
984 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
985 + if (r == NULL) {
986 + dev_err(&pdev->dev, "platform_get_resource\n");
987 + ret = -ENOENT;
988 + goto err_master;
989 + }
990 +
991 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
992 + pdev->name);
993 + if (!r) {
994 + dev_err(&pdev->dev, "devm_request_mem_region\n");
995 + ret = -ENXIO;
996 + goto err_master;
997 + }
998 +
999 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
1000 + if (!hw->base) {
1001 + dev_err(&pdev->dev, "devm_ioremap_nocache\n");
1002 + ret = -ENXIO;
1003 + goto err_master;
1004 + }
1005 +
1006 + hw->clk = clk_get(&pdev->dev, "fpi");
1007 + if (IS_ERR(hw->clk)) {
1008 + dev_err(&pdev->dev, "clk_get\n");
1009 + ret = PTR_ERR(hw->clk);
1010 + goto err_master;
1011 + }
1012 +
1013 + memset(hw->irq, 0, sizeof(hw->irq));
1014 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
1015 + ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
1016 + if (0 > ret) {
1017 + dev_err(&pdev->dev, "platform_get_irq_byname\n");
1018 + goto err_irq;
1019 + }
1020 +
1021 + hw->irq[i] = ret;
1022 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
1023 + 0, ltq_spi_irqs[i].name, hw);
1024 + if (ret) {
1025 + dev_err(&pdev->dev, "request_irq\n");
1026 + goto err_irq;
1027 + }
1028 + }
1029 +
1030 + hw->bitbang.master = spi_master_get(master);
1031 + hw->bitbang.chipselect = ltq_spi_chipselect;
1032 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
1033 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
1034 +
1035 + master->bus_num = pdev->id;
1036 + master->num_chipselect = pdata->num_chipselect;
1037 + master->setup = ltq_spi_setup;
1038 + master->cleanup = ltq_spi_cleanup;
1039 +
1040 + hw->dev = &pdev->dev;
1041 + init_completion(&hw->done);
1042 + spin_lock_init(&hw->lock);
1043 +
1044 + /* Set GPIO alternate functions to SPI */
1045 + ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
1046 + ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
1047 + ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
1048 +
1049 + ltq_spi_hw_enable(hw);
1050 +
1051 + /* Read module capabilities */
1052 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
1053 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1054 + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1055 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
1056 +
1057 + ltq_spi_config_mode_set(hw);
1058 +
1059 + /* Enable error checking, disable TX/RX, set idle value high */
1060 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
1061 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
1062 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
1063 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
1064 +
1065 + /* Enable master mode and clear error flags */
1066 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
1067 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
1068 +
1069 + /* Reset GPIO/CS registers */
1070 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
1071 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
1072 +
1073 + /* Enable and flush FIFOs */
1074 + ltq_spi_reset_fifos(hw);
1075 +
1076 + ret = spi_bitbang_start(&hw->bitbang);
1077 + if (ret) {
1078 + dev_err(&pdev->dev, "spi_bitbang_start\n");
1079 + goto err_bitbang;
1080 + }
1081 +
1082 + platform_set_drvdata(pdev, hw);
1083 +
1084 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1085 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1086 +
1087 + return 0;
1088 +
1089 +err_bitbang:
1090 + ltq_spi_hw_disable(hw);
1091 +
1092 +err_irq:
1093 + clk_put(hw->clk);
1094 +
1095 + for (; i > 0; i--)
1096 + free_irq(hw->irq[i], hw);
1097 +
1098 +err_master:
1099 + spi_master_put(master);
1100 +
1101 +err:
1102 + return ret;
1103 +}
1104 +
1105 +static int __exit ltq_spi_remove(struct platform_device *pdev)
1106 +{
1107 + struct ltq_spi *hw = platform_get_drvdata(pdev);
1108 + int ret, i;
1109 +
1110 + ret = spi_bitbang_stop(&hw->bitbang);
1111 + if (ret)
1112 + return ret;
1113 +
1114 + platform_set_drvdata(pdev, NULL);
1115 +
1116 + ltq_spi_config_mode_set(hw);
1117 + ltq_spi_hw_disable(hw);
1118 +
1119 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1120 + if (0 < hw->irq[i])
1121 + free_irq(hw->irq[i], hw);
1122 +
1123 + gpio_free(LTQ_SPI_GPIO_DI);
1124 + gpio_free(LTQ_SPI_GPIO_DO);
1125 + gpio_free(LTQ_SPI_GPIO_CLK);
1126 +
1127 + clk_put(hw->clk);
1128 + spi_master_put(hw->bitbang.master);
1129 +
1130 + return 0;
1131 +}
1132 +
1133 +static struct platform_driver ltq_spi_driver = {
1134 + .driver = {
1135 + .name = "ltq-spi",
1136 + .owner = THIS_MODULE,
1137 + },
1138 + .remove = __exit_p(ltq_spi_remove),
1139 +};
1140 +
1141 +static int __init ltq_spi_init(void)
1142 +{
1143 + return platform_driver_probe(&ltq_spi_driver, ltq_spi_probe);
1144 +}
1145 +module_init(ltq_spi_init);
1146 +
1147 +static void __exit ltq_spi_exit(void)
1148 +{
1149 + platform_driver_unregister(&ltq_spi_driver);
1150 +}
1151 +module_exit(ltq_spi_exit);
1152 +
1153 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1154 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1155 +MODULE_LICENSE("GPL");
1156 +MODULE_ALIAS("platform:ltq-spi");
Staging tree of Mathias Kresin