1 From e75df4f96373e5d16f8ca13aa031e54cdcfeda62 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 13 Mar 2013 09:29:37 +0100
4 Subject: [PATCH 33/36] SPI: MIPS: lantiq: adds spi-xway
6 This patch adds support for the SPI core found on several Lantiq SoCs.
7 The Driver has been runtime tested in combination with m25p80 Flash Devices
10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
11 Signed-off-by: John Crispin <blogic@openwrt.org>
13 drivers/spi/Kconfig | 8 +
14 drivers/spi/Makefile | 1 +
15 drivers/spi/spi-xway.c | 977 ++++++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 986 insertions(+)
17 create mode 100644 drivers/spi/spi-xway.c
19 --- a/drivers/spi/Kconfig
20 +++ b/drivers/spi/Kconfig
21 @@ -597,6 +597,14 @@ config SPI_NUC900
23 SPI driver for Nuvoton NUC900 series ARM SoCs
26 + tristate "Lantiq XWAY SPI controller"
27 + depends on LANTIQ && SOC_TYPE_XWAY
30 + This driver supports the Lantiq SoC SPI controller in master
34 # Add new SPI master controllers in alphabetical order above this line
36 --- a/drivers/spi/Makefile
37 +++ b/drivers/spi/Makefile
38 @@ -86,3 +86,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
39 obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
40 obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
41 obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
42 +obj-$(CONFIG_SPI_XWAY) += spi-xway.o
44 +++ b/drivers/spi/spi-xway.c
47 + * Lantiq SoC SPI controller
49 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
50 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
52 + * This program is free software; you can distribute it and/or modify it
53 + * under the terms of the GNU General Public License (Version 2) as
54 + * published by the Free Software Foundation.
57 +#include <linux/init.h>
58 +#include <linux/module.h>
59 +#include <linux/workqueue.h>
60 +#include <linux/platform_device.h>
61 +#include <linux/io.h>
62 +#include <linux/sched.h>
63 +#include <linux/delay.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/completion.h>
66 +#include <linux/spinlock.h>
67 +#include <linux/err.h>
68 +#include <linux/clk.h>
69 +#include <linux/spi/spi.h>
70 +#include <linux/spi/spi_bitbang.h>
71 +#include <linux/of_irq.h>
73 +#include <lantiq_soc.h>
75 +#define LTQ_SPI_CLC 0x00 /* Clock control */
76 +#define LTQ_SPI_PISEL 0x04 /* Port input select */
77 +#define LTQ_SPI_ID 0x08 /* Identification */
78 +#define LTQ_SPI_CON 0x10 /* Control */
79 +#define LTQ_SPI_STAT 0x14 /* Status */
80 +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */
81 +#define LTQ_SPI_TB 0x20 /* Transmit buffer */
82 +#define LTQ_SPI_RB 0x24 /* Receive buffer */
83 +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */
84 +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */
85 +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */
86 +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */
87 +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */
88 +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */
89 +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */
90 +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */
91 +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */
92 +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */
93 +#define LTQ_SPI_RXREQ 0x80 /* Receive request */
94 +#define LTQ_SPI_RXCNT 0x84 /* Receive count */
95 +#define LTQ_SPI_DMACON 0xEC /* DMA control */
96 +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */
97 +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */
98 +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */
100 +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */
101 +#define LTQ_SPI_CLC_SMC_MASK 0xFF
102 +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */
103 +#define LTQ_SPI_CLC_RMC_MASK 0xFF
104 +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
105 +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
107 +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */
108 +#define LTQ_SPI_ID_TXFS_MASK 0x3F
109 +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */
110 +#define LTQ_SPI_ID_RXFS_MASK 0x3F
111 +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */
112 +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */
114 +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */
115 +#define LTQ_SPI_CON_BM_MASK 0x1F
116 +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
117 +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
118 +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
119 +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
120 +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
121 +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
122 +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
123 +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
124 +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
125 +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
126 +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
127 +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
128 +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
129 +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
131 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
132 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
133 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
134 +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
135 +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
136 +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
137 +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
138 +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
139 +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
140 +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
142 +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
143 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
144 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
145 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
146 +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error
148 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
149 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
150 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
151 +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
152 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
153 +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
154 +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
155 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
156 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
157 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
158 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
159 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
161 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */
162 +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F
163 +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
164 +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
166 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */
167 +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F
168 +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
169 +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
171 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
172 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0
173 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f
174 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
176 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8
177 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0
179 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8
180 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0
182 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */
183 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */
185 +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
186 +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
187 +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */
188 +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */
189 +#define LTQ_SPI_IRNEN_ALL 0xF
192 + struct spi_bitbang bitbang;
193 + struct completion done;
196 + struct device *dev;
197 + void __iomem *base;
198 + struct clk *fpiclk;
199 + struct clk *spiclk;
209 + struct spi_transfer *curr_transfer;
211 + u32 (*get_tx) (struct ltq_spi *);
215 + unsigned dma_support:1;
216 + unsigned cfg_mode:1;
219 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
221 + return spi_master_get_devdata(spi->master);
224 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
226 + return ioread32be(hw->base + reg);
229 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
231 + iowrite32be(val, hw->base + reg);
234 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
238 + val = ltq_spi_reg_read(hw, reg);
240 + ltq_spi_reg_write(hw, val, reg);
243 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
247 + val = ltq_spi_reg_read(hw, reg);
249 + ltq_spi_reg_write(hw, val, reg);
252 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
256 + /* Power-up module */
257 + clk_enable(hw->spiclk);
260 + * Set clock divider for run mode to 1 to
261 + * run at same frequency as FPI bus
263 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
264 + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
267 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
269 + /* Set clock divider to 0 and set module disable bit */
270 + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
272 + /* Power-down module */
273 + clk_disable(hw->spiclk);
276 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
281 + * Enable and flush FIFOs. Set interrupt trigger level to
282 + * half of FIFO count implemented in hardware.
284 + if (hw->txfs > 1) {
285 + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
286 + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
287 + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
290 + if (hw->rxfs > 1) {
291 + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
292 + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
293 + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
297 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
300 + unsigned long timeout;
302 + timeout = jiffies + msecs_to_jiffies(200);
305 + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
306 + if (!(stat & LTQ_SPI_STAT_BSY))
310 + } while (!time_after_eq(jiffies, timeout));
312 + dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
317 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
323 + * Putting the SPI module in config mode is only safe if no
324 + * transfer is in progress as indicated by busy flag STATE.BSY.
326 + if (ltq_spi_wait_ready(hw)) {
327 + ltq_spi_reset_fifos(hw);
328 + hw->status = -ETIMEDOUT;
330 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
335 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
340 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
345 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
347 + const u8 *tx = hw->tx;
356 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
358 + const u16 *tx = (u16 *) hw->tx;
367 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
369 + const u32 *tx = (u32 *) hw->tx;
378 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
380 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
382 + u8 bits_per_word = spi->bits_per_word;
385 + * Use either default value of SPI device or value
386 + * from current transfer.
388 + if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
389 + bits_per_word = hw->curr_transfer->bits_per_word;
391 + if (bits_per_word <= 8)
392 + hw->get_tx = ltq_spi_tx_word_u8;
393 + else if (bits_per_word <= 16)
394 + hw->get_tx = ltq_spi_tx_word_u16;
395 + else if (bits_per_word <= 32)
396 + hw->get_tx = ltq_spi_tx_word_u32;
398 + /* CON.BM value = bits_per_word - 1 */
399 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
401 + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
402 + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
403 + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
406 +static void ltq_spi_speed_set(struct spi_device *spi)
408 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
409 + u32 br, max_speed_hz, spi_clk;
410 + u32 speed_hz = spi->max_speed_hz;
413 + * Use either default value of SPI device or value
414 + * from current transfer.
416 + if (hw->curr_transfer && hw->curr_transfer->speed_hz)
417 + speed_hz = hw->curr_transfer->speed_hz;
420 + * SPI module clock is derived from FPI bus clock dependent on
421 + * divider value in CLC.RMS which is always set to 1.
423 + spi_clk = clk_get_rate(hw->fpiclk);
426 + * Maximum SPI clock frequency in master mode is half of
427 + * SPI module clock frequency. Maximum reload value of
428 + * baudrate generator BR is 2^16.
430 + max_speed_hz = spi_clk / 2;
431 + if (speed_hz >= max_speed_hz)
434 + br = (max_speed_hz / speed_hz) - 1;
439 + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
442 +static void ltq_spi_clockmode_set(struct spi_device *spi)
444 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
447 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
450 + * SPI mode mapping in CON register:
451 + * Mode CPOL CPHA CON.PO CON.PH
457 + if (spi->mode & SPI_CPHA)
458 + con &= ~LTQ_SPI_CON_PH;
460 + con |= LTQ_SPI_CON_PH;
462 + if (spi->mode & SPI_CPOL)
463 + con |= LTQ_SPI_CON_PO;
465 + con &= ~LTQ_SPI_CON_PO;
467 + /* Set heading control */
468 + if (spi->mode & SPI_LSB_FIRST)
469 + con &= ~LTQ_SPI_CON_HB;
471 + con |= LTQ_SPI_CON_HB;
473 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
476 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
480 + con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
483 + if (t->tx_buf && t->rx_buf) {
484 + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
485 + } else if (t->rx_buf) {
486 + con &= ~LTQ_SPI_CON_RXOFF;
487 + con |= LTQ_SPI_CON_TXOFF;
488 + } else if (t->tx_buf) {
489 + con &= ~LTQ_SPI_CON_TXOFF;
490 + con |= LTQ_SPI_CON_RXOFF;
493 + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
495 + ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
498 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
500 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
503 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
504 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
507 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
509 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
512 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
513 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
516 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
518 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
521 + case BITBANG_CS_ACTIVE:
522 + ltq_spi_bits_per_word_set(spi);
523 + ltq_spi_speed_set(spi);
524 + ltq_spi_clockmode_set(spi);
525 + ltq_spi_run_mode_set(hw);
526 + ltq_spi_internal_cs_activate(spi);
529 + case BITBANG_CS_INACTIVE:
530 + ltq_spi_internal_cs_deactivate(spi);
531 + ltq_spi_config_mode_set(hw);
536 +static int ltq_spi_setup_transfer(struct spi_device *spi,
537 + struct spi_transfer *t)
539 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
540 + u8 bits_per_word = spi->bits_per_word;
542 + hw->curr_transfer = t;
544 + if (t && t->bits_per_word)
545 + bits_per_word = t->bits_per_word;
547 + if (bits_per_word > 32)
550 + ltq_spi_config_mode_set(hw);
555 +static int ltq_spi_setup(struct spi_device *spi)
557 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
560 + /* Set default word length to 8 if not set */
561 + if (!spi->bits_per_word)
562 + spi->bits_per_word = 8;
564 + if (spi->bits_per_word > 32)
568 + * Up to six GPIOs can be connected to the SPI module
569 + * via GPIO alternate function to control the chip select lines.
571 + gpocon = (1 << (spi->chip_select +
572 + LTQ_SPI_GPOCON_ISCSBN_SHIFT));
574 + if (spi->mode & SPI_CS_HIGH)
575 + gpocon |= (1 << spi->chip_select);
577 + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
579 + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
580 + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
585 +static void ltq_spi_cleanup(struct spi_device *spi)
590 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
595 + /* Determine how much FIFOs are free for TX data */
596 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
597 + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
598 + LTQ_SPI_FSTAT_TXFFL_MASK);
603 + while (hw->tx_cnt < hw->len && fifo_space) {
604 + data = hw->get_tx(hw);
605 + ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
610 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
612 + u32 fstat, data, *rx32;
614 + u8 rxbv, shift, *rx8;
616 + /* Determine how much FIFOs are filled with RX data */
617 + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
618 + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
619 + & LTQ_SPI_FSTAT_RXFFL_MASK);
625 + * The 32 bit FIFO is always used completely independent from the
626 + * bits_per_word value. Thus four bytes have to be read at once
629 + rx32 = (u32 *) hw->rx;
630 + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
631 + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
638 + * If there are remaining bytes, read byte count from STAT.RXBV
639 + * register and read the data byte-wise.
641 + while (fifo_fill && hw->rx_cnt < hw->len) {
642 + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
643 + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
644 + data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
646 + shift = (rxbv - 1) * 8;
650 + *rx8++ = (data >> shift) & 0xFF;
661 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
663 + u32 rxreq, rxreq_max, rxtodo;
665 + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
668 + * In RX-only mode the serial clock is activated only after writing
669 + * the expected amount of RX bytes into RXREQ register.
670 + * To avoid receive overflows at high clocks it is better to request
671 + * only the amount of bytes that fits into all FIFOs. This value
672 + * depends on the FIFO size implemented in hardware.
674 + rxreq = hw->len - hw->rx_cnt;
675 + rxreq_max = hw->rxfs << 2;
676 + rxreq = min(rxreq_max, rxreq);
678 + if (!rxtodo && rxreq)
679 + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
682 +static inline void ltq_spi_complete(struct ltq_spi *hw)
684 + complete(&hw->done);
687 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
689 + struct ltq_spi *hw = data;
690 + unsigned long flags;
693 + spin_lock_irqsave(&hw->lock, flags);
695 + if (hw->tx_cnt < hw->len)
696 + ltq_spi_txfifo_write(hw);
698 + if (hw->tx_cnt == hw->len)
701 + spin_unlock_irqrestore(&hw->lock, flags);
704 + ltq_spi_complete(hw);
706 + return IRQ_HANDLED;
709 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
711 + struct ltq_spi *hw = data;
712 + unsigned long flags;
715 + spin_lock_irqsave(&hw->lock, flags);
717 + if (hw->rx_cnt < hw->len) {
718 + ltq_spi_rxfifo_read(hw);
720 + if (hw->tx && hw->tx_cnt < hw->len)
721 + ltq_spi_txfifo_write(hw);
724 + if (hw->rx_cnt == hw->len)
727 + ltq_spi_rxreq_set(hw);
729 + spin_unlock_irqrestore(&hw->lock, flags);
732 + ltq_spi_complete(hw);
734 + return IRQ_HANDLED;
737 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
739 + struct ltq_spi *hw = data;
740 + unsigned long flags;
742 + spin_lock_irqsave(&hw->lock, flags);
744 + /* Disable all interrupts */
745 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
747 + /* Clear all error flags */
748 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
751 + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
752 + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
755 + spin_unlock_irqrestore(&hw->lock, flags);
757 + ltq_spi_complete(hw);
759 + return IRQ_HANDLED;
762 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
764 + struct ltq_spi *hw = ltq_spi_to_hw(spi);
767 + hw->tx = t->tx_buf;
768 + hw->rx = t->rx_buf;
773 + init_completion(&hw->done);
775 + ltq_spi_xmit_set(hw, t);
777 + /* Enable error interrupts */
778 + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
781 + /* Initially fill TX FIFO with as much data as possible */
782 + ltq_spi_txfifo_write(hw);
783 + irq_flags |= LTQ_SPI_IRNEN_T;
785 + /* Always enable RX interrupt in Full Duplex mode */
787 + irq_flags |= LTQ_SPI_IRNEN_R;
788 + } else if (hw->rx) {
789 + /* Start RX clock */
790 + ltq_spi_rxreq_set(hw);
792 + /* Enable RX interrupt to receive data from RX FIFOs */
793 + irq_flags |= LTQ_SPI_IRNEN_R;
796 + /* Enable TX or RX interrupts */
797 + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
798 + wait_for_completion_interruptible(&hw->done);
800 + /* Disable all interrupts */
801 + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
804 + * Return length of current transfer for bitbang utility code if
805 + * no errors occured during transmission.
808 + hw->status = hw->len;
813 +static const struct ltq_spi_irq_map {
815 + irq_handler_t handler;
816 +} ltq_spi_irqs[] = {
817 + { "spi_rx", ltq_spi_rx_irq },
818 + { "spi_tx", ltq_spi_tx_irq },
819 + { "spi_err", ltq_spi_err_irq },
822 +static int ltq_spi_probe(struct platform_device *pdev)
824 + struct resource irqres[3];
825 + struct spi_master *master;
826 + struct resource *r;
827 + struct ltq_spi *hw;
831 + if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) {
832 + dev_err(&pdev->dev, "IRQ settings missing in device tree\n");
836 + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
838 + dev_err(&pdev->dev, "spi_alloc_master\n");
843 + hw = spi_master_get_devdata(master);
845 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 + dev_err(&pdev->dev, "platform_get_resource\n");
852 + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
855 + dev_err(&pdev->dev, "failed to request memory region\n");
860 + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
862 + dev_err(&pdev->dev, "failed to remap memory region\n");
867 + memset(hw->irq, 0, sizeof(hw->irq));
868 + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
869 + hw->irq[i] = irqres[i].start;
870 + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
871 + 0, ltq_spi_irqs[i].name, hw);
873 + dev_err(&pdev->dev, "failed to request %s irq (%d)\n",
874 + ltq_spi_irqs[i].name, hw->irq[i]);
879 + hw->fpiclk = clk_get_fpi();
880 + if (IS_ERR(hw->fpiclk)) {
881 + dev_err(&pdev->dev, "failed to get fpi clock\n");
882 + ret = PTR_ERR(hw->fpiclk);
886 + hw->spiclk = clk_get(&pdev->dev, NULL);
887 + if (IS_ERR(hw->spiclk)) {
888 + dev_err(&pdev->dev, "failed to get spi clock gate\n");
889 + ret = PTR_ERR(hw->spiclk);
893 + hw->bitbang.master = spi_master_get(master);
894 + hw->bitbang.chipselect = ltq_spi_chipselect;
895 + hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
896 + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
898 + if (of_machine_is_compatible("lantiq,ase"))
899 + master->num_chipselect = 3;
901 + master->num_chipselect = 6;
902 + master->bus_num = pdev->id;
903 + master->setup = ltq_spi_setup;
904 + master->cleanup = ltq_spi_cleanup;
905 + master->dev.of_node = pdev->dev.of_node;
907 + hw->dev = &pdev->dev;
908 + init_completion(&hw->done);
909 + spin_lock_init(&hw->lock);
911 + ltq_spi_hw_enable(hw);
913 + /* Read module capabilities */
914 + id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
915 + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
916 + hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK;
917 + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
919 + ltq_spi_config_mode_set(hw);
921 + /* Enable error checking, disable TX/RX, set idle value high */
922 + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
923 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
924 + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
925 + ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
927 + /* Enable master mode and clear error flags */
928 + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
929 + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
931 + /* Reset GPIO/CS registers */
932 + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
933 + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
935 + /* Enable and flush FIFOs */
936 + ltq_spi_reset_fifos(hw);
938 + ret = spi_bitbang_start(&hw->bitbang);
940 + dev_err(&pdev->dev, "spi_bitbang_start failed\n");
944 + platform_set_drvdata(pdev, hw);
946 + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
947 + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
952 + ltq_spi_hw_disable(hw);
956 + clk_put(hw->fpiclk);
958 + clk_put(hw->spiclk);
961 + clk_put(hw->fpiclk);
964 + free_irq(hw->irq[i], hw);
967 + spi_master_put(master);
973 +static int ltq_spi_remove(struct platform_device *pdev)
975 + struct ltq_spi *hw = platform_get_drvdata(pdev);
978 + spi_bitbang_stop(&hw->bitbang);
980 + platform_set_drvdata(pdev, NULL);
982 + ltq_spi_config_mode_set(hw);
983 + ltq_spi_hw_disable(hw);
985 + for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
986 + if (0 < hw->irq[i])
987 + free_irq(hw->irq[i], hw);
990 + clk_put(hw->fpiclk);
992 + clk_put(hw->spiclk);
994 + spi_master_put(hw->bitbang.master);
999 +static const struct of_device_id ltq_spi_match[] = {
1000 + { .compatible = "lantiq,spi-xway" },
1003 +MODULE_DEVICE_TABLE(of, ltq_spi_match);
1005 +static struct platform_driver ltq_spi_driver = {
1006 + .probe = ltq_spi_probe,
1007 + .remove = ltq_spi_remove,
1009 + .name = "spi-xway",
1010 + .owner = THIS_MODULE,
1011 + .of_match_table = ltq_spi_match,
1015 +module_platform_driver(ltq_spi_driver);
1017 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1018 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1019 +MODULE_LICENSE("GPL");
1020 +MODULE_ALIAS("platform:spi-xway");