target/linux/lantiq/patches-3.3/0005-pci-support.patch

   1 From b80a5236053be899421417871d1be8016912e94b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 3 Aug 2012 09:52:10 +0200
   4 Subject: [PATCH 05/25] pci support
   5
   6 ---
   7  arch/mips/include/asm/mach-lantiq/lantiq.h         |   37 ++++-----
   8  .../mips/include/asm/mach-lantiq/lantiq_platform.h |    9 ++
   9  arch/mips/pci/Makefile                             |    5 +-
  10  arch/mips/pci/ops-lantiq.c                         |    6 +-
  11  arch/mips/pci/pci-lantiq.c                         |   82 ++++++++------------
  12  arch/mips/pci/pci-lantiq.h                         |    2 +-
  13  arch/mips/pci/pci.c                                |   25 ++++++
  14  7 files changed, 89 insertions(+), 77 deletions(-)
  15
  16 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
  17 index ce2f029..622847f 100644
  18 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  19 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  20 @@ -9,6 +9,8 @@
  21  #define _LANTIQ_H__
  22
  23  #include <linux/irq.h>
  24 +#include <linux/clk.h>
  25 +#include <linux/ioport.h>
  26
  27  /* generic reg access functions */
  28  #define ltq_r32(reg)           __raw_readl(reg)
  29 @@ -18,40 +20,33 @@
  30  #define ltq_r8(reg)            __raw_readb(reg)
  31  #define ltq_w8(val, reg)       __raw_writeb(val, reg)
  32
  33 -/* register access macros for EBU and CGU */
  34 -#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
  35 -#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
  36 -#define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
  37 -#define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
  38 -
  39 -extern __iomem void *ltq_ebu_membase;
  40 -extern __iomem void *ltq_cgu_membase;
  41 -
  42  extern unsigned int ltq_get_cpu_ver(void);
  43  extern unsigned int ltq_get_soc_type(void);
  44
  45 -/* clock speeds */
  46 -#define CLOCK_60M      60000000
  47 -#define CLOCK_83M      83333333
  48 -#define CLOCK_111M     111111111
  49 -#define CLOCK_133M     133333333
  50 -#define CLOCK_167M     166666667
  51 -#define CLOCK_200M     200000000
  52 -#define CLOCK_266M     266666666
  53 -#define CLOCK_333M     333333333
  54 -#define CLOCK_400M     400000000
  55 -
  56  /* spinlock all ebu i/o */
  57  extern spinlock_t ebu_lock;
  58
  59 +/* request a non-gpio and set the PIO config */
  60 +extern int ltq_gpio_request(struct device *dev, unsigned int pin,
  61 +               unsigned int mux, unsigned int dir, const char *name);
  62 +
  63  /* some irq helpers */
  64  extern void ltq_disable_irq(struct irq_data *data);
  65  extern void ltq_mask_and_ack_irq(struct irq_data *data);
  66  extern void ltq_enable_irq(struct irq_data *data);
  67
  68 +/* clock handling */
  69 +extern int clk_activate(struct clk *clk);
  70 +extern void clk_deactivate(struct clk *clk);
  71 +extern struct clk *clk_get_cpu(void);
  72 +extern struct clk *clk_get_fpi(void);
  73 +extern struct clk *clk_get_io(void);
  74 +
  75  /* find out what caused the last cpu reset */
  76  extern int ltq_reset_cause(void);
  77 -#define LTQ_RST_CAUSE_WDTRST   0x20
  78 +
  79 +/* helper for requesting and remapping resources */
  80 +extern void __iomem *ltq_remap_resource(struct resource *res);
  81
  82  #define IOPORT_RESOURCE_START  0x10000000
  83  #define IOPORT_RESOURCE_END    0xffffffff
  84 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  85 index a305f1d..38ed938 100644
  86 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  87 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  88 @@ -50,4 +50,13 @@ struct ltq_eth_data {
  89         int mii_mode;
  90  };
  91
  92 +
  93 +struct ltq_spi_platform_data {
  94 +       u16 num_chipselect;
  95 +};
  96 +
  97 +struct ltq_spi_controller_data {
  98 +       unsigned gpio;
  99 +};
 100 +
 101  #endif
 102 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
 103 index c3ac4b0..31e70c5 100644
 104 --- a/arch/mips/pci/Makefile
 105 +++ b/arch/mips/pci/Makefile
 106 @@ -41,7 +41,10 @@ obj-$(CONFIG_SIBYTE_SB1250)  += fixup-sb1250.o pci-sb1250.o
 107  obj-$(CONFIG_SIBYTE_BCM112X)   += fixup-sb1250.o pci-sb1250.o
 108  obj-$(CONFIG_SIBYTE_BCM1x80)   += pci-bcm1480.o pci-bcm1480ht.o
 109  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
 110 -obj-$(CONFIG_SOC_XWAY)         += pci-lantiq.o ops-lantiq.o
 111 +obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
 112 +obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
 113 +obj-$(CONFIG_PCIE_LANTIQ)      += pcie-lantiq-phy.o pcie-lantiq.o fixup-lantiq-pcie.o
 114 +obj-$(CONFIG_PCIE_LANTIQ_MSI)  += pcie-lantiq-msi.o
 115  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
 116  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
 117  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
 118 diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
 119 index 1f2afb5..5cbb0cf 100644
 120 --- a/arch/mips/pci/ops-lantiq.c
 121 +++ b/arch/mips/pci/ops-lantiq.c
 122 @@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
 123
 124         spin_lock_irqsave(&ebu_lock, flags);
 125
 126 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 127 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
 128         cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
 129                         LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
 130
 131 @@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
 132         wmb();
 133
 134         /* clean possible Master abort */
 135 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 136 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
 137         cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
 138         temp = ltq_r32(((u32 *)(cfg_base)));
 139         temp = swab32(temp);
 140 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
 141 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
 142         cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
 143         ltq_w32(temp, ((u32 *)cfg_base));
 144
 145 diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
 146 index be1e1af..7a29738 100644
 147 --- a/arch/mips/pci/pci-lantiq.c
 148 +++ b/arch/mips/pci/pci-lantiq.c
 149 @@ -65,45 +65,42 @@
 150  #define ltq_pci_w32(x, y)      ltq_w32((x), ltq_pci_membase + (y))
 151  #define ltq_pci_r32(x)         ltq_r32(ltq_pci_membase + (x))
 152
 153 -#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_mapped_cfg + (y))
 154 -#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_mapped_cfg + (x))
 155 +#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_cfgbase + (y))
 156 +#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_cfgbase + (x))
 157
 158  struct ltq_pci_gpio_map {
 159         int pin;
 160 -       int alt0;
 161 -       int alt1;
 162 +       int mux;
 163         int dir;
 164         char *name;
 165  };
 166
 167  /* the pci core can make use of the following gpios */
 168  static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
 169 -       { 0, 1, 0, 0, "pci-exin0" },
 170 -       { 1, 1, 0, 0, "pci-exin1" },
 171 -       { 2, 1, 0, 0, "pci-exin2" },
 172 -       { 39, 1, 0, 0, "pci-exin3" },
 173 -       { 10, 1, 0, 0, "pci-exin4" },
 174 -       { 9, 1, 0, 0, "pci-exin5" },
 175 -       { 30, 1, 0, 1, "pci-gnt1" },
 176 -       { 23, 1, 0, 1, "pci-gnt2" },
 177 -       { 19, 1, 0, 1, "pci-gnt3" },
 178 -       { 38, 1, 0, 1, "pci-gnt4" },
 179 -       { 29, 1, 0, 0, "pci-req1" },
 180 -       { 31, 1, 0, 0, "pci-req2" },
 181 -       { 3, 1, 0, 0, "pci-req3" },
 182 -       { 37, 1, 0, 0, "pci-req4" },
 183 +       { 0, 2, 0, "pci-exin0" },
 184 +       { 1, 2, 0, "pci-exin1" },
 185 +       { 2, 1, 0, "pci-exin2" },
 186 +       { 39, 2, 0, "pci-exin3" },
 187 +       { 10, 2, 0, "pci-exin4" },
 188 +       { 9, 2, 0, "pci-exin5" },
 189 +       { 30, 2, 1, "pci-gnt1" },
 190 +       { 23, 1, 1, "pci-gnt2" },
 191 +       { 19, 2, 1, "pci-gnt3" },
 192 +       { 38, 2, 1, "pci-gnt4" },
 193 +       { 29, 2, 0, "pci-req1" },
 194 +       { 31, 1, 0, "pci-req2" },
 195 +       { 3, 3, 0, "pci-req3" },
 196 +       { 37, 2, 0, "pci-req4" },
 197  };
 198
 199 -__iomem void *ltq_pci_mapped_cfg;
 200 +__iomem void *ltq_pci_cfgbase;
 201  static __iomem void *ltq_pci_membase;
 202
 203 -int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
 204 -
 205  /* Since the PCI REQ pins can be reused for other functionality, make it
 206     possible to exclude those from interpretation by the PCI controller */
 207  static int ltq_pci_req_mask = 0xf;
 208
 209 -static int *ltq_pci_irq_map;
 210 +extern int *ltq_pci_irq_map;
 211
 212  struct pci_ops ltq_pci_ops = {
 213         .read   = ltq_pci_read_config_dword,
 214 @@ -132,14 +129,6 @@ static struct pci_controller ltq_pci_controller = {
 215         .io_offset      = 0x00000000UL,
 216  };
 217
 218 -int pcibios_plat_dev_init(struct pci_dev *dev)
 219 -{
 220 -       if (ltqpci_plat_dev_init)
 221 -               return ltqpci_plat_dev_init(dev);
 222 -
 223 -       return 0;
 224 -}
 225 -
 226  static u32 ltq_calc_bar11mask(void)
 227  {
 228         u32 mem, bar11mask;
 229 @@ -151,25 +140,26 @@ static u32 ltq_calc_bar11mask(void)
 230         return bar11mask;
 231  }
 232
 233 -static void ltq_pci_setup_gpio(int gpio)
 234 +static void ltq_pci_setup_gpio(struct device *dev)
 235  {
 236 +       struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
 237         int i;
 238         for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
 239 -               if (gpio & (1 << i)) {
 240 -                       ltq_gpio_request(ltq_pci_gpio_map[i].pin,
 241 -                               ltq_pci_gpio_map[i].alt0,
 242 -                               ltq_pci_gpio_map[i].alt1,
 243 +               if (conf->gpio & (1 << i)) {
 244 +                       ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin,
 245 +                               ltq_pci_gpio_map[i].mux,
 246                                 ltq_pci_gpio_map[i].dir,
 247                                 ltq_pci_gpio_map[i].name);
 248                 }
 249         }
 250 -       ltq_gpio_request(21, 0, 0, 1, "pci-reset");
 251 -       ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 252 +       ltq_gpio_request(dev, 21, 0, 1, "pci-reset");
 253 +       ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 254  }
 255
 256 -static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
 257 +static int __devinit ltq_pci_startup(struct device *dev)
 258  {
 259         u32 temp_buffer;
 260 +       struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
 261
 262         /* set clock to 33Mhz */
 263         if (ltq_is_ar9()) {
 264 @@ -192,7 +182,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
 265         }
 266
 267         /* setup pci clock and gpis used by pci */
 268 -       ltq_pci_setup_gpio(conf->gpio);
 269 +       ltq_pci_setup_gpio(dev);
 270
 271         /* enable auto-switching between PCI and EBU */
 272         ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
 273 @@ -256,16 +246,6 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
 274         return 0;
 275  }
 276
 277 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 278 -{
 279 -       if (ltq_pci_irq_map[slot])
 280 -               return ltq_pci_irq_map[slot];
 281 -       printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
 282 -               slot);
 283 -
 284 -       return 0;
 285 -}
 286 -
 287  static int __devinit ltq_pci_probe(struct platform_device *pdev)
 288  {
 289         struct ltq_pci_data *ltq_pci_data =
 290 @@ -273,11 +253,11 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
 291         pci_probe_only = 0;
 292         ltq_pci_irq_map = ltq_pci_data->irq;
 293         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
 294 -       ltq_pci_mapped_cfg =
 295 +       ltq_pci_cfgbase =
 296                 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
 297         ltq_pci_controller.io_map_base =
 298                 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
 299 -       ltq_pci_startup(ltq_pci_data);
 300 +       ltq_pci_startup(&pdev->dev);
 301         register_pci_controller(&ltq_pci_controller);
 302
 303         return 0;
 304 diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
 305 index 66bf6cd..c4721b4 100644
 306 --- a/arch/mips/pci/pci-lantiq.h
 307 +++ b/arch/mips/pci/pci-lantiq.h
 308 @@ -9,7 +9,7 @@
 309  #ifndef _LTQ_PCI_H__
 310  #define _LTQ_PCI_H__
 311
 312 -extern __iomem void *ltq_pci_mapped_cfg;
 313 +extern __iomem void *ltq_pci_cfgbase;
 314  extern int ltq_pci_read_config_dword(struct pci_bus *bus,
 315         unsigned int devfn, int where, int size, u32 *val);
 316  extern int ltq_pci_write_config_dword(struct pci_bus *bus,
 317 diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
 318 index 1552150..cd034a9 100644
 319 --- a/arch/mips/pci/pci.c
 320 +++ b/arch/mips/pci/pci.c
 321 @@ -201,6 +201,31 @@ static int __init pcibios_init(void)
 322
 323  subsys_initcall(pcibios_init);
 324
 325 +int pcibios_host_nr(void)
 326 +{
 327 +    int count;
 328 +    struct pci_controller *hose;
 329 +    for (count = 0, hose = hose_head; hose; hose = hose->next, count++) {
 330 +        ;
 331 +    }
 332 +    return count;
 333 +}
 334 +EXPORT_SYMBOL(pcibios_host_nr);
 335 +
 336 +int pcibios_1st_host_bus_nr(void)
 337 +{
 338 +    int bus_nr = 0;
 339 +    struct pci_controller *hose = hose_head;
 340 +
 341 +    if (hose != NULL) {
 342 +        if (hose->bus != NULL) {
 343 +            bus_nr = hose->bus->subordinate + 1;
 344 +        }
 345 +    }
 346 +    return bus_nr;
 347 +}
 348 +EXPORT_SYMBOL(pcibios_1st_host_bus_nr);
 349 +
 350  static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 351  {
 352         u16 cmd, old_cmd;
 353 --
 354 1.7.9.1
 355