1 --- a/arch/mips/lantiq/irq.c
2 +++ b/arch/mips/lantiq/irq.c
7 -static struct resource ltq_eiu_irq[MAX_EIU];
8 +static u32 ltq_eiu_irq[MAX_EIU];
9 static void __iomem *ltq_icu_membase[MAX_IM];
10 static void __iomem *ltq_eiu_membase;
11 static struct irq_domain *ltq_domain;
13 int ltq_eiu_get_irq(int exin)
15 if (exin < exin_avail)
16 - return ltq_eiu_irq[exin].start;
17 + return ltq_eiu_irq[exin];
24 for (i = 0; i < MAX_EIU; i++) {
25 - if (d->hwirq == ltq_eiu_irq[i].start) {
26 + if (d->hwirq == ltq_eiu_irq[i]) {
33 for (i = 0; i < MAX_EIU; i++) {
34 - if (d->hwirq == ltq_eiu_irq[i].start) {
35 + if (d->hwirq == ltq_eiu_irq[i]) {
36 /* by default we are low level triggered */
37 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
38 /* clear all pending */
42 for (i = 0; i < MAX_EIU; i++) {
43 - if (d->hwirq == ltq_eiu_irq[i].start) {
44 + if (d->hwirq == ltq_eiu_irq[i]) {
46 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
51 for (i = 0; i < exin_avail; i++)
52 - if (hw == ltq_eiu_irq[i].start)
53 + if (hw == ltq_eiu_irq[i])
56 - irq_set_chip_and_handler(hw, chip, handle_level_irq);
57 + irq_set_chip_and_handler(irq, chip, handle_level_irq);
62 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
63 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
64 /* find out how many external irq sources we have */
65 - exin_avail = of_irq_count(eiu_node);
66 + exin_avail = of_property_count_u32_elems(eiu_node, "lantiq,eiu-irqs");
68 if (exin_avail > MAX_EIU)
71 - ret = of_irq_to_resource_table(eiu_node,
72 + ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
73 ltq_eiu_irq, exin_avail);
74 - if (ret != exin_avail)
76 panic("failed to load external irq resources");
78 if (!request_mem_region(res.start, resource_size(&res),