1 From c8eedcadc38a5e6008d3990fbe0a5285b30335fc Mon Sep 17 00:00:00 2001
2 From: Mathias Kresin <dev@kresin.me>
3 Date: Sun, 7 Jul 2019 21:48:56 +0200
4 Subject: [PATCH] MIPS: lantiq: Add GPHY Firmware loader
6 Upstream, the GPHY Firmware loader has been merged into the DSA switch
7 driver. But we don't use the driver yet, so bring it back.
9 Signed-off-by: Mathias Kresin <dev@kresin.me>
11 .../bindings/mips/lantiq/rcu-gphy.txt | 36 +++
12 .../devicetree/bindings/mips/lantiq/rcu.txt | 18 ++
13 arch/mips/configs/xway_defconfig | 1 +
14 arch/mips/lantiq/Kconfig | 4 +
15 drivers/soc/lantiq/Makefile | 1 +
16 drivers/soc/lantiq/gphy.c | 224 ++++++++++++++++++
17 6 files changed, 284 insertions(+)
18 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
19 create mode 100644 drivers/soc/lantiq/gphy.c
22 +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
24 +Lantiq XWAY SoC GPHY binding
25 +============================
27 +This binding describes a software-defined ethernet PHY, provided by the RCU
28 +module on newer Lantiq XWAY SoCs (xRX200 and newer).
30 +-------------------------------------------------------------------------------
32 +- compatible : Should be one of
33 + "lantiq,xrx200-gphy"
34 + "lantiq,xrx200a1x-gphy"
35 + "lantiq,xrx200a2x-gphy"
36 + "lantiq,xrx300-gphy"
37 + "lantiq,xrx330-gphy"
38 +- reg : Addrress of the GPHY FW load address register
39 +- resets : Must reference the RCU GPHY reset bit
40 +- reset-names : One entry, value must be "gphy" or optional "gphy2"
41 +- clocks : A reference to the (PMU) GPHY clock gate
44 +- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
45 + <dt-bindings/mips/lantiq_xway_gphy.h>
48 +-------------------------------------------------------------------------------
49 +Example for the GPHys on the xRX200 SoCs:
51 +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
53 + compatible = "lantiq,xrx200a2x-gphy";
56 + resets = <&reset0 31 30>, <&reset1 7 7>;
57 + reset-names = "gphy", "gphy2";
58 + clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
59 + lantiq,gphy-mode = <GPHY_MODE_GE>;
61 --- a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
62 +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
63 @@ -26,6 +26,24 @@ Example of the RCU bindings on a xRX200
64 ranges = <0x0 0x203000 0x100>;
68 + compatible = "lantiq,xrx200a2x-gphy";
71 + resets = <&reset0 31 30>, <&reset1 7 7>;
72 + reset-names = "gphy", "gphy2";
73 + lantiq,gphy-mode = <GPHY_MODE_GE>;
77 + compatible = "lantiq,xrx200a2x-gphy";
80 + resets = <&reset0 29 28>, <&reset1 6 6>;
81 + reset-names = "gphy", "gphy2";
82 + lantiq,gphy-mode = <GPHY_MODE_GE>;
85 reset0: reset-controller@10 {
86 compatible = "lantiq,xrx200-reset";
87 reg = <0x10 4>, <0x14 4>;
88 --- a/arch/mips/configs/xway_defconfig
89 +++ b/arch/mips/configs/xway_defconfig
90 @@ -13,6 +13,7 @@ CONFIG_EMBEDDED=y
91 # CONFIG_COMPAT_BRK is not set
94 +CONFIG_XRX200_PHY_FW=y
95 CONFIG_CPU_MIPS32_R2=y
96 CONFIG_MIPS_VPE_LOADER=y
98 --- a/arch/mips/lantiq/Kconfig
99 +++ b/arch/mips/lantiq/Kconfig
100 @@ -62,4 +62,8 @@ config PCIE_LANTIQ_MSI
101 depends on PCIE_LANTIQ && PCI_MSI
104 +config XRX200_PHY_FW
105 + bool "XRX200 PHY firmware loader"
106 + depends on SOC_XWAY
109 --- a/drivers/soc/lantiq/Makefile
110 +++ b/drivers/soc/lantiq/Makefile
112 # SPDX-License-Identifier: GPL-2.0-only
114 +obj-$(CONFIG_XRX200_PHY_FW) += gphy.o
116 +++ b/drivers/soc/lantiq/gphy.c
119 + * This program is free software; you can redistribute it and/or modify it
120 + * under the terms of the GNU General Public License version 2 as published
121 + * by the Free Software Foundation.
123 + * Copyright (C) 2012 John Crispin <blogic@phrozen.org>
124 + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
125 + * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
128 +#include <linux/clk.h>
129 +#include <linux/delay.h>
130 +#include <linux/dma-mapping.h>
131 +#include <linux/firmware.h>
132 +#include <linux/mfd/syscon.h>
133 +#include <linux/module.h>
134 +#include <linux/reboot.h>
135 +#include <linux/regmap.h>
136 +#include <linux/reset.h>
137 +#include <linux/of_device.h>
138 +#include <linux/of_platform.h>
139 +#include <linux/property.h>
140 +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
142 +#include <lantiq_soc.h>
144 +#define XRX200_GPHY_FW_ALIGN (16 * 1024)
146 +struct xway_gphy_priv {
147 + struct clk *gphy_clk_gate;
148 + struct reset_control *gphy_reset;
149 + struct reset_control *gphy_reset2;
150 + void __iomem *membase;
154 +struct xway_gphy_match_data {
155 + char *fe_firmware_name;
156 + char *ge_firmware_name;
159 +static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
160 + .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
161 + .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
164 +static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
165 + .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
166 + .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
169 +static const struct xway_gphy_match_data xrx300_gphy_data = {
170 + .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
171 + .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
174 +static const struct of_device_id xway_gphy_match[] = {
175 + { .compatible = "lantiq,xrx200-gphy", .data = NULL },
176 + { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
177 + { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
178 + { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
179 + { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
182 +MODULE_DEVICE_TABLE(of, xway_gphy_match);
184 +static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
185 + dma_addr_t *dev_addr)
187 + const struct firmware *fw;
189 + dma_addr_t dma_addr;
193 + ret = request_firmware(&fw, priv->fw_name, dev);
195 + dev_err(dev, "failed to load firmware: %s, error: %i\n",
196 + priv->fw_name, ret);
201 + * GPHY cores need the firmware code in a persistent and contiguous
202 + * memory area with a 16 kB boundary aligned start address.
204 + size = fw->size + XRX200_GPHY_FW_ALIGN;
206 + fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
208 + fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
209 + *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
210 + memcpy(fw_addr, fw->data, fw->size);
212 + dev_err(dev, "failed to alloc firmware memory\n");
216 + release_firmware(fw);
221 +static int xway_gphy_of_probe(struct platform_device *pdev,
222 + struct xway_gphy_priv *priv)
224 + struct device *dev = &pdev->dev;
225 + const struct xway_gphy_match_data *gphy_fw_name_cfg;
228 + struct resource *res_gphy;
230 + gphy_fw_name_cfg = of_device_get_match_data(dev);
232 + if (of_device_is_compatible(pdev->dev.of_node, "lantiq,xrx200-gphy"))
233 + switch (ltq_soc_type()) {
235 + gphy_fw_name_cfg = &xrx200a1x_gphy_data;
237 + case SOC_TYPE_VR9_2:
238 + gphy_fw_name_cfg = &xrx200a2x_gphy_data;
242 + priv->gphy_clk_gate = devm_clk_get(dev, NULL);
243 + if (IS_ERR(priv->gphy_clk_gate)) {
244 + dev_err(dev, "Failed to lookup gate clock\n");
245 + return PTR_ERR(priv->gphy_clk_gate);
248 + res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
249 + priv->membase = devm_ioremap_resource(dev, res_gphy);
250 + if (IS_ERR(priv->membase))
251 + return PTR_ERR(priv->membase);
253 + priv->gphy_reset = devm_reset_control_get(dev, "gphy");
254 + if (IS_ERR(priv->gphy_reset)) {
255 + if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
256 + dev_err(dev, "Failed to lookup gphy reset\n");
257 + return PTR_ERR(priv->gphy_reset);
260 + priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
261 + if (IS_ERR(priv->gphy_reset2))
262 + return PTR_ERR(priv->gphy_reset2);
264 + ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
265 + /* Default to GE mode */
267 + gphy_mode = GPHY_MODE_GE;
269 + switch (gphy_mode) {
271 + priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
274 + priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
277 + dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
284 +static int xway_gphy_probe(struct platform_device *pdev)
286 + struct device *dev = &pdev->dev;
287 + struct xway_gphy_priv *priv;
288 + dma_addr_t fw_addr = 0;
291 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
295 + ret = xway_gphy_of_probe(pdev, priv);
299 + ret = clk_prepare_enable(priv->gphy_clk_gate);
303 + ret = xway_gphy_load(dev, priv, &fw_addr);
305 + clk_disable_unprepare(priv->gphy_clk_gate);
309 + reset_control_assert(priv->gphy_reset);
310 + reset_control_assert(priv->gphy_reset2);
312 + iowrite32be(fw_addr, priv->membase);
314 + reset_control_deassert(priv->gphy_reset);
315 + reset_control_deassert(priv->gphy_reset2);
317 + platform_set_drvdata(pdev, priv);
322 +static int xway_gphy_remove(struct platform_device *pdev)
324 + struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
326 + iowrite32be(0, priv->membase);
328 + clk_disable_unprepare(priv->gphy_clk_gate);
333 +static struct platform_driver xway_gphy_driver = {
334 + .probe = xway_gphy_probe,
335 + .remove = xway_gphy_remove,
337 + .name = "xway-rcu-gphy",
338 + .of_match_table = xway_gphy_match,
342 +module_platform_driver(xway_gphy_driver);
344 +MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
345 +MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
346 +MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
347 +MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
348 +MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
349 +MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
350 +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
351 +MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
352 +MODULE_LICENSE("GPL");