1 From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001
2 From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
3 Date: Sat, 16 Apr 2016 12:03:39 +0100
4 Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit
7 Currently dw_pcie_setup_rc() configures memory base and memory limit in the
8 type1 configuration header for the root complex. In doing so it uses the
9 CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
10 This is wrong and it is useless since the configuration is overwritten
11 later on when pci_bus_assign_resources() is called.
13 Remove this configuration from dw_pcie_setup_rc().
15 Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
16 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
17 Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
19 drivers/pci/host/pcie-designware.c | 8 --------
20 1 file changed, 8 deletions(-)
22 --- a/drivers/pci/host/pcie-designware.c
23 +++ b/drivers/pci/host/pcie-designware.c
24 @@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = {
25 void dw_pcie_setup_rc(struct pcie_port *pp)
31 /* set the number of lanes */
32 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
33 @@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port *
35 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
37 - /* setup memory base, memory limit */
38 - membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
39 - memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
40 - val = memlimit | membase;
41 - dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
43 /* setup command register */
44 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);