1 From 2ba4c76bc645b7b4ff04364f294f3022d369108a Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Thu, 5 Jul 2018 16:20:56 +0800
4 Subject: [PATCH 04/32] dts: support layercape
6 This is an integrated patch for layerscape dts support.
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 26 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 25 +
37 arch/arm/boot/dts/ls1021a.dtsi | 284 ++++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 18 +
48 .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++
49 .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 141 +++
50 .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 177 ++++
51 .../boot/dts/freescale/fsl-ls1012a-qds.dts | 166 ++++
52 .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 102 ++
53 .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 567 +++++++++++
54 .../boot/dts/freescale/fsl-ls1043-post.dtsi | 44 +
55 .../dts/freescale/fsl-ls1043a-qds-sdk.dts | 71 ++
56 .../boot/dts/freescale/fsl-ls1043a-qds.dts | 210 ++++-
57 .../dts/freescale/fsl-ls1043a-rdb-sdk.dts | 71 ++
58 .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
59 .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 152 ++-
60 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 357 +++++--
61 .../boot/dts/freescale/fsl-ls1046-post.dtsi | 48 +
62 .../dts/freescale/fsl-ls1046a-qds-sdk.dts | 112 +++
63 .../boot/dts/freescale/fsl-ls1046a-qds.dts | 326 +++++++
64 .../dts/freescale/fsl-ls1046a-rdb-sdk.dts | 85 ++
65 .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
66 .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 181 ++++
67 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 771 +++++++++++++++
68 .../boot/dts/freescale/fsl-ls1088a-qds.dts | 137 +++
69 .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 200 ++++
70 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 800 ++++++++++++++++
71 .../boot/dts/freescale/fsl-ls2080a-qds.dts | 229 +----
72 .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 207 ++--
73 .../boot/dts/freescale/fsl-ls2080a-simu.dts | 47 +-
74 .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 803 ++--------------
75 .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
76 .../boot/dts/freescale/fsl-ls2088a-qds.dts | 126 +++
77 .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 104 ++
78 .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 159 ++++
79 .../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 162 ++++
80 .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 136 +++
81 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 885 ++++++++++++++++++
82 .../dts/freescale/qoriq-bman-portals-sdk.dtsi | 55 ++
83 .../dts/freescale/qoriq-bman-portals.dtsi | 77 ++
84 .../boot/dts/freescale/qoriq-dpaa-eth.dtsi | 73 ++
85 .../dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
86 .../dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
87 .../dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
88 .../dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
89 .../dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
90 .../dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
91 .../dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
92 .../dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
93 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 +
94 .../boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
95 .../dts/freescale/qoriq-qman-portals-sdk.dtsi | 38 +
96 .../dts/freescale/qoriq-qman-portals.dtsi | 87 ++
97 .../boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
98 .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
99 .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
100 70 files changed, 8051 insertions(+), 1286 deletions(-)
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
122 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
123 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
124 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
135 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
136 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
137 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
138 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
139 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
140 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
141 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
142 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
144 --- a/arch/arm/boot/dts/alpine.dtsi
145 +++ b/arch/arm/boot/dts/alpine.dtsi
147 interrupt-controller;
148 reg = <0x0 0xfb001000 0x0 0x1000>,
149 <0x0 0xfb002000 0x0 0x2000>,
150 - <0x0 0xfb004000 0x0 0x1000>,
151 + <0x0 0xfb004000 0x0 0x2000>,
152 <0x0 0xfb006000 0x0 0x2000>;
154 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
155 --- a/arch/arm/boot/dts/axm55xx.dtsi
156 +++ b/arch/arm/boot/dts/axm55xx.dtsi
158 #address-cells = <0>;
159 interrupt-controller;
160 reg = <0x20 0x01001000 0 0x1000>,
161 - <0x20 0x01002000 0 0x1000>,
162 + <0x20 0x01002000 0 0x2000>,
163 <0x20 0x01004000 0 0x2000>,
164 <0x20 0x01006000 0 0x2000>;
165 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
166 --- a/arch/arm/boot/dts/ecx-2000.dts
167 +++ b/arch/arm/boot/dts/ecx-2000.dts
169 interrupt-controller;
170 interrupts = <1 9 0xf04>;
171 reg = <0xfff11000 0x1000>,
172 - <0xfff12000 0x1000>,
173 + <0xfff12000 0x2000>,
177 --- a/arch/arm/boot/dts/imx6ul.dtsi
178 +++ b/arch/arm/boot/dts/imx6ul.dtsi
182 intc: interrupt-controller@00a01000 {
183 - compatible = "arm,cortex-a7-gic";
184 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
185 #interrupt-cells = <3>;
186 interrupt-controller;
187 reg = <0x00a01000 0x1000>,
188 - <0x00a02000 0x1000>,
189 + <0x00a02000 0x2000>,
193 --- a/arch/arm/boot/dts/keystone.dtsi
194 +++ b/arch/arm/boot/dts/keystone.dtsi
198 gic: interrupt-controller {
199 - compatible = "arm,cortex-a15-gic";
200 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
201 #interrupt-cells = <3>;
202 interrupt-controller;
203 reg = <0x0 0x02561000 0x0 0x1000>,
204 <0x0 0x02562000 0x0 0x2000>,
205 - <0x0 0x02564000 0x0 0x1000>,
206 + <0x0 0x02564000 0x0 0x2000>,
207 <0x0 0x02566000 0x0 0x2000>;
208 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
209 IRQ_TYPE_LEVEL_HIGH)>;
210 --- a/arch/arm/boot/dts/ls1021a-qds.dts
211 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
220 + qflash0: s25fl128s@0 {
221 + compatible = "spansion,m25p80";
222 + #address-cells = <1>;
224 + spi-max-frequency = <20000000>;
230 tbi-handle = <&tbi0>;
231 phy-handle = <&sgmii_phy1c>;
237 + compatible = "fsl,ifc-nand";
238 + reg = <0x2 0x0 0x10000>;
241 fpga: board-control@3,0 {
242 #address-cells = <1>;
256 --- a/arch/arm/boot/dts/ls1021a-twr.dts
257 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
266 + qflash0: n25q128a13@0 {
267 + compatible = "n25q128a13", "jedec,spi-nor";
268 + #address-cells = <1>;
270 + spi-max-frequency = <20000000>;
276 tbi-handle = <&tbi1>;
277 phy-handle = <&sgmii_phy2>;
301 --- a/arch/arm/boot/dts/ls1021a.dtsi
302 +++ b/arch/arm/boot/dts/ls1021a.dtsi
305 #include "skeleton64.dtsi"
306 #include <dt-bindings/interrupt-controller/arm-gic.h>
307 +#include <dt-bindings/thermal/thermal.h>
310 compatible = "fsl,ls1021a";
312 #address-cells = <1>;
317 compatible = "arm,cortex-a7";
320 - clocks = <&cluster1_clk>;
321 + clocks = <&clockgen 1 0>;
322 + #cooling-cells = <2>;
327 compatible = "arm,cortex-a7";
330 - clocks = <&cluster1_clk>;
331 + clocks = <&clockgen 1 0>;
336 + compatible = "fixed-clock";
337 + #clock-cells = <0>;
338 + clock-frequency = <100000000>;
339 + clock-output-names = "sysclk";
343 compatible = "arm,armv7-timer";
344 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
345 @@ -108,11 +117,11 @@
348 gic: interrupt-controller@1400000 {
349 - compatible = "arm,cortex-a7-gic";
350 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
351 #interrupt-cells = <3>;
352 interrupt-controller;
353 reg = <0x0 0x1401000 0x0 0x1000>,
354 - <0x0 0x1402000 0x0 0x1000>,
355 + <0x0 0x1402000 0x0 0x2000>,
356 <0x0 0x1404000 0x0 0x2000>,
357 <0x0 0x1406000 0x0 0x2000>;
358 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
359 @@ -120,14 +129,14 @@
362 msi1: msi-controller@1570e00 {
363 - compatible = "fsl,1s1021a-msi";
364 + compatible = "fsl,ls1021a-msi";
365 reg = <0x0 0x1570e00 0x0 0x8>;
367 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
370 msi2: msi-controller@1570e08 {
371 - compatible = "fsl,1s1021a-msi";
372 + compatible = "fsl,ls1021a-msi";
373 reg = <0x0 0x1570e08 0x0 0x8>;
375 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
376 @@ -137,11 +146,12 @@
377 compatible = "fsl,ifc", "simple-bus";
378 reg = <0x0 0x1530000 0x0 0x10000>;
379 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
384 compatible = "fsl,ls1021a-dcfg", "syscon";
385 - reg = <0x0 0x1ee0000 0x0 0x10000>;
386 + reg = <0x0 0x1ee0000 0x0 0x1000>;
391 <0x0 0x20220520 0x0 0x4>;
392 reg-names = "ahci", "sata-ecc";
393 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
394 - clocks = <&platform_clk 1>;
395 + clocks = <&clockgen 4 1>;
399 @@ -214,43 +224,89 @@
402 clockgen: clocking@1ee1000 {
403 - #address-cells = <1>;
405 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
406 + compatible = "fsl,ls1021a-clockgen";
407 + reg = <0x0 0x1ee1000 0x0 0x1000>;
408 + #clock-cells = <2>;
409 + clocks = <&sysclk>;
413 - compatible = "fixed-clock";
414 - #clock-cells = <0>;
415 - clock-output-names = "sysclk";
418 - cga_pll1: pll@800 {
419 - compatible = "fsl,qoriq-core-pll-2.0";
420 - #clock-cells = <1>;
421 - reg = <0x800 0x10>;
422 - clocks = <&sysclk>;
423 - clock-output-names = "cga-pll1", "cga-pll1-div2",
427 - platform_clk: pll@c00 {
428 - compatible = "fsl,qoriq-core-pll-2.0";
429 - #clock-cells = <1>;
430 - reg = <0xc00 0x10>;
431 - clocks = <&sysclk>;
432 - clock-output-names = "platform-clk", "platform-clk-div2";
435 - cluster1_clk: clk0c0@0 {
436 - compatible = "fsl,qoriq-core-mux-2.0";
437 - #clock-cells = <0>;
439 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
440 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
441 - clock-output-names = "cluster1-clk";
443 + compatible = "fsl,qoriq-tmu";
444 + reg = <0x0 0x1f00000 0x0 0x10000>;
445 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
446 + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
447 + fsl,tmu-calibration = <0x00000000 0x0000000f
448 + 0x00000001 0x00000017
449 + 0x00000002 0x0000001e
450 + 0x00000003 0x00000026
451 + 0x00000004 0x0000002e
452 + 0x00000005 0x00000035
453 + 0x00000006 0x0000003d
454 + 0x00000007 0x00000044
455 + 0x00000008 0x0000004c
456 + 0x00000009 0x00000053
457 + 0x0000000a 0x0000005b
458 + 0x0000000b 0x00000064
460 + 0x00010000 0x00000011
461 + 0x00010001 0x0000001c
462 + 0x00010002 0x00000024
463 + 0x00010003 0x0000002b
464 + 0x00010004 0x00000034
465 + 0x00010005 0x00000039
466 + 0x00010006 0x00000042
467 + 0x00010007 0x0000004c
468 + 0x00010008 0x00000051
469 + 0x00010009 0x0000005a
470 + 0x0001000a 0x00000063
472 + 0x00020000 0x00000013
473 + 0x00020001 0x00000019
474 + 0x00020002 0x00000024
475 + 0x00020003 0x0000002c
476 + 0x00020004 0x00000035
477 + 0x00020005 0x0000003d
478 + 0x00020006 0x00000046
479 + 0x00020007 0x00000050
480 + 0x00020008 0x00000059
482 + 0x00030000 0x00000002
483 + 0x00030001 0x0000000d
484 + 0x00030002 0x00000019
485 + 0x00030003 0x00000024>;
486 + #thermal-sensor-cells = <1>;
490 + cpu_thermal: cpu-thermal {
491 + polling-delay-passive = <1000>;
492 + polling-delay = <5000>;
494 + thermal-sensors = <&tmu 0>;
497 + cpu_alert: cpu-alert {
498 + temperature = <85000>;
499 + hysteresis = <2000>;
502 + cpu_crit: cpu-crit {
503 + temperature = <95000>;
504 + hysteresis = <2000>;
511 + trip = <&cpu_alert>;
513 + <&cpu0 THERMAL_NO_LIMIT
520 dspi0: dspi@2100000 {
521 compatible = "fsl,ls1021a-v1.0-dspi";
522 #address-cells = <1>;
524 reg = <0x0 0x2100000 0x0 0x10000>;
525 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
526 clock-names = "dspi";
527 - clocks = <&platform_clk 1>;
528 + clocks = <&clockgen 4 1>;
529 spi-num-chipselects = <6>;
532 @@ -271,31 +327,48 @@
533 reg = <0x0 0x2110000 0x0 0x10000>;
534 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
535 clock-names = "dspi";
536 - clocks = <&platform_clk 1>;
537 + clocks = <&clockgen 4 1>;
538 spi-num-chipselects = <6>;
543 + qspi: quadspi@1550000 {
544 + compatible = "fsl,ls1021a-qspi";
545 + #address-cells = <1>;
547 + reg = <0x0 0x1550000 0x0 0x10000>,
548 + <0x0 0x40000000 0x0 0x4000000>;
549 + reg-names = "QuadSPI", "QuadSPI-memory";
550 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
551 + clock-names = "qspi_en", "qspi";
552 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
554 + amba-base = <0x40000000>;
555 + status = "disabled";
559 - compatible = "fsl,vf610-i2c";
560 + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
561 #address-cells = <1>;
563 reg = <0x0 0x2180000 0x0 0x10000>;
564 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
566 - clocks = <&platform_clk 1>;
567 + clocks = <&clockgen 4 1>;
568 + fsl-scl-gpio = <&gpio3 23 0>;
573 - compatible = "fsl,vf610-i2c";
574 + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
575 #address-cells = <1>;
577 reg = <0x0 0x2190000 0x0 0x10000>;
578 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
580 - clocks = <&platform_clk 1>;
581 + clocks = <&clockgen 4 1>;
582 + fsl-scl-gpio = <&gpio3 23 0>;
587 reg = <0x0 0x21a0000 0x0 0x10000>;
588 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
590 - clocks = <&platform_clk 1>;
591 + clocks = <&clockgen 4 1>;
596 compatible = "fsl,ls1021a-lpuart";
597 reg = <0x0 0x2960000 0x0 0x1000>;
598 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
599 - clocks = <&platform_clk 1>;
600 + clocks = <&clockgen 4 1>;
605 compatible = "fsl,ls1021a-lpuart";
606 reg = <0x0 0x2970000 0x0 0x1000>;
607 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
608 - clocks = <&platform_clk 1>;
609 + clocks = <&clockgen 4 1>;
614 compatible = "fsl,ls1021a-lpuart";
615 reg = <0x0 0x2980000 0x0 0x1000>;
616 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
617 - clocks = <&platform_clk 1>;
618 + clocks = <&clockgen 4 1>;
623 compatible = "fsl,ls1021a-lpuart";
624 reg = <0x0 0x2990000 0x0 0x1000>;
625 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
626 - clocks = <&platform_clk 1>;
627 + clocks = <&clockgen 4 1>;
631 @@ -435,16 +508,26 @@
632 compatible = "fsl,ls1021a-lpuart";
633 reg = <0x0 0x29a0000 0x0 0x1000>;
634 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
635 - clocks = <&platform_clk 1>;
636 + clocks = <&clockgen 4 1>;
641 + ftm0: ftm0@29d0000 {
642 + compatible = "fsl,ls1021a-ftm";
643 + reg = <0x0 0x29d0000 0x0 0x10000>,
644 + <0x0 0x1ee2140 0x0 0x4>;
645 + reg-names = "ftm", "FlexTimer1";
646 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
651 wdog0: watchdog@2ad0000 {
652 compatible = "fsl,imx21-wdt";
653 reg = <0x0 0x2ad0000 0x0 0x10000>;
654 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
655 - clocks = <&platform_clk 1>;
656 + clocks = <&clockgen 4 1>;
657 clock-names = "wdog-en";
661 compatible = "fsl,vf610-sai";
662 reg = <0x0 0x2b50000 0x0 0x10000>;
663 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
664 - clocks = <&platform_clk 1>, <&platform_clk 1>,
665 - <&platform_clk 1>, <&platform_clk 1>;
666 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
667 + <&clockgen 4 1>, <&clockgen 4 1>;
668 clock-names = "bus", "mclk1", "mclk2", "mclk3";
669 dma-names = "tx", "rx";
670 dmas = <&edma0 1 47>,
672 compatible = "fsl,vf610-sai";
673 reg = <0x0 0x2b60000 0x0 0x10000>;
674 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
675 - clocks = <&platform_clk 1>, <&platform_clk 1>,
676 - <&platform_clk 1>, <&platform_clk 1>;
677 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
678 + <&clockgen 4 1>, <&clockgen 4 1>;
679 clock-names = "bus", "mclk1", "mclk2", "mclk3";
680 dma-names = "tx", "rx";
681 dmas = <&edma0 1 45>,
682 @@ -489,16 +572,31 @@
685 clock-names = "dmamux0", "dmamux1";
686 - clocks = <&platform_clk 1>,
688 + clocks = <&clockgen 4 1>,
692 + qdma: qdma@8390000 {
693 + compatible = "fsl,ls1021a-qdma";
694 + reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
695 + <0x0 0x8399000 0x0 0x1000>, /* Status regs */
696 + <0x0 0x839a000 0x0 0x2000>; /* Block regs */
697 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
698 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
699 + interrupt-names = "qdma-error", "qdma-queue";
702 + status-sizes = <64>;
703 + queue-sizes = <64 64>;
708 compatible = "fsl,ls1021a-dcu";
709 reg = <0x0 0x2ce0000 0x0 0x10000>;
710 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
711 - clocks = <&platform_clk 0>,
713 + clocks = <&clockgen 4 0>,
715 clock-names = "dcu", "pix";
719 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
721 snps,quirk-frame-length-adjustment = <0x20>;
724 snps,dis_rxdet_inp3_quirk;
726 + snps,dis-u1u2-when-u3-quirk;
731 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
732 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
733 reg-names = "regs", "config";
734 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
735 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
736 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
737 + interrupt-names = "pme", "aer";
738 fsl,pcie-scfg = <&scfg 0>;
739 #address-cells = <3>;
742 bus-range = <0x0 0xff>;
743 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
744 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
745 - msi-parent = <&msi1>;
746 + msi-parent = <&msi1>, <&msi2>;
747 #interrupt-cells = <1>;
748 interrupt-map-mask = <0 0 0 7>;
749 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
751 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
752 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
753 reg-names = "regs", "config";
754 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
755 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
756 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
757 + interrupt-names = "pme", "aer";
758 fsl,pcie-scfg = <&scfg 1>;
759 #address-cells = <3>;
762 bus-range = <0x0 0xff>;
763 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
764 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
765 - msi-parent = <&msi2>;
766 + msi-parent = <&msi1>, <&msi2>;
767 #interrupt-cells = <1>;
768 interrupt-map-mask = <0 0 0 7>;
769 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
771 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
772 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
775 + can0: can@2a70000 {
776 + compatible = "fsl,ls1021ar2-flexcan";
777 + reg = <0x0 0x2a70000 0x0 0x1000>;
778 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
779 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
780 + clock-names = "ipg", "per";
782 + status = "disabled";
785 + can1: can@2a80000 {
786 + compatible = "fsl,ls1021ar2-flexcan";
787 + reg = <0x0 0x2a80000 0x0 0x1000>;
788 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
789 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
790 + clock-names = "ipg", "per";
792 + status = "disabled";
795 + can2: can@2a90000 {
796 + compatible = "fsl,ls1021ar2-flexcan";
797 + reg = <0x0 0x2a90000 0x0 0x1000>;
798 + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
799 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
800 + clock-names = "ipg", "per";
802 + status = "disabled";
805 + can3: can@2aa0000 {
806 + compatible = "fsl,ls1021ar2-flexcan";
807 + reg = <0x0 0x2aa0000 0x0 0x1000>;
808 + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
809 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
810 + clock-names = "ipg", "per";
812 + status = "disabled";
816 --- a/arch/arm/boot/dts/mt6580.dtsi
817 +++ b/arch/arm/boot/dts/mt6580.dtsi
819 #interrupt-cells = <3>;
820 interrupt-parent = <&gic>;
821 reg = <0x10211000 0x1000>,
822 - <0x10212000 0x1000>,
823 + <0x10212000 0x2000>,
827 --- a/arch/arm/boot/dts/mt6589.dtsi
828 +++ b/arch/arm/boot/dts/mt6589.dtsi
830 #interrupt-cells = <3>;
831 interrupt-parent = <&gic>;
832 reg = <0x10211000 0x1000>,
833 - <0x10212000 0x1000>,
834 + <0x10212000 0x2000>,
838 --- a/arch/arm/boot/dts/mt8127.dtsi
839 +++ b/arch/arm/boot/dts/mt8127.dtsi
841 #interrupt-cells = <3>;
842 interrupt-parent = <&gic>;
843 reg = <0 0x10211000 0 0x1000>,
844 - <0 0x10212000 0 0x1000>,
845 + <0 0x10212000 0 0x2000>,
846 <0 0x10214000 0 0x2000>,
847 <0 0x10216000 0 0x2000>;
849 --- a/arch/arm/boot/dts/mt8135.dtsi
850 +++ b/arch/arm/boot/dts/mt8135.dtsi
852 #interrupt-cells = <3>;
853 interrupt-parent = <&gic>;
854 reg = <0 0x10211000 0 0x1000>,
855 - <0 0x10212000 0 0x1000>,
856 + <0 0x10212000 0 0x2000>,
857 <0 0x10214000 0 0x2000>,
858 <0 0x10216000 0 0x2000>;
860 --- a/arch/arm/boot/dts/rk3288.dtsi
861 +++ b/arch/arm/boot/dts/rk3288.dtsi
862 @@ -1109,7 +1109,7 @@
863 #address-cells = <0>;
865 reg = <0xffc01000 0x1000>,
866 - <0xffc02000 0x1000>,
867 + <0xffc02000 0x2000>,
870 interrupts = <GIC_PPI 9 0xf04>;
871 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
872 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
874 gic: interrupt-controller@01c81000 {
875 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
876 reg = <0x01c81000 0x1000>,
877 - <0x01c82000 0x1000>,
878 + <0x01c82000 0x2000>,
881 interrupt-controller;
882 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
883 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
884 @@ -1685,9 +1685,9 @@
887 gic: interrupt-controller@01c81000 {
888 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
889 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
890 reg = <0x01c81000 0x1000>,
891 - <0x01c82000 0x1000>,
892 + <0x01c82000 0x2000>,
895 interrupt-controller;
896 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
897 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
899 gic: interrupt-controller@01c81000 {
900 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
901 reg = <0x01c81000 0x1000>,
902 - <0x01c82000 0x1000>,
903 + <0x01c82000 0x2000>,
906 interrupt-controller;
907 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
908 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
910 gic: interrupt-controller@01c41000 {
911 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
912 reg = <0x01c41000 0x1000>,
913 - <0x01c42000 0x1000>,
914 + <0x01c42000 0x2000>,
917 interrupt-controller;
918 --- a/arch/arm64/boot/dts/freescale/Makefile
919 +++ b/arch/arm64/boot/dts/freescale/Makefile
921 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
922 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
923 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
924 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
925 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
926 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
927 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
928 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
929 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
930 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
931 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
932 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
933 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
934 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
935 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
936 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
937 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
938 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
939 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
940 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
941 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
942 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
943 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
946 subdir-y := $(dts-dirs)
948 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
951 + * Device Tree file for NXP LS1012A 2G5RDB Board.
953 + * Copyright 2017 NXP
955 + * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
957 + * This file is dual-licensed: you can use it either under the terms
958 + * of the GPLv2 or the X11 license, at your option. Note that this dual
959 + * licensing only applies to this file, and not this project as a
962 + * a) This library is free software; you can redistribute it and/or
963 + * modify it under the terms of the GNU General Public License as
964 + * published by the Free Software Foundation; either version 2 of the
965 + * License, or (at your option) any later version.
967 + * This library is distributed in the hope that it will be useful,
968 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
969 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
970 + * GNU General Public License for more details.
972 + * Or, alternatively,
974 + * b) Permission is hereby granted, free of charge, to any person
975 + * obtaining a copy of this software and associated documentation
976 + * files (the "Software"), to deal in the Software without
977 + * restriction, including without limitation the rights to use,
978 + * copy, modify, merge, publish, distribute, sublicense, and/or
979 + * sell copies of the Software, and to permit persons to whom the
980 + * Software is furnished to do so, subject to the following
983 + * The above copyright notice and this permission notice shall be
984 + * included in all copies or substantial portions of the Software.
986 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
987 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
988 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
989 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
990 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
991 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
992 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
993 + * OTHER DEALINGS IN THE SOFTWARE.
997 +#include "fsl-ls1012a.dtsi"
1000 + model = "LS1012A 2G5RDB Board";
1001 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1004 + ethernet0 = &pfe_mac0;
1005 + ethernet1 = &pfe_mac1;
1022 + qflash0: s25fs512s@0 {
1023 + compatible = "spansion,m25p80";
1024 + #address-cells = <1>;
1025 + #size-cells = <1>;
1026 + spi-max-frequency = <20000000>;
1038 + #address-cells = <1>;
1039 + #size-cells = <0>;
1042 + compatible = "fsl,pfe-gemac-port";
1043 + #address-cells = <1>;
1044 + #size-cells = <0>;
1045 + reg = <0x0>; /* GEM_ID */
1046 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1047 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1048 + fsl,mdio-mux-val = <0x0>;
1049 + phy-mode = "sgmii-2500";
1050 + fsl,pfe-phy-if-flags = <0x0>;
1053 + reg = <0x1>; /* enabled/disabled */
1058 + compatible = "fsl,pfe-gemac-port";
1059 + #address-cells = <1>;
1060 + #size-cells = <0>;
1061 + reg = <0x1>; /* GEM_ID */
1062 + fsl,gemac-bus-id = < 0x0>; /* BUS_ID */
1063 + fsl,gemac-phy-id = < 0x2>; /* PHY_ID */
1064 + fsl,mdio-mux-val = <0x0>;
1065 + phy-mode = "sgmii-2500";
1066 + fsl,pfe-phy-if-flags = <0x0>;
1069 + reg = <0x0>; /* enabled/disabled */
1074 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
1076 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1078 + * Device Tree file for Freescale LS1012A Freedom Board.
1080 + * Copyright 2016 Freescale Semiconductor, Inc.
1085 +#include "fsl-ls1012a.dtsi"
1088 + model = "LS1012A Freedom Board";
1089 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
1092 + ethernet0 = &pfe_mac0;
1093 + ethernet1 = &pfe_mac1;
1096 + sys_mclk: clock-mclk {
1097 + compatible = "fixed-clock";
1098 + #clock-cells = <0>;
1099 + clock-frequency = <25000000>;
1102 + reg_1p8v: regulator-1p8v {
1103 + compatible = "regulator-fixed";
1104 + regulator-name = "1P8V";
1105 + regulator-min-microvolt = <1800000>;
1106 + regulator-max-microvolt = <1800000>;
1107 + regulator-always-on;
1111 + compatible = "simple-audio-card";
1112 + simple-audio-card,format = "i2s";
1113 + simple-audio-card,widgets =
1114 + "Microphone", "Microphone Jack",
1115 + "Headphone", "Headphone Jack",
1116 + "Speaker", "Speaker Ext",
1117 + "Line", "Line In Jack";
1118 + simple-audio-card,routing =
1119 + "MIC_IN", "Microphone Jack",
1120 + "Microphone Jack", "Mic Bias",
1121 + "LINE_IN", "Line In Jack",
1122 + "Headphone Jack", "HP_OUT",
1123 + "Speaker Ext", "LINE_OUT";
1125 + simple-audio-card,cpu {
1126 + sound-dai = <&sai2>;
1131 + simple-audio-card,codec {
1132 + sound-dai = <&codec>;
1135 + system-clock-frequency = <25000000>;
1147 + codec: sgtl5000@a {
1148 + #sound-dai-cells = <0>;
1149 + compatible = "fsl,sgtl5000";
1151 + VDDA-supply = <®_1p8v>;
1152 + VDDIO-supply = <®_1p8v>;
1153 + clocks = <&sys_mclk>;
1162 + qflash0: s25fs512s@0 {
1163 + compatible = "spansion,m25p80";
1164 + #address-cells = <1>;
1165 + #size-cells = <1>;
1167 + spi-max-frequency = <20000000>;
1174 + #address-cells = <1>;
1175 + #size-cells = <0>;
1178 + compatible = "fsl,pfe-gemac-port";
1179 + #address-cells = <1>;
1180 + #size-cells = <0>;
1181 + reg = <0x0>; /* GEM_ID */
1182 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1183 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1184 + fsl,mdio-mux-val = <0x0>;
1185 + phy-mode = "sgmii";
1186 + fsl,pfe-phy-if-flags = <0x0>;
1189 + reg = <0x1>; /* enabled/disabled */
1194 + compatible = "fsl,pfe-gemac-port";
1195 + #address-cells = <1>;
1196 + #size-cells = <0>;
1197 + reg = <0x1>; /* GEM_ID */
1198 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1199 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1200 + fsl,mdio-mux-val = <0x0>;
1201 + phy-mode = "sgmii";
1202 + fsl,pfe-phy-if-flags = <0x0>;
1205 + reg = <0x0>; /* enabled/disabled */
1218 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
1221 + * Device Tree file for NXP LS1012A FRWY Board.
1223 + * Copyright 2018 NXP
1225 + * This file is dual-licensed: you can use it either under the terms
1226 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1227 + * licensing only applies to this file, and not this project as a
1230 + * a) This library is free software; you can redistribute it and/or
1231 + * modify it under the terms of the GNU General Public License as
1232 + * published by the Free Software Foundation; either version 2 of the
1233 + * License, or (at your option) any later version.
1235 + * This library is distributed in the hope that it will be useful,
1236 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1237 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1238 + * GNU General Public License for more details.
1240 + * Or, alternatively,
1242 + * b) Permission is hereby granted, free of charge, to any person
1243 + * obtaining a copy of this software and associated documentation
1244 + * files (the "Software"), to deal in the Software without
1245 + * restriction, including without limitation the rights to use,
1246 + * copy, modify, merge, publish, distribute, sublicense, and/or
1247 + * sell copies of the Software, and to permit persons to whom the
1248 + * Software is furnished to do so, subject to the following
1251 + * The above copyright notice and this permission notice shall be
1252 + * included in all copies or substantial portions of the Software.
1254 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1255 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1256 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1257 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1258 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1259 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1260 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1261 + * OTHER DEALINGS IN THE SOFTWARE.
1265 +#include "fsl-ls1012a.dtsi"
1268 + model = "LS1012A FRWY Board";
1269 + compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
1272 + ethernet0 = &pfe_mac0;
1273 + ethernet1 = &pfe_mac1;
1276 + sys_mclk: clock-mclk {
1277 + compatible = "fixed-clock";
1278 + #clock-cells = <0>;
1279 + clock-frequency = <25000000>;
1282 + reg_1p8v: regulator-1p8v {
1283 + compatible = "regulator-fixed";
1284 + regulator-name = "1P8V";
1285 + regulator-min-microvolt = <1800000>;
1286 + regulator-max-microvolt = <1800000>;
1287 + regulator-always-on;
1291 + compatible = "simple-audio-card";
1292 + simple-audio-card,format = "i2s";
1293 + simple-audio-card,widgets =
1294 + "Microphone", "Microphone Jack",
1295 + "Headphone", "Headphone Jack",
1296 + "Speaker", "Speaker Ext",
1297 + "Line", "Line In Jack";
1298 + simple-audio-card,routing =
1299 + "MIC_IN", "Microphone Jack",
1300 + "Microphone Jack", "Mic Bias",
1301 + "LINE_IN", "Line In Jack",
1302 + "Headphone Jack", "HP_OUT",
1303 + "Speaker Ext", "LINE_OUT";
1305 + simple-audio-card,cpu {
1306 + sound-dai = <&sai2>;
1311 + simple-audio-card,codec {
1312 + sound-dai = <&codec>;
1315 + system-clock-frequency = <25000000>;
1331 + codec: sgtl5000@a {
1332 + compatible = "fsl,sgtl5000";
1333 + #sound-dai-cells = <0>;
1335 + VDDA-supply = <®_1p8v>;
1336 + VDDIO-supply = <®_1p8v>;
1337 + clocks = <&sys_mclk>;
1346 + qflash0: w25q16dw@0 {
1347 + compatible = "spansion,m25p80";
1348 + #address-cells = <1>;
1349 + #size-cells = <1>;
1351 + spi-max-frequency = <20000000>;
1358 + #address-cells = <1>;
1359 + #size-cells = <0>;
1362 + compatible = "fsl,pfe-gemac-port";
1363 + #address-cells = <1>;
1364 + #size-cells = <0>;
1365 + reg = <0x0>; /* GEM_ID */
1366 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1367 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1368 + fsl,mdio-mux-val = <0x0>;
1369 + phy-mode = "sgmii";
1370 + fsl,pfe-phy-if-flags = <0x0>;
1373 + reg = <0x1>; /* enabled/disabled */
1378 + compatible = "fsl,pfe-gemac-port";
1379 + #address-cells = <1>;
1380 + #size-cells = <0>;
1381 + reg = <0x1>; /* GEM_ID */
1382 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1383 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1384 + fsl,mdio-mux-val = <0x0>;
1385 + phy-mode = "sgmii";
1386 + fsl,pfe-phy-if-flags = <0x0>;
1389 + reg = <0x0>; /* enabled/disabled */
1398 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
1400 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1402 + * Device Tree file for Freescale LS1012A QDS Board.
1404 + * Copyright 2016 Freescale Semiconductor, Inc.
1409 +#include "fsl-ls1012a.dtsi"
1412 + model = "LS1012A QDS Board";
1413 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
1416 + ethernet0 = &pfe_mac0;
1417 + ethernet1 = &pfe_mac1;
1420 + sys_mclk: clock-mclk {
1421 + compatible = "fixed-clock";
1422 + #clock-cells = <0>;
1423 + clock-frequency = <24576000>;
1426 + reg_3p3v: regulator-3p3v {
1427 + compatible = "regulator-fixed";
1428 + regulator-name = "3P3V";
1429 + regulator-min-microvolt = <3300000>;
1430 + regulator-max-microvolt = <3300000>;
1431 + regulator-always-on;
1435 + compatible = "simple-audio-card";
1436 + simple-audio-card,format = "i2s";
1437 + simple-audio-card,widgets =
1438 + "Microphone", "Microphone Jack",
1439 + "Headphone", "Headphone Jack",
1440 + "Speaker", "Speaker Ext",
1441 + "Line", "Line In Jack";
1442 + simple-audio-card,routing =
1443 + "MIC_IN", "Microphone Jack",
1444 + "Microphone Jack", "Mic Bias",
1445 + "LINE_IN", "Line In Jack",
1446 + "Headphone Jack", "HP_OUT",
1447 + "Speaker Ext", "LINE_OUT";
1449 + simple-audio-card,cpu {
1450 + sound-dai = <&sai2>;
1455 + simple-audio-card,codec {
1456 + sound-dai = <&codec>;
1459 + system-clock-frequency = <24576000>;
1476 + compatible = "nxp,pca9547";
1478 + #address-cells = <1>;
1479 + #size-cells = <0>;
1482 + #address-cells = <1>;
1483 + #size-cells = <0>;
1486 + codec: sgtl5000@a {
1487 + #sound-dai-cells = <0>;
1488 + compatible = "fsl,sgtl5000";
1490 + VDDA-supply = <®_3p3v>;
1491 + VDDIO-supply = <®_3p3v>;
1492 + clocks = <&sys_mclk>;
1503 + qflash0: s25fs512s@0 {
1504 + compatible = "spansion,m25p80";
1505 + #address-cells = <1>;
1506 + #size-cells = <1>;
1507 + spi-max-frequency = <20000000>;
1515 + #address-cells = <1>;
1516 + #size-cells = <0>;
1519 + compatible = "fsl,pfe-gemac-port";
1520 + #address-cells = <1>;
1521 + #size-cells = <0>;
1522 + reg = <0x0>; /* GEM_ID */
1523 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1524 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1525 + fsl,mdio-mux-val = <0x2>;
1526 + phy-mode = "sgmii-2500";
1527 + fsl,pfe-phy-if-flags = <0x0>;
1530 + reg = <0x1>; /* enabled/disabled */
1535 + compatible = "fsl,pfe-gemac-port";
1536 + #address-cells = <1>;
1537 + #size-cells = <0>;
1538 + reg = <0x1>; /* GEM_ID */
1539 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1540 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1541 + fsl,mdio-mux-val = <0x3>;
1542 + phy-mode = "sgmii-2500";
1543 + fsl,pfe-phy-if-flags = <0x0>;
1546 + reg = <0x0>; /* enabled/disabled */
1567 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1569 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1571 + * Device Tree file for Freescale LS1012A RDB Board.
1573 + * Copyright 2016 Freescale Semiconductor, Inc.
1578 +#include "fsl-ls1012a.dtsi"
1581 + model = "LS1012A RDB Board";
1582 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1585 + ethernet0 = &pfe_mac0;
1586 + ethernet1 = &pfe_mac1;
1607 + qflash0: s25fs512s@0 {
1608 + compatible = "spansion,m25p80";
1609 + #address-cells = <1>;
1610 + #size-cells = <1>;
1611 + spi-max-frequency = <20000000>;
1636 + #address-cells = <1>;
1637 + #size-cells = <0>;
1640 + compatible = "fsl,pfe-gemac-port";
1641 + #address-cells = <1>;
1642 + #size-cells = <0>;
1643 + reg = <0x0>; /* GEM_ID */
1644 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1645 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1646 + fsl,mdio-mux-val = <0x0>;
1647 + phy-mode = "sgmii";
1648 + fsl,pfe-phy-if-flags = <0x0>;
1651 + reg = <0x1>; /* enabled/disabled */
1656 + compatible = "fsl,pfe-gemac-port";
1657 + #address-cells = <1>;
1658 + #size-cells = <0>;
1659 + reg = <0x1>; /* GEM_ID */
1660 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1661 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1662 + fsl,mdio-mux-val = <0x0>;
1663 + phy-mode = "rgmii-txid";
1664 + fsl,pfe-phy-if-flags = <0x0>;
1667 + reg = <0x0>; /* enabled/disabled */
1672 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1674 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1676 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1678 + * Copyright 2016 Freescale Semiconductor, Inc.
1682 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1683 +#include <dt-bindings/thermal/thermal.h>
1686 + compatible = "fsl,ls1012a";
1687 + interrupt-parent = <&gic>;
1688 + #address-cells = <2>;
1689 + #size-cells = <2>;
1697 + sec_mon = &sec_mon;
1701 + #address-cells = <1>;
1702 + #size-cells = <0>;
1705 + device_type = "cpu";
1706 + compatible = "arm,cortex-a53";
1708 + clocks = <&clockgen 1 0>;
1709 + #cooling-cells = <2>;
1710 + cpu-idle-states = <&CPU_PH20>;
1716 + * PSCI node is not added default, U-boot will add missing
1717 + * parts if it determines to use PSCI.
1719 + entry-method = "arm,psci";
1721 + CPU_PH20: cpu-ph20 {
1722 + compatible = "arm,idle-state";
1723 + idle-state-name = "PH20";
1724 + arm,psci-suspend-param = <0x0>;
1725 + entry-latency-us = <1000>;
1726 + exit-latency-us = <1000>;
1727 + min-residency-us = <3000>;
1732 + compatible = "fixed-clock";
1733 + #clock-cells = <0>;
1734 + clock-frequency = <125000000>;
1735 + clock-output-names = "sysclk";
1738 + coreclk: coreclk {
1739 + compatible = "fixed-clock";
1740 + #clock-cells = <0>;
1741 + clock-frequency = <100000000>;
1742 + clock-output-names = "coreclk";
1746 + compatible = "arm,armv8-timer";
1747 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1748 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1749 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1750 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1754 + compatible = "arm,armv8-pmuv3";
1755 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1758 + gic: interrupt-controller@1400000 {
1759 + compatible = "arm,gic-400";
1760 + #interrupt-cells = <3>;
1761 + interrupt-controller;
1762 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1763 + <0x0 0x1402000 0 0x2000>, /* GICC */
1764 + <0x0 0x1404000 0 0x2000>, /* GICH */
1765 + <0x0 0x1406000 0 0x2000>; /* GICV */
1766 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1770 + compatible = "syscon-reboot";
1777 + compatible = "simple-bus";
1778 + #address-cells = <2>;
1779 + #size-cells = <2>;
1782 + scfg: scfg@1570000 {
1783 + compatible = "fsl,ls1012a-scfg", "syscon";
1784 + reg = <0x0 0x1570000 0x0 0x10000>;
1788 + crypto: crypto@1700000 {
1789 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1791 + fsl,sec-era = <8>;
1792 + #address-cells = <1>;
1793 + #size-cells = <1>;
1794 + ranges = <0x0 0x00 0x1700000 0x100000>;
1795 + reg = <0x00 0x1700000 0x0 0x100000>;
1796 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1798 + sec_jr0: jr@10000 {
1799 + compatible = "fsl,sec-v5.4-job-ring",
1800 + "fsl,sec-v5.0-job-ring",
1801 + "fsl,sec-v4.0-job-ring";
1802 + reg = <0x10000 0x10000>;
1803 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1806 + sec_jr1: jr@20000 {
1807 + compatible = "fsl,sec-v5.4-job-ring",
1808 + "fsl,sec-v5.0-job-ring",
1809 + "fsl,sec-v4.0-job-ring";
1810 + reg = <0x20000 0x10000>;
1811 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1814 + sec_jr2: jr@30000 {
1815 + compatible = "fsl,sec-v5.4-job-ring",
1816 + "fsl,sec-v5.0-job-ring",
1817 + "fsl,sec-v4.0-job-ring";
1818 + reg = <0x30000 0x10000>;
1819 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1822 + sec_jr3: jr@40000 {
1823 + compatible = "fsl,sec-v5.4-job-ring",
1824 + "fsl,sec-v5.0-job-ring",
1825 + "fsl,sec-v4.0-job-ring";
1826 + reg = <0x40000 0x10000>;
1827 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1831 + compatible = "fsl,sec-v5.4-dma",
1832 + "fsl,sec-v5.0-dma",
1833 + "fsl,sec-v4.0-dma";
1837 + compatible = "fsl,sec-v5.4-rtic",
1838 + "fsl,sec-v5.0-rtic",
1839 + "fsl,sec-v4.0-rtic";
1840 + #address-cells = <1>;
1841 + #size-cells = <1>;
1842 + reg = <0x60000 0x100 0x60e00 0x18>;
1843 + ranges = <0x0 0x60100 0x500>;
1845 + rtic_a: rtic-a@0 {
1846 + compatible = "fsl,sec-v5.4-rtic-memory",
1847 + "fsl,sec-v5.0-rtic-memory",
1848 + "fsl,sec-v4.0-rtic-memory";
1849 + reg = <0x00 0x20 0x100 0x100>;
1852 + rtic_b: rtic-b@20 {
1853 + compatible = "fsl,sec-v5.4-rtic-memory",
1854 + "fsl,sec-v5.0-rtic-memory",
1855 + "fsl,sec-v4.0-rtic-memory";
1856 + reg = <0x20 0x20 0x200 0x100>;
1859 + rtic_c: rtic-c@40 {
1860 + compatible = "fsl,sec-v5.4-rtic-memory",
1861 + "fsl,sec-v5.0-rtic-memory",
1862 + "fsl,sec-v4.0-rtic-memory";
1863 + reg = <0x40 0x20 0x300 0x100>;
1866 + rtic_d: rtic-d@60 {
1867 + compatible = "fsl,sec-v5.4-rtic-memory",
1868 + "fsl,sec-v5.0-rtic-memory",
1869 + "fsl,sec-v4.0-rtic-memory";
1870 + reg = <0x60 0x20 0x400 0x100>;
1875 + sec_mon: sec_mon@1e90000 {
1876 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1877 + "fsl,sec-v4.0-mon";
1878 + reg = <0x0 0x1e90000 0x0 0x10000>;
1879 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1880 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1883 + dcfg: dcfg@1ee0000 {
1884 + compatible = "fsl,ls1012a-dcfg",
1886 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1890 + clockgen: clocking@1ee1000 {
1891 + compatible = "fsl,ls1012a-clockgen";
1892 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1893 + #clock-cells = <2>;
1894 + clocks = <&sysclk &coreclk>;
1895 + clock-names = "sysclk", "coreclk";
1898 + tmu: tmu@1f00000 {
1899 + compatible = "fsl,qoriq-tmu";
1900 + reg = <0x0 0x1f00000 0x0 0x10000>;
1901 + interrupts = <0 33 0x4>;
1902 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1903 + fsl,tmu-calibration = <0x00000000 0x00000026
1904 + 0x00000001 0x0000002d
1905 + 0x00000002 0x00000032
1906 + 0x00000003 0x00000039
1907 + 0x00000004 0x0000003f
1908 + 0x00000005 0x00000046
1909 + 0x00000006 0x0000004d
1910 + 0x00000007 0x00000054
1911 + 0x00000008 0x0000005a
1912 + 0x00000009 0x00000061
1913 + 0x0000000a 0x0000006a
1914 + 0x0000000b 0x00000071
1916 + 0x00010000 0x00000025
1917 + 0x00010001 0x0000002c
1918 + 0x00010002 0x00000035
1919 + 0x00010003 0x0000003d
1920 + 0x00010004 0x00000045
1921 + 0x00010005 0x0000004e
1922 + 0x00010006 0x00000057
1923 + 0x00010007 0x00000061
1924 + 0x00010008 0x0000006b
1925 + 0x00010009 0x00000076
1927 + 0x00020000 0x00000029
1928 + 0x00020001 0x00000033
1929 + 0x00020002 0x0000003d
1930 + 0x00020003 0x00000049
1931 + 0x00020004 0x00000056
1932 + 0x00020005 0x00000061
1933 + 0x00020006 0x0000006d
1935 + 0x00030000 0x00000021
1936 + 0x00030001 0x0000002a
1937 + 0x00030002 0x0000003c
1938 + 0x00030003 0x0000004e>;
1940 + #thermal-sensor-cells = <1>;
1944 + cpu_thermal: cpu-thermal {
1945 + polling-delay-passive = <1000>;
1946 + polling-delay = <5000>;
1947 + thermal-sensors = <&tmu 0>;
1950 + cpu_alert: cpu-alert {
1951 + temperature = <85000>;
1952 + hysteresis = <2000>;
1956 + cpu_crit: cpu-crit {
1957 + temperature = <95000>;
1958 + hysteresis = <2000>;
1959 + type = "critical";
1965 + trip = <&cpu_alert>;
1967 + <&cpu0 THERMAL_NO_LIMIT
1968 + THERMAL_NO_LIMIT>;
1974 + esdhc0: esdhc@1560000 {
1975 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1976 + reg = <0x0 0x1560000 0x0 0x10000>;
1977 + interrupts = <0 62 0x4>;
1978 + clocks = <&clockgen 4 0>;
1979 + voltage-ranges = <1800 1800 3300 3300>;
1983 + status = "disabled";
1986 + esdhc1: esdhc@1580000 {
1987 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1988 + reg = <0x0 0x1580000 0x0 0x10000>;
1989 + interrupts = <0 65 0x4>;
1990 + clocks = <&clockgen 4 0>;
1991 + voltage-ranges = <1800 1800 3300 3300>;
1996 + status = "disabled";
1999 + rcpm: rcpm@1ee2000 {
2000 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
2001 + reg = <0x0 0x1ee2000 0x0 0x1000>;
2002 + fsl,#rcpm-wakeup-cells = <1>;
2005 + ftm0: ftm0@29d0000 {
2006 + compatible = "fsl,ls1012a-ftm";
2007 + reg = <0x0 0x29d0000 0x0 0x10000>,
2008 + <0x0 0x1ee2140 0x0 0x4>;
2009 + reg-names = "ftm", "FlexTimer1";
2010 + interrupts = <0 86 0x4>;
2014 + i2c0: i2c@2180000 {
2015 + compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
2016 + #address-cells = <1>;
2017 + #size-cells = <0>;
2018 + reg = <0x0 0x2180000 0x0 0x10000>;
2019 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
2020 + clocks = <&clockgen 4 3>;
2021 + fsl-scl-gpio = <&gpio0 13 0>;
2022 + status = "disabled";
2025 + i2c1: i2c@2190000 {
2026 + compatible = "fsl,vf610-i2c";
2027 + #address-cells = <1>;
2028 + #size-cells = <0>;
2029 + reg = <0x0 0x2190000 0x0 0x10000>;
2030 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
2031 + clocks = <&clockgen 4 3>;
2032 + status = "disabled";
2035 + duart0: serial@21c0500 {
2036 + compatible = "fsl,ns16550", "ns16550a";
2037 + reg = <0x00 0x21c0500 0x0 0x100>;
2038 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
2039 + clocks = <&clockgen 4 0>;
2040 + status = "disabled";
2043 + duart1: serial@21c0600 {
2044 + compatible = "fsl,ns16550", "ns16550a";
2045 + reg = <0x00 0x21c0600 0x0 0x100>;
2046 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
2047 + clocks = <&clockgen 4 0>;
2048 + status = "disabled";
2051 + gpio0: gpio@2300000 {
2052 + compatible = "fsl,qoriq-gpio";
2053 + reg = <0x0 0x2300000 0x0 0x10000>;
2054 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
2056 + #gpio-cells = <2>;
2057 + interrupt-controller;
2058 + #interrupt-cells = <2>;
2061 + gpio1: gpio@2310000 {
2062 + compatible = "fsl,qoriq-gpio";
2063 + reg = <0x0 0x2310000 0x0 0x10000>;
2064 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
2066 + #gpio-cells = <2>;
2067 + interrupt-controller;
2068 + #interrupt-cells = <2>;
2071 + qspi: quadspi@1550000 {
2072 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
2073 + #address-cells = <1>;
2074 + #size-cells = <0>;
2075 + reg = <0x0 0x1550000 0x0 0x10000>,
2076 + <0x0 0x40000000 0x0 0x10000000>;
2077 + reg-names = "QuadSPI", "QuadSPI-memory";
2078 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
2079 + clock-names = "qspi_en", "qspi";
2080 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
2082 + fsl,qspi-has-second-chip;
2083 + status = "disabled";
2086 + wdog0: wdog@2ad0000 {
2087 + compatible = "fsl,ls1012a-wdt",
2089 + reg = <0x0 0x2ad0000 0x0 0x10000>;
2090 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
2091 + clocks = <&clockgen 4 0>;
2095 + sai1: sai@2b50000 {
2096 + #sound-dai-cells = <0>;
2097 + compatible = "fsl,vf610-sai";
2098 + reg = <0x0 0x2b50000 0x0 0x10000>;
2099 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
2100 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
2101 + <&clockgen 4 3>, <&clockgen 4 3>;
2102 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
2103 + dma-names = "tx", "rx";
2104 + dmas = <&edma0 1 47>,
2106 + status = "disabled";
2109 + sai2: sai@2b60000 {
2110 + #sound-dai-cells = <0>;
2111 + compatible = "fsl,vf610-sai";
2112 + reg = <0x0 0x2b60000 0x0 0x10000>;
2113 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
2114 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
2115 + <&clockgen 4 3>, <&clockgen 4 3>;
2116 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
2117 + dma-names = "tx", "rx";
2118 + dmas = <&edma0 1 45>,
2120 + status = "disabled";
2123 + edma0: edma@2c00000 {
2125 + compatible = "fsl,vf610-edma";
2126 + reg = <0x0 0x2c00000 0x0 0x10000>,
2127 + <0x0 0x2c10000 0x0 0x10000>,
2128 + <0x0 0x2c20000 0x0 0x10000>;
2129 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
2130 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
2131 + interrupt-names = "edma-tx", "edma-err";
2132 + dma-channels = <32>;
2134 + clock-names = "dmamux0", "dmamux1";
2135 + clocks = <&clockgen 4 3>,
2139 + usb0: usb3@2f00000 {
2140 + compatible = "snps,dwc3";
2141 + reg = <0x0 0x2f00000 0x0 0x10000>;
2142 + interrupts = <0 60 0x4>;
2144 + snps,quirk-frame-length-adjustment = <0x20>;
2145 + snps,dis_rxdet_inp3_quirk;
2148 + usb1: usb2@8600000 {
2149 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
2150 + reg = <0x0 0x8600000 0x0 0x1000>;
2151 + interrupts = <0 139 0x4>;
2153 + phy_type = "ulpi";
2156 + sata: sata@3200000 {
2157 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
2158 + reg = <0x0 0x3200000 0x0 0x10000>,
2159 + <0x0 0x20140520 0x0 0x4>;
2160 + reg-names = "ahci", "sata-ecc";
2161 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
2162 + clocks = <&clockgen 4 0>;
2164 + status = "disabled";
2167 + msi: msi-controller1@1572000 {
2168 + compatible = "fsl,ls1012a-msi";
2169 + reg = <0x0 0x1572000 0x0 0x8>;
2171 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
2174 + pcie: pcie@3400000 {
2175 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
2176 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2177 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2178 + reg-names = "regs", "config";
2179 + interrupts = <0 118 0x4>, /* AER interrupt */
2180 + <0 117 0x4>; /* PME interrupt */
2181 + interrupt-names = "aer", "pme";
2182 + #address-cells = <3>;
2183 + #size-cells = <2>;
2184 + device_type = "pci";
2186 + bus-range = <0x0 0xff>;
2187 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2188 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2189 + msi-parent = <&msi>;
2190 + #interrupt-cells = <1>;
2191 + interrupt-map-mask = <0 0 0 7>;
2192 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
2193 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
2194 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
2195 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
2196 + status = "disabled";
2201 + #address-cells = <2>;
2202 + #size-cells = <2>;
2205 + pfe_reserved: packetbuffer@83400000 {
2206 + reg = <0 0x83400000 0 0xc00000>;
2210 + pfe: pfe@04000000 {
2211 + compatible = "fsl,pfe";
2212 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
2213 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
2214 + reg-names = "pfe", "pfe-ddr";
2215 + fsl,pfe-num-interfaces = <0x2>;
2216 + interrupts = <0 172 0x4>, /* HIF interrupt */
2217 + <0 173 0x4>, /*HIF_NOCPY interrupt */
2218 + <0 174 0x4>; /* WoL interrupt */
2219 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
2220 + memory-region = <&pfe_reserved>;
2221 + fsl,pfe-scfg = <&scfg 0>;
2222 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
2223 + clocks = <&clockgen 4 0>;
2224 + clock-names = "pfe";
2227 + pfe_mac0: ethernet@0 {
2230 + pfe_mac1: ethernet@1 {
2236 + compatible = "linaro,optee-tz";
2242 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
2244 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2246 + * QorIQ FMan v3 device tree nodes for ls1043
2248 + * Copyright 2015-2016 Freescale Semiconductor Inc.
2253 +/* include used FMan blocks */
2254 +#include "qoriq-fman3-0.dtsi"
2255 +#include "qoriq-fman3-0-1g-0.dtsi"
2256 +#include "qoriq-fman3-0-1g-1.dtsi"
2257 +#include "qoriq-fman3-0-1g-2.dtsi"
2258 +#include "qoriq-fman3-0-1g-3.dtsi"
2259 +#include "qoriq-fman3-0-1g-4.dtsi"
2260 +#include "qoriq-fman3-0-1g-5.dtsi"
2261 +#include "qoriq-fman3-0-10g-0.dtsi"
2266 + /* these aliases provide the FMan ports mapping */
2267 + enet0: ethernet@e0000 {
2270 + enet1: ethernet@e2000 {
2273 + enet2: ethernet@e4000 {
2276 + enet3: ethernet@e6000 {
2279 + enet4: ethernet@e8000 {
2282 + enet5: ethernet@ea000 {
2285 + enet6: ethernet@f0000 {
2289 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
2292 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2294 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2296 + * Mingkai Hu <Mingkai.hu@freescale.com>
2298 + * This file is dual-licensed: you can use it either under the terms
2299 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2300 + * licensing only applies to this file, and not this project as a
2303 + * a) This library is free software; you can redistribute it and/or
2304 + * modify it under the terms of the GNU General Public License as
2305 + * published by the Free Software Foundation; either version 2 of the
2306 + * License, or (at your option) any later version.
2308 + * This library is distributed in the hope that it will be useful,
2309 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2310 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2311 + * GNU General Public License for more details.
2313 + * Or, alternatively,
2315 + * b) Permission is hereby granted, free of charge, to any person
2316 + * obtaining a copy of this software and associated documentation
2317 + * files (the "Software"), to deal in the Software without
2318 + * restriction, including without limitation the rights to use,
2319 + * copy, modify, merge, publish, distribute, sublicense, and/or
2320 + * sell copies of the Software, and to permit persons to whom the
2321 + * Software is furnished to do so, subject to the following
2324 + * The above copyright notice and this permission notice shall be
2325 + * included in all copies or substantial portions of the Software.
2327 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2328 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2329 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2330 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2331 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2332 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2333 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2334 + * OTHER DEALINGS IN THE SOFTWARE.
2337 +#include "fsl-ls1043a-qds.dts"
2338 +#include "qoriq-qman-portals-sdk.dtsi"
2339 +#include "qoriq-bman-portals-sdk.dtsi"
2342 + compatible = "fsl,bman-fbpr";
2343 + alloc-ranges = <0 0 0x10000 0>;
2346 + compatible = "fsl,qman-fqd";
2347 + alloc-ranges = <0 0 0x10000 0>;
2350 + compatible = "fsl,qman-pfdr";
2351 + alloc-ranges = <0 0 0x10000 0>;
2355 +#include "qoriq-dpaa-eth.dtsi"
2356 +#include "qoriq-fman3-0-6oh.dtsi"
2360 + compatible = "fsl,fman", "simple-bus";
2362 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2363 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2365 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2367 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2369 - * Copyright 2014-2015, Freescale Semiconductor
2370 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2372 * Mingkai Hu <Mingkai.hu@freescale.com>
2374 - * This file is dual-licensed: you can use it either under the terms
2375 - * of the GPLv2 or the X11 license, at your option. Note that this dual
2376 - * licensing only applies to this file, and not this project as a
2379 - * a) This library is free software; you can redistribute it and/or
2380 - * modify it under the terms of the GNU General Public License as
2381 - * published by the Free Software Foundation; either version 2 of the
2382 - * License, or (at your option) any later version.
2384 - * This library is distributed in the hope that it will be useful,
2385 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2386 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2387 - * GNU General Public License for more details.
2389 - * Or, alternatively,
2391 - * b) Permission is hereby granted, free of charge, to any person
2392 - * obtaining a copy of this software and associated documentation
2393 - * files (the "Software"), to deal in the Software without
2394 - * restriction, including without limitation the rights to use,
2395 - * copy, modify, merge, publish, distribute, sublicense, and/or
2396 - * sell copies of the Software, and to permit persons to whom the
2397 - * Software is furnished to do so, subject to the following
2400 - * The above copyright notice and this permission notice shall be
2401 - * included in all copies or substantial portions of the Software.
2403 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2404 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2405 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2406 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2407 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2408 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2409 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2410 - * OTHER DEALINGS IN THE SOFTWARE.
2414 -/include/ "fsl-ls1043a.dtsi"
2415 +#include "fsl-ls1043a.dtsi"
2418 model = "LS1043A QDS Board";
2423 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2424 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2425 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2426 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2427 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2428 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2429 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2430 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2431 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2432 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2433 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2434 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2435 + emi1_slot1 = &ls1043mdio_s1;
2436 + emi1_slot2 = &ls1043mdio_s2;
2437 + emi1_slot3 = &ls1043mdio_s3;
2438 + emi1_slot4 = &ls1043mdio_s4;
2445 fpga: board-control@2,0 {
2446 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2447 + #address-cells = <1>;
2448 + #size-cells = <1>;
2449 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2450 reg = <0x2 0x0 0x0000100>;
2451 + ranges = <0 2 0 0x100>;
2455 @@ -181,3 +163,149 @@
2460 +#include "fsl-ls1043-post.dtsi"
2464 + phy-handle = <&qsgmii_phy_s2_p1>;
2465 + phy-connection-type = "sgmii";
2469 + phy-handle = <&qsgmii_phy_s2_p2>;
2470 + phy-connection-type = "sgmii";
2474 + phy-handle = <&rgmii_phy1>;
2475 + phy-connection-type = "rgmii";
2479 + phy-handle = <&rgmii_phy2>;
2480 + phy-connection-type = "rgmii";
2484 + phy-handle = <&qsgmii_phy_s2_p3>;
2485 + phy-connection-type = "sgmii";
2489 + phy-handle = <&qsgmii_phy_s2_p4>;
2490 + phy-connection-type = "sgmii";
2493 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2494 + fixed-link = <1 1 10000 0 0>;
2495 + phy-connection-type = "xgmii";
2501 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2502 + mdio-parent-bus = <&mdio0>;
2503 + #address-cells = <1>;
2504 + #size-cells = <0>;
2505 + reg = <0x54 1>; /* BRDCFG4 */
2506 + mux-mask = <0xe0>; /* EMI1 */
2508 + /* On-board RGMII1 PHY */
2509 + ls1043mdio0: mdio@0 {
2511 + #address-cells = <1>;
2512 + #size-cells = <0>;
2514 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2519 + /* On-board RGMII2 PHY */
2520 + ls1043mdio1: mdio@1 {
2522 + #address-cells = <1>;
2523 + #size-cells = <0>;
2525 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2531 + ls1043mdio_s1: mdio@2 {
2533 + #address-cells = <1>;
2534 + #size-cells = <0>;
2535 + status = "disabled";
2537 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2540 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2543 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2546 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2550 + sgmii_phy_s1_p1: ethernet-phy@1c {
2556 + ls1043mdio_s2: mdio@3 {
2558 + #address-cells = <1>;
2559 + #size-cells = <0>;
2560 + status = "disabled";
2562 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2565 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2568 + qsgmii_phy_s2_p3: ethernet-phy@a {
2571 + qsgmii_phy_s2_p4: ethernet-phy@b {
2575 + sgmii_phy_s2_p1: ethernet-phy@1c {
2581 + ls1043mdio_s3: mdio@4 {
2583 + #address-cells = <1>;
2584 + #size-cells = <0>;
2585 + status = "disabled";
2587 + sgmii_phy_s3_p1: ethernet-phy@1c {
2593 + ls1043mdio_s4: mdio@5 {
2595 + #address-cells = <1>;
2596 + #size-cells = <0>;
2597 + status = "disabled";
2599 + sgmii_phy_s4_p1: ethernet-phy@1c {
2606 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2609 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2611 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2613 + * Mingkai Hu <Mingkai.hu@freescale.com>
2615 + * This file is dual-licensed: you can use it either under the terms
2616 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2617 + * licensing only applies to this file, and not this project as a
2620 + * a) This library is free software; you can redistribute it and/or
2621 + * modify it under the terms of the GNU General Public License as
2622 + * published by the Free Software Foundation; either version 2 of the
2623 + * License, or (at your option) any later version.
2625 + * This library is distributed in the hope that it will be useful,
2626 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2627 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2628 + * GNU General Public License for more details.
2630 + * Or, alternatively,
2632 + * b) Permission is hereby granted, free of charge, to any person
2633 + * obtaining a copy of this software and associated documentation
2634 + * files (the "Software"), to deal in the Software without
2635 + * restriction, including without limitation the rights to use,
2636 + * copy, modify, merge, publish, distribute, sublicense, and/or
2637 + * sell copies of the Software, and to permit persons to whom the
2638 + * Software is furnished to do so, subject to the following
2641 + * The above copyright notice and this permission notice shall be
2642 + * included in all copies or substantial portions of the Software.
2644 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2645 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2646 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2647 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2648 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2649 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2650 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2651 + * OTHER DEALINGS IN THE SOFTWARE.
2654 +#include "fsl-ls1043a-rdb.dts"
2655 +#include "qoriq-qman-portals-sdk.dtsi"
2656 +#include "qoriq-bman-portals-sdk.dtsi"
2659 + compatible = "fsl,bman-fbpr";
2660 + alloc-ranges = <0 0 0x10000 0>;
2663 + compatible = "fsl,qman-fqd";
2664 + alloc-ranges = <0 0 0x10000 0>;
2667 + compatible = "fsl,qman-pfdr";
2668 + alloc-ranges = <0 0 0x10000 0>;
2672 +#include "qoriq-dpaa-eth.dtsi"
2673 +#include "qoriq-fman3-0-6oh.dtsi"
2677 + compatible = "fsl,fman", "simple-bus";
2680 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2683 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2685 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2687 + * This file is licensed under the terms of the GNU General Public
2688 + * License version 2. This program is licensed "as is" without any
2689 + * warranty of any kind, whether express or implied.
2692 +#include "fsl-ls1043a-rdb-sdk.dts"
2695 + bp7: buffer-pool@7 {
2696 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2698 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2699 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2702 + bp8: buffer-pool@8 {
2703 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2705 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2706 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2709 + bp9: buffer-pool@9 {
2710 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2712 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2713 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2717 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2720 + compatible = "fsl,dpa-ethernet-init";
2721 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2722 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2723 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2727 + compatible = "fsl,dpa-ethernet-init";
2728 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2729 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2730 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2734 + compatible = "fsl,dpa-ethernet-init";
2735 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2736 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2737 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2741 + compatible = "fsl,dpa-ethernet-init";
2742 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2743 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2744 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2748 + compatible = "fsl,dpa-ethernet-init";
2749 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2750 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2751 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2755 + compatible = "fsl,dpa-ethernet-init";
2756 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2757 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2758 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2762 + compatible = "fsl,dpa-ethernet-init";
2763 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2764 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2765 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2769 + compatible = "fsl,dpa-oh";
2770 + /* Define frame queues for the OH port*/
2771 + /* <OH Rx error, OH Rx default> */
2772 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2773 + fsl,fman-oh-port = <&fman0_oh2>;
2779 + #address-cells = <2>;
2780 + #size-cells = <2>;
2783 + usdpaa_mem: usdpaa_mem {
2784 + compatible = "fsl,usdpaa-mem";
2785 + alloc-ranges = <0 0 0x10000 0>;
2786 + size = <0 0x10000000>;
2787 + alignment = <0 0x10000000>;
2793 + fman0_oh2: port@83000 {
2795 + compatible = "fsl,fman-port-oh";
2796 + reg = <0x83000 0x1000>;
2799 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2800 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2802 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2804 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2806 - * Copyright 2014-2015, Freescale Semiconductor
2807 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2809 * Mingkai Hu <Mingkai.hu@freescale.com>
2811 - * This file is dual-licensed: you can use it either under the terms
2812 - * of the GPLv2 or the X11 license, at your option. Note that this dual
2813 - * licensing only applies to this file, and not this project as a
2816 - * a) This library is free software; you can redistribute it and/or
2817 - * modify it under the terms of the GNU General Public License as
2818 - * published by the Free Software Foundation; either version 2 of the
2819 - * License, or (at your option) any later version.
2821 - * This library is distributed in the hope that it will be useful,
2822 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2823 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2824 - * GNU General Public License for more details.
2826 - * Or, alternatively,
2828 - * b) Permission is hereby granted, free of charge, to any person
2829 - * obtaining a copy of this software and associated documentation
2830 - * files (the "Software"), to deal in the Software without
2831 - * restriction, including without limitation the rights to use,
2832 - * copy, modify, merge, publish, distribute, sublicense, and/or
2833 - * sell copies of the Software, and to permit persons to whom the
2834 - * Software is furnished to do so, subject to the following
2837 - * The above copyright notice and this permission notice shall be
2838 - * included in all copies or substantial portions of the Software.
2840 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2841 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2842 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2843 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2844 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2845 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2846 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2847 - * OTHER DEALINGS IN THE SOFTWARE.
2851 -/include/ "fsl-ls1043a.dtsi"
2852 +#include "fsl-ls1043a.dtsi"
2855 model = "LS1043A RDB Board";
2857 compatible = "pericom,pt7c4338";
2861 + compatible = "nxp,pcf85263";
2869 spi-max-frequency = <1000000>; /* input clock */
2873 + compatible = "maxim,ds26522";
2875 + spi-max-frequency = <2000000>;
2876 + fsl,spi-cs-sck-delay = <100>;
2877 + fsl,spi-sck-cs-delay = <50>;
2881 + compatible = "maxim,ds26522";
2883 + spi-max-frequency = <2000000>;
2884 + fsl,spi-cs-sck-delay = <100>;
2885 + fsl,spi-sck-cs-delay = <50>;
2890 + ucc_hdlc: ucc@2000 {
2891 + compatible = "fsl,ucc-hdlc";
2892 + rx-clock-name = "clk8";
2893 + tx-clock-name = "clk9";
2894 + fsl,rx-sync-clock = "rsync_pin";
2895 + fsl,tx-sync-clock = "tsync_pin";
2896 + fsl,tx-timeslot-mask = <0xfffffffe>;
2897 + fsl,rx-timeslot-mask = <0xfffffffe>;
2898 + fsl,tdm-framer-type = "e1";
2900 + fsl,siram-entry-id = <0>;
2901 + fsl,tdm-interface;
2906 @@ -139,3 +138,76 @@
2911 +#include "fsl-ls1043-post.dtsi"
2915 + phy-handle = <&qsgmii_phy1>;
2916 + phy-connection-type = "qsgmii";
2920 + phy-handle = <&qsgmii_phy2>;
2921 + phy-connection-type = "qsgmii";
2925 + phy-handle = <&rgmii_phy1>;
2926 + phy-connection-type = "rgmii-txid";
2930 + phy-handle = <&rgmii_phy2>;
2931 + phy-connection-type = "rgmii-txid";
2935 + phy-handle = <&qsgmii_phy3>;
2936 + phy-connection-type = "qsgmii";
2940 + phy-handle = <&qsgmii_phy4>;
2941 + phy-connection-type = "qsgmii";
2944 + ethernet@f0000 { /* 10GEC1 */
2945 + phy-handle = <&aqr105_phy>;
2946 + phy-connection-type = "xgmii";
2950 + rgmii_phy1: ethernet-phy@1 {
2954 + rgmii_phy2: ethernet-phy@2 {
2958 + qsgmii_phy1: ethernet-phy@4 {
2962 + qsgmii_phy2: ethernet-phy@5 {
2966 + qsgmii_phy3: ethernet-phy@6 {
2970 + qsgmii_phy4: ethernet-phy@7 {
2976 + aqr105_phy: ethernet-phy@1 {
2977 + compatible = "ethernet-phy-ieee802.3-c45";
2978 + interrupts = <0 132 4>;
2983 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2984 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2986 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2988 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2990 - * Copyright 2014-2015, Freescale Semiconductor
2991 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2993 * Mingkai Hu <Mingkai.hu@freescale.com>
2995 - * This file is dual-licensed: you can use it either under the terms
2996 - * of the GPLv2 or the X11 license, at your option. Note that this dual
2997 - * licensing only applies to this file, and not this project as a
3000 - * a) This library is free software; you can redistribute it and/or
3001 - * modify it under the terms of the GNU General Public License as
3002 - * published by the Free Software Foundation; either version 2 of the
3003 - * License, or (at your option) any later version.
3005 - * This library is distributed in the hope that it will be useful,
3006 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
3007 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3008 - * GNU General Public License for more details.
3010 - * Or, alternatively,
3012 - * b) Permission is hereby granted, free of charge, to any person
3013 - * obtaining a copy of this software and associated documentation
3014 - * files (the "Software"), to deal in the Software without
3015 - * restriction, including without limitation the rights to use,
3016 - * copy, modify, merge, publish, distribute, sublicense, and/or
3017 - * sell copies of the Software, and to permit persons to whom the
3018 - * Software is furnished to do so, subject to the following
3021 - * The above copyright notice and this permission notice shall be
3022 - * included in all copies or substantial portions of the Software.
3024 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3025 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3026 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3027 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3028 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3029 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3030 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3031 - * OTHER DEALINGS IN THE SOFTWARE.
3034 +#include <dt-bindings/thermal/thermal.h>
3035 +#include <dt-bindings/interrupt-controller/arm-gic.h>
3038 compatible = "fsl,ls1043a";
3039 interrupt-parent = <&gic>;
3040 #address-cells = <2>;
3045 + ethernet0 = &enet0;
3046 + ethernet1 = &enet1;
3047 + ethernet2 = &enet2;
3048 + ethernet3 = &enet3;
3049 + ethernet4 = &enet4;
3050 + ethernet5 = &enet5;
3051 + ethernet6 = &enet6;
3055 #address-cells = <1>;
3059 clocks = <&clockgen 1 0>;
3060 next-level-cache = <&l2>;
3061 + #cooling-cells = <2>;
3062 + cpu-idle-states = <&CPU_PH20>;
3068 clocks = <&clockgen 1 0>;
3069 next-level-cache = <&l2>;
3070 + cpu-idle-states = <&CPU_PH20>;
3076 clocks = <&clockgen 1 0>;
3077 next-level-cache = <&l2>;
3078 + cpu-idle-states = <&CPU_PH20>;
3084 clocks = <&clockgen 1 0>;
3085 next-level-cache = <&l2>;
3086 + cpu-idle-states = <&CPU_PH20>;
3096 + * PSCI node is not added default, U-boot will add missing
3097 + * parts if it determines to use PSCI.
3099 + entry-method = "arm,psci";
3101 + CPU_PH20: cpu-ph20 {
3102 + compatible = "arm,idle-state";
3103 + idle-state-name = "PH20";
3104 + arm,psci-suspend-param = <0x0>;
3105 + entry-latency-us = <1000>;
3106 + exit-latency-us = <1000>;
3107 + min-residency-us = <3000>;
3112 device_type = "memory";
3113 reg = <0x0 0x80000000 0 0x80000000>;
3114 /* DRAM space 1, size: 2GiB DRAM */
3118 + #address-cells = <2>;
3119 + #size-cells = <2>;
3122 + bman_fbpr: bman-fbpr {
3123 + compatible = "shared-dma-pool";
3124 + size = <0 0x1000000>;
3125 + alignment = <0 0x1000000>;
3129 + qman_fqd: qman-fqd {
3130 + compatible = "shared-dma-pool";
3131 + size = <0 0x400000>;
3132 + alignment = <0 0x400000>;
3136 + qman_pfdr: qman-pfdr {
3137 + compatible = "shared-dma-pool";
3138 + size = <0 0x2000000>;
3139 + alignment = <0 0x2000000>;
3145 compatible = "fixed-clock";
3148 interrupts = <1 9 0xf08>;
3153 compatible = "simple-bus";
3154 #address-cells = <2>;
3156 @@ -213,13 +239,14 @@
3158 dcfg: dcfg@1ee0000 {
3159 compatible = "fsl,ls1043a-dcfg", "syscon";
3160 - reg = <0x0 0x1ee0000 0x0 0x10000>;
3161 + reg = <0x0 0x1ee0000 0x0 0x1000>;
3166 compatible = "fsl,ifc", "simple-bus";
3167 reg = <0x0 0x1530000 0x0 0x10000>;
3169 interrupts = <0 43 0x4>;
3172 @@ -255,6 +282,103 @@
3176 + tmu: tmu@1f00000 {
3177 + compatible = "fsl,qoriq-tmu";
3178 + reg = <0x0 0x1f00000 0x0 0x10000>;
3179 + interrupts = <0 33 0x4>;
3180 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
3181 + fsl,tmu-calibration = <0x00000000 0x00000026
3182 + 0x00000001 0x0000002d
3183 + 0x00000002 0x00000032
3184 + 0x00000003 0x00000039
3185 + 0x00000004 0x0000003f
3186 + 0x00000005 0x00000046
3187 + 0x00000006 0x0000004d
3188 + 0x00000007 0x00000054
3189 + 0x00000008 0x0000005a
3190 + 0x00000009 0x00000061
3191 + 0x0000000a 0x0000006a
3192 + 0x0000000b 0x00000071
3194 + 0x00010000 0x00000025
3195 + 0x00010001 0x0000002c
3196 + 0x00010002 0x00000035
3197 + 0x00010003 0x0000003d
3198 + 0x00010004 0x00000045
3199 + 0x00010005 0x0000004e
3200 + 0x00010006 0x00000057
3201 + 0x00010007 0x00000061
3202 + 0x00010008 0x0000006b
3203 + 0x00010009 0x00000076
3205 + 0x00020000 0x00000029
3206 + 0x00020001 0x00000033
3207 + 0x00020002 0x0000003d
3208 + 0x00020003 0x00000049
3209 + 0x00020004 0x00000056
3210 + 0x00020005 0x00000061
3211 + 0x00020006 0x0000006d
3213 + 0x00030000 0x00000021
3214 + 0x00030001 0x0000002a
3215 + 0x00030002 0x0000003c
3216 + 0x00030003 0x0000004e>;
3217 + #thermal-sensor-cells = <1>;
3221 + cpu_thermal: cpu-thermal {
3222 + polling-delay-passive = <1000>;
3223 + polling-delay = <5000>;
3225 + thermal-sensors = <&tmu 3>;
3228 + cpu_alert: cpu-alert {
3229 + temperature = <85000>;
3230 + hysteresis = <2000>;
3233 + cpu_crit: cpu-crit {
3234 + temperature = <95000>;
3235 + hysteresis = <2000>;
3236 + type = "critical";
3242 + trip = <&cpu_alert>;
3244 + <&cpu0 THERMAL_NO_LIMIT
3245 + THERMAL_NO_LIMIT>;
3251 + qman: qman@1880000 {
3252 + compatible = "fsl,qman";
3253 + reg = <0x00 0x1880000 0x0 0x10000>;
3254 + interrupts = <0 45 0x4>;
3255 + memory-region = <&qman_fqd &qman_pfdr>;
3258 + bman: bman@1890000 {
3259 + compatible = "fsl,bman";
3260 + reg = <0x00 0x1890000 0x0 0x10000>;
3261 + interrupts = <0 45 0x4>;
3262 + memory-region = <&bman_fbpr>;
3265 + bportals: bman-portals@508000000 {
3266 + ranges = <0x0 0x5 0x08000000 0x8000000>;
3269 + qportals: qman-portals@500000000 {
3270 + ranges = <0x0 0x5 0x00000000 0x8000000>;
3273 dspi0: dspi@2100000 {
3274 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
3275 #address-cells = <1>;
3280 - compatible = "fsl,vf610-i2c";
3281 + compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
3282 #address-cells = <1>;
3284 reg = <0x0 0x2180000 0x0 0x10000>;
3286 dmas = <&edma0 1 39>,
3288 dma-names = "tx", "rx";
3289 + fsl-scl-gpio = <&gpio4 12 0>;
3290 status = "disabled";
3293 @@ -396,6 +521,72 @@
3294 #interrupt-cells = <2>;
3297 + uqe: uqe@2400000 {
3298 + #address-cells = <1>;
3299 + #size-cells = <1>;
3300 + device_type = "qe";
3301 + compatible = "fsl,qe", "simple-bus";
3302 + ranges = <0x0 0x0 0x2400000 0x40000>;
3303 + reg = <0x0 0x2400000 0x0 0x480>;
3304 + brg-frequency = <100000000>;
3305 + bus-frequency = <200000000>;
3307 + fsl,qe-num-riscs = <1>;
3308 + fsl,qe-num-snums = <28>;
3311 + compatible = "fsl,qe-ic";
3312 + reg = <0x80 0x80>;
3313 + #address-cells = <0>;
3314 + interrupt-controller;
3315 + #interrupt-cells = <1>;
3316 + interrupts = <0 77 0x04 0 77 0x04>;
3320 + #address-cells = <1>;
3321 + #size-cells = <0>;
3322 + compatible = "fsl,ls1043-qe-si",
3323 + "fsl,t1040-qe-si";
3324 + reg = <0x700 0x80>;
3327 + siram1: siram@1000 {
3328 + #address-cells = <1>;
3329 + #size-cells = <1>;
3330 + compatible = "fsl,ls1043-qe-siram",
3331 + "fsl,t1040-qe-siram";
3332 + reg = <0x1000 0x800>;
3337 + reg = <0x2000 0x200>;
3338 + interrupts = <32>;
3339 + interrupt-parent = <&qeic>;
3344 + reg = <0x2200 0x200>;
3345 + interrupts = <34>;
3346 + interrupt-parent = <&qeic>;
3350 + #address-cells = <1>;
3351 + #size-cells = <1>;
3352 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
3353 + ranges = <0x0 0x10000 0x6000>;
3356 + compatible = "fsl,qe-muram-data",
3357 + "fsl,cpm-muram-data";
3358 + reg = <0x0 0x6000>;
3363 lpuart0: serial@2950000 {
3364 compatible = "fsl,ls1021a-lpuart";
3365 reg = <0x0 0x2950000 0x0 0x1000>;
3366 @@ -450,6 +641,16 @@
3367 status = "disabled";
3370 + ftm0: ftm0@29d0000 {
3371 + compatible = "fsl,ls1043a-ftm";
3372 + reg = <0x0 0x29d0000 0x0 0x10000>,
3373 + <0x0 0x1ee2140 0x0 0x4>;
3374 + reg-names = "ftm", "FlexTimer1";
3375 + interrupts = <0 86 0x4>;
3380 wdog0: wdog@2ad0000 {
3381 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
3382 reg = <0x0 0x2ad0000 0x0 0x10000>;
3383 @@ -482,6 +683,10 @@
3385 snps,quirk-frame-length-adjustment = <0x20>;
3386 snps,dis_rxdet_inp3_quirk;
3387 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3388 + snps,dma-snooping;
3390 + snps,dis-u1u2-when-u3-quirk;
3393 usb1: usb3@3000000 {
3394 @@ -491,6 +696,11 @@
3396 snps,quirk-frame-length-adjustment = <0x20>;
3397 snps,dis_rxdet_inp3_quirk;
3398 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3399 + snps,dma-snooping;
3402 + snps,dis-u1u2-when-u3-quirk;
3405 usb2: usb3@3100000 {
3406 @@ -500,32 +710,54 @@
3408 snps,quirk-frame-length-adjustment = <0x20>;
3409 snps,dis_rxdet_inp3_quirk;
3410 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
3411 + snps,dma-snooping;
3414 + snps,dis-u1u2-when-u3-quirk;
3417 sata: sata@3200000 {
3418 compatible = "fsl,ls1043a-ahci";
3419 - reg = <0x0 0x3200000 0x0 0x10000>;
3420 + reg = <0x0 0x3200000 0x0 0x10000>,
3421 + <0x0 0x20140520 0x0 0x4>;
3422 + reg-names = "ahci", "sata-ecc";
3423 interrupts = <0 69 0x4>;
3424 clocks = <&clockgen 4 0>;
3428 + qdma: qdma@8380000 {
3429 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
3430 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
3431 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
3432 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
3433 + interrupts = <0 152 0x4>,
3435 + interrupt-names = "qdma-error", "qdma-queue";
3438 + status-sizes = <64>;
3439 + queue-sizes = <64 64>;
3443 msi1: msi-controller1@1571000 {
3444 - compatible = "fsl,1s1043a-msi";
3445 + compatible = "fsl,ls1043a-msi";
3446 reg = <0x0 0x1571000 0x0 0x8>;
3448 interrupts = <0 116 0x4>;
3451 msi2: msi-controller2@1572000 {
3452 - compatible = "fsl,1s1043a-msi";
3453 + compatible = "fsl,ls1043a-msi";
3454 reg = <0x0 0x1572000 0x0 0x8>;
3456 interrupts = <0 126 0x4>;
3459 msi3: msi-controller3@1573000 {
3460 - compatible = "fsl,1s1043a-msi";
3461 + compatible = "fsl,ls1043a-msi";
3462 reg = <0x0 0x1573000 0x0 0x8>;
3464 interrupts = <0 160 0x4>;
3466 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
3467 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
3468 reg-names = "regs", "config";
3469 - interrupts = <0 118 0x4>, /* controller interrupt */
3470 - <0 117 0x4>; /* PME interrupt */
3471 - interrupt-names = "intr", "pme";
3472 + interrupts = <0 117 0x4>, /* PME interrupt */
3473 + <0 118 0x4>; /* aer interrupt */
3474 + interrupt-names = "pme", "aer";
3475 #address-cells = <3>;
3477 device_type = "pci";
3479 bus-range = <0x0 0xff>;
3480 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
3481 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3482 - msi-parent = <&msi1>;
3483 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3484 #interrupt-cells = <1>;
3485 interrupt-map-mask = <0 0 0 7>;
3486 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
3488 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
3489 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
3490 reg-names = "regs", "config";
3491 - interrupts = <0 128 0x4>,
3493 - interrupt-names = "intr", "pme";
3494 + interrupts = <0 127 0x4>,
3496 + interrupt-names = "pme", "aer";
3497 #address-cells = <3>;
3499 device_type = "pci";
3501 bus-range = <0x0 0xff>;
3502 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
3503 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3504 - msi-parent = <&msi2>;
3505 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3506 #interrupt-cells = <1>;
3507 interrupt-map-mask = <0 0 0 7>;
3508 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
3510 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
3511 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
3512 reg-names = "regs", "config";
3513 - interrupts = <0 162 0x4>,
3515 - interrupt-names = "intr", "pme";
3516 + interrupts = <0 161 0x4>,
3518 + interrupt-names = "pme", "aer";
3519 #address-cells = <3>;
3521 device_type = "pci";
3523 bus-range = <0x0 0xff>;
3524 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3525 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3526 - msi-parent = <&msi3>;
3527 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3528 #interrupt-cells = <1>;
3529 interrupt-map-mask = <0 0 0 7>;
3530 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3531 @@ -607,4 +839,13 @@
3537 + compatible = "linaro,optee-tz";
3543 +#include "qoriq-qman-portals.dtsi"
3544 +#include "qoriq-bman-portals.dtsi"
3546 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3548 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3550 + * QorIQ FMan v3 device tree nodes for ls1046
3552 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3558 +/* include used FMan blocks */
3559 +#include "qoriq-fman3-0.dtsi"
3560 +#include "qoriq-fman3-0-1g-0.dtsi"
3561 +#include "qoriq-fman3-0-1g-1.dtsi"
3562 +#include "qoriq-fman3-0-1g-2.dtsi"
3563 +#include "qoriq-fman3-0-1g-3.dtsi"
3564 +#include "qoriq-fman3-0-1g-4.dtsi"
3565 +#include "qoriq-fman3-0-1g-5.dtsi"
3566 +#include "qoriq-fman3-0-10g-0.dtsi"
3567 +#include "qoriq-fman3-0-10g-1.dtsi"
3571 + /* these aliases provide the FMan ports mapping */
3572 + enet0: ethernet@e0000 {
3575 + enet1: ethernet@e2000 {
3578 + enet2: ethernet@e4000 {
3581 + enet3: ethernet@e6000 {
3584 + enet4: ethernet@e8000 {
3587 + enet5: ethernet@ea000 {
3590 + enet6: ethernet@f0000 {
3593 + enet7: ethernet@f2000 {
3597 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3600 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3602 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3604 + * Mingkai Hu <Mingkai.hu@freescale.com>
3606 + * This file is dual-licensed: you can use it either under the terms
3607 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3608 + * licensing only applies to this file, and not this project as a
3611 + * a) This library is free software; you can redistribute it and/or
3612 + * modify it under the terms of the GNU General Public License as
3613 + * published by the Free Software Foundation; either version 2 of the
3614 + * License, or (at your option) any later version.
3616 + * This library is distributed in the hope that it will be useful,
3617 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3618 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3619 + * GNU General Public License for more details.
3621 + * Or, alternatively,
3623 + * b) Permission is hereby granted, free of charge, to any person
3624 + * obtaining a copy of this software and associated documentation
3625 + * files (the "Software"), to deal in the Software without
3626 + * restriction, including without limitation the rights to use,
3627 + * copy, modify, merge, publish, distribute, sublicense, and/or
3628 + * sell copies of the Software, and to permit persons to whom the
3629 + * Software is furnished to do so, subject to the following
3632 + * The above copyright notice and this permission notice shall be
3633 + * included in all copies or substantial portions of the Software.
3635 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3636 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3637 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3638 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3639 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3640 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3641 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3642 + * OTHER DEALINGS IN THE SOFTWARE.
3645 +#include "fsl-ls1046a-qds.dts"
3646 +#include "qoriq-qman-portals-sdk.dtsi"
3647 +#include "qoriq-bman-portals-sdk.dtsi"
3650 + compatible = "fsl,bman-fbpr";
3651 + alloc-ranges = <0 0 0x10000 0>;
3654 + compatible = "fsl,qman-fqd";
3655 + alloc-ranges = <0 0 0x10000 0>;
3658 + compatible = "fsl,qman-pfdr";
3659 + alloc-ranges = <0 0 0x10000 0>;
3663 +#include "qoriq-dpaa-eth.dtsi"
3664 +#include "qoriq-fman3-0-6oh.dtsi"
3669 + compatible = "fsl,dpa-ethernet";
3670 + fsl,fman-mac = <&enet7>;
3676 + compatible = "fsl,fman", "simple-bus";
3684 + #address-cells = <1>;
3685 + #size-cells = <1>;
3686 + compatible = "n25q128a11", "jedec,spi-nor";
3688 + spi-max-frequency = <10000000>;
3692 + #address-cells = <1>;
3693 + #size-cells = <1>;
3694 + compatible = "sst25wf040b", "jedec,spi-nor";
3698 + spi-max-frequency = <10000000>;
3702 + #address-cells = <1>;
3703 + #size-cells = <1>;
3704 + compatible = "en25s64", "jedec,spi-nor";
3708 + spi-max-frequency = <10000000>;
3712 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3714 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3716 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3718 + * Copyright 2016 Freescale Semiconductor, Inc.
3720 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3725 +#include "fsl-ls1046a.dtsi"
3728 + model = "LS1046A QDS Board";
3729 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3736 + serial0 = &duart0;
3737 + serial1 = &duart1;
3738 + serial2 = &duart2;
3739 + serial3 = &duart3;
3741 + emi1_slot1 = &ls1046mdio_s1;
3742 + emi1_slot2 = &ls1046mdio_s2;
3743 + emi1_slot4 = &ls1046mdio_s4;
3745 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3746 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3747 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3748 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3749 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3750 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3751 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3752 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3753 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3757 + stdout-path = "serial0:115200n8";
3766 + #address-cells = <1>;
3767 + #size-cells = <1>;
3768 + compatible = "n25q128a11", "jedec,spi-nor";
3770 + spi-max-frequency = <10000000>;
3774 + #address-cells = <1>;
3775 + #size-cells = <1>;
3776 + compatible = "sst25wf040b", "jedec,spi-nor";
3780 + spi-max-frequency = <10000000>;
3784 + #address-cells = <1>;
3785 + #size-cells = <1>;
3786 + compatible = "en25s64", "jedec,spi-nor";
3790 + spi-max-frequency = <10000000>;
3806 + compatible = "nxp,pca9547";
3808 + #address-cells = <1>;
3809 + #size-cells = <0>;
3812 + #address-cells = <1>;
3813 + #size-cells = <0>;
3817 + compatible = "ti,ina220";
3819 + shunt-resistor = <1000>;
3823 + compatible = "ti,ina220";
3825 + shunt-resistor = <1000>;
3830 + #address-cells = <1>;
3831 + #size-cells = <0>;
3835 + compatible = "nxp,pcf2129";
3838 + interrupts = <0 150 0x4>;
3842 + compatible = "atmel,24c512";
3847 + compatible = "atmel,24c512";
3852 + compatible = "adi,adt7461a";
3860 + #address-cells = <2>;
3861 + #size-cells = <1>;
3862 + /* NOR, NAND Flashes and FPGA on board */
3863 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3864 + 0x1 0x0 0x0 0x7e800000 0x00010000
3865 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3869 + compatible = "cfi-flash";
3870 + reg = <0x0 0x0 0x8000000>;
3872 + device-width = <1>;
3876 + compatible = "fsl,ifc-nand";
3877 + reg = <0x1 0x0 0x10000>;
3880 + fpga: board-control@2,0 {
3881 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3882 + reg = <0x2 0x0 0x0000100>;
3883 + ranges = <0 2 0 0x100>;
3896 + qflash0: s25fl128s@0 {
3897 + compatible = "spansion,m25p80";
3898 + #address-cells = <1>;
3899 + #size-cells = <1>;
3900 + spi-max-frequency = <20000000>;
3905 +#include "fsl-ls1046-post.dtsi"
3909 + phy-handle = <&qsgmii_phy_s2_p1>;
3910 + phy-connection-type = "sgmii";
3914 + phy-handle = <&sgmii_phy_s4_p1>;
3915 + phy-connection-type = "sgmii";
3919 + phy-handle = <&rgmii_phy1>;
3920 + phy-connection-type = "rgmii";
3924 + phy-handle = <&rgmii_phy2>;
3925 + phy-connection-type = "rgmii";
3929 + phy-handle = <&sgmii_phy_s1_p3>;
3930 + phy-connection-type = "sgmii";
3934 + phy-handle = <&sgmii_phy_s1_p4>;
3935 + phy-connection-type = "sgmii";
3938 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3939 + phy-handle = <&sgmii_phy_s1_p1>;
3940 + phy-connection-type = "xgmii";
3943 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3944 + phy-handle = <&sgmii_phy_s1_p2>;
3945 + phy-connection-type = "xgmii";
3950 + #address-cells = <1>;
3951 + #size-cells = <1>;
3953 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3954 + mdio-parent-bus = <&mdio0>;
3955 + #address-cells = <1>;
3956 + #size-cells = <0>;
3957 + reg = <0x54 1>; /* BRDCFG4 */
3958 + mux-mask = <0xe0>; /* EMI1 */
3960 + /* On-board RGMII1 PHY */
3961 + ls1046mdio0: mdio@0 {
3963 + #address-cells = <1>;
3964 + #size-cells = <0>;
3966 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3971 + /* On-board RGMII2 PHY */
3972 + ls1046mdio1: mdio@1 {
3974 + #address-cells = <1>;
3975 + #size-cells = <0>;
3977 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3983 + ls1046mdio_s1: mdio@2 {
3985 + #address-cells = <1>;
3986 + #size-cells = <0>;
3987 + status = "disabled";
3989 + sgmii_phy_s1_p1: ethernet-phy@1c {
3993 + sgmii_phy_s1_p2: ethernet-phy@1d {
3997 + sgmii_phy_s1_p3: ethernet-phy@1e {
4001 + sgmii_phy_s1_p4: ethernet-phy@1f {
4007 + ls1046mdio_s2: mdio@3 {
4009 + #address-cells = <1>;
4010 + #size-cells = <0>;
4011 + status = "disabled";
4013 + qsgmii_phy_s2_p1: ethernet-phy@8 {
4016 + qsgmii_phy_s2_p2: ethernet-phy@9 {
4019 + qsgmii_phy_s2_p3: ethernet-phy@a {
4022 + qsgmii_phy_s2_p4: ethernet-phy@b {
4028 + ls1046mdio_s4: mdio@5 {
4030 + #address-cells = <1>;
4031 + #size-cells = <0>;
4032 + status = "disabled";
4034 + sgmii_phy_s4_p1: ethernet-phy@1c {
4041 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
4044 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4046 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
4048 + * Mingkai Hu <Mingkai.hu@freescale.com>
4050 + * This file is dual-licensed: you can use it either under the terms
4051 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4052 + * licensing only applies to this file, and not this project as a
4055 + * a) This library is free software; you can redistribute it and/or
4056 + * modify it under the terms of the GNU General Public License as
4057 + * published by the Free Software Foundation; either version 2 of the
4058 + * License, or (at your option) any later version.
4060 + * This library is distributed in the hope that it will be useful,
4061 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4062 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4063 + * GNU General Public License for more details.
4065 + * Or, alternatively,
4067 + * b) Permission is hereby granted, free of charge, to any person
4068 + * obtaining a copy of this software and associated documentation
4069 + * files (the "Software"), to deal in the Software without
4070 + * restriction, including without limitation the rights to use,
4071 + * copy, modify, merge, publish, distribute, sublicense, and/or
4072 + * sell copies of the Software, and to permit persons to whom the
4073 + * Software is furnished to do so, subject to the following
4076 + * The above copyright notice and this permission notice shall be
4077 + * included in all copies or substantial portions of the Software.
4079 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4080 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4081 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4082 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4083 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4084 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4085 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4086 + * OTHER DEALINGS IN THE SOFTWARE.
4089 +#include "fsl-ls1046a-rdb.dts"
4090 +#include "qoriq-qman-portals-sdk.dtsi"
4091 +#include "qoriq-bman-portals-sdk.dtsi"
4094 + compatible = "fsl,bman-fbpr";
4095 + alloc-ranges = <0 0 0x10000 0>;
4098 + compatible = "fsl,qman-fqd";
4099 + alloc-ranges = <0 0 0x10000 0>;
4102 + compatible = "fsl,qman-pfdr";
4103 + alloc-ranges = <0 0 0x10000 0>;
4107 +#include "qoriq-dpaa-eth.dtsi"
4108 +#include "qoriq-fman3-0-6oh.dtsi"
4113 + status = "disabled";
4116 + status = "disabled";
4119 + compatible = "fsl,dpa-ethernet";
4120 + fsl,fman-mac = <&enet7>;
4126 + compatible = "fsl,fman", "simple-bus";
4129 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
4132 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4134 + * Copyright 2016 Freescale Semiconductor, Inc.
4136 + * This file is licensed under the terms of the GNU General Public
4137 + * License version 2. This program is licensed "as is" without any
4138 + * warranty of any kind, whether express or implied.
4141 +#include "fsl-ls1046a-rdb-sdk.dts"
4144 + bp7: buffer-pool@7 {
4145 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
4147 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
4148 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
4151 + bp8: buffer-pool@8 {
4152 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
4154 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
4155 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
4158 + bp9: buffer-pool@9 {
4159 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
4161 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
4162 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
4166 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
4169 + compatible = "fsl,dpa-ethernet-init";
4170 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4171 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
4172 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
4176 + compatible = "fsl,dpa-ethernet-init";
4177 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4178 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
4179 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
4183 + compatible = "fsl,dpa-ethernet-init";
4184 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4185 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
4186 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
4190 + compatible = "fsl,dpa-ethernet-init";
4191 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4192 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
4193 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
4197 + compatible = "fsl,dpa-ethernet-init";
4198 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4199 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
4200 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
4204 + compatible = "fsl,dpa-ethernet-init";
4205 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
4206 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
4207 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
4211 + compatible = "fsl,dpa-oh";
4212 + /* Define frame queues for the OH port*/
4213 + /* <OH Rx error, OH Rx default> */
4214 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
4215 + fsl,fman-oh-port = <&fman0_oh2>;
4221 + #address-cells = <2>;
4222 + #size-cells = <2>;
4225 + usdpaa_mem: usdpaa_mem {
4226 + compatible = "fsl,usdpaa-mem";
4227 + alloc-ranges = <0 0 0x10000 0>;
4228 + size = <0 0x10000000>;
4229 + alignment = <0 0x10000000>;
4235 + fman0_oh2: port@83000 {
4237 + compatible = "fsl,fman-port-oh";
4238 + reg = <0x83000 0x1000>;
4242 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
4244 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4246 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4248 + * Copyright 2016 Freescale Semiconductor, Inc.
4250 + * Mingkai Hu <mingkai.hu@nxp.com>
4255 +#include "fsl-ls1046a.dtsi"
4258 + model = "LS1046A RDB Board";
4259 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
4262 + serial0 = &duart0;
4263 + serial1 = &duart1;
4264 + serial2 = &duart2;
4265 + serial3 = &duart3;
4269 + stdout-path = "serial0:115200n8";
4293 + compatible = "ti,ina220";
4295 + shunt-resistor = <1000>;
4299 + compatible = "adi,adt7461";
4304 + compatible = "atmel,24c512";
4309 + compatible = "atmel,24c512";
4318 + compatible = "nxp,pcf2129";
4324 + #address-cells = <2>;
4325 + #size-cells = <1>;
4326 + /* NAND Flashe and CPLD on board */
4327 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
4328 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
4332 + compatible = "fsl,ifc-nand";
4333 + #address-cells = <1>;
4334 + #size-cells = <1>;
4335 + reg = <0x0 0x0 0x10000>;
4338 + cpld: board-control@2,0 {
4339 + compatible = "fsl,ls1046ardb-cpld";
4340 + reg = <0x2 0x0 0x0000100>;
4349 + qflash0: s25fs512s@0 {
4350 + compatible = "spansion,m25p80";
4351 + #address-cells = <1>;
4352 + #size-cells = <1>;
4353 + spi-max-frequency = <20000000>;
4357 + qflash1: s25fs512s@1 {
4358 + compatible = "spansion,m25p80";
4359 + #address-cells = <1>;
4360 + #size-cells = <1>;
4361 + spi-max-frequency = <20000000>;
4366 +#include "fsl-ls1046-post.dtsi"
4370 + phy-handle = <&rgmii_phy1>;
4371 + phy-connection-type = "rgmii";
4375 + phy-handle = <&rgmii_phy2>;
4376 + phy-connection-type = "rgmii";
4380 + phy-handle = <&sgmii_phy1>;
4381 + phy-connection-type = "sgmii";
4385 + phy-handle = <&sgmii_phy2>;
4386 + phy-connection-type = "sgmii";
4389 + ethernet@f0000 { /* 10GEC1 */
4390 + phy-handle = <&aqr106_phy>;
4391 + phy-connection-type = "xgmii";
4394 + ethernet@f2000 { /* 10GEC2 */
4395 + fixed-link = <0 1 1000 0 0>;
4396 + phy-connection-type = "xgmii";
4400 + rgmii_phy1: ethernet-phy@1 {
4404 + rgmii_phy2: ethernet-phy@2 {
4408 + sgmii_phy1: ethernet-phy@3 {
4412 + sgmii_phy2: ethernet-phy@4 {
4418 + aqr106_phy: ethernet-phy@0 {
4419 + compatible = "ethernet-phy-ieee802.3-c45";
4420 + interrupts = <0 131 4>;
4426 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
4428 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4430 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4432 + * Copyright 2016 Freescale Semiconductor, Inc.
4434 + * Mingkai Hu <mingkai.hu@nxp.com>
4437 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4438 +#include <dt-bindings/thermal/thermal.h>
4441 + compatible = "fsl,ls1046a";
4442 + interrupt-parent = <&gic>;
4443 + #address-cells = <2>;
4444 + #size-cells = <2>;
4449 + ethernet0 = &enet0;
4450 + ethernet1 = &enet1;
4451 + ethernet2 = &enet2;
4452 + ethernet3 = &enet3;
4453 + ethernet4 = &enet4;
4454 + ethernet5 = &enet5;
4455 + ethernet6 = &enet6;
4456 + ethernet7 = &enet7;
4460 + #address-cells = <1>;
4461 + #size-cells = <0>;
4464 + device_type = "cpu";
4465 + compatible = "arm,cortex-a72";
4467 + clocks = <&clockgen 1 0>;
4468 + next-level-cache = <&l2>;
4469 + cpu-idle-states = <&CPU_PH20>;
4470 + #cooling-cells = <2>;
4474 + device_type = "cpu";
4475 + compatible = "arm,cortex-a72";
4477 + clocks = <&clockgen 1 0>;
4478 + next-level-cache = <&l2>;
4479 + cpu-idle-states = <&CPU_PH20>;
4483 + device_type = "cpu";
4484 + compatible = "arm,cortex-a72";
4486 + clocks = <&clockgen 1 0>;
4487 + next-level-cache = <&l2>;
4488 + cpu-idle-states = <&CPU_PH20>;
4492 + device_type = "cpu";
4493 + compatible = "arm,cortex-a72";
4495 + clocks = <&clockgen 1 0>;
4496 + next-level-cache = <&l2>;
4497 + cpu-idle-states = <&CPU_PH20>;
4501 + compatible = "cache";
4507 + * PSCI node is not added default, U-boot will add missing
4508 + * parts if it determines to use PSCI.
4510 + entry-method = "arm,psci";
4512 + CPU_PH20: cpu-ph20 {
4513 + compatible = "arm,idle-state";
4514 + idle-state-name = "PH20";
4515 + arm,psci-suspend-param = <0x0>;
4516 + entry-latency-us = <1000>;
4517 + exit-latency-us = <1000>;
4518 + min-residency-us = <3000>;
4523 + device_type = "memory";
4527 + compatible = "fixed-clock";
4528 + #clock-cells = <0>;
4529 + clock-frequency = <100000000>;
4530 + clock-output-names = "sysclk";
4534 + compatible ="syscon-reboot";
4541 + compatible = "arm,armv8-timer";
4542 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
4543 + IRQ_TYPE_LEVEL_LOW)>,
4544 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
4545 + IRQ_TYPE_LEVEL_LOW)>,
4546 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
4547 + IRQ_TYPE_LEVEL_LOW)>,
4548 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4549 + IRQ_TYPE_LEVEL_LOW)>;
4553 + compatible = "arm,cortex-a72-pmu";
4554 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4555 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4556 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4557 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4558 + interrupt-affinity = <&cpu0>,
4564 + gic: interrupt-controller@1400000 {
4565 + compatible = "arm,gic-400";
4566 + #interrupt-cells = <3>;
4567 + interrupt-controller;
4568 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4569 + <0x0 0x1420000 0 0x20000>, /* GICC */
4570 + <0x0 0x1440000 0 0x20000>, /* GICH */
4571 + <0x0 0x1460000 0 0x20000>; /* GICV */
4572 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4573 + IRQ_TYPE_LEVEL_LOW)>;
4577 + compatible = "simple-bus";
4578 + #address-cells = <2>;
4579 + #size-cells = <2>;
4582 + ddr: memory-controller@1080000 {
4583 + compatible = "fsl,qoriq-memory-controller";
4584 + reg = <0x0 0x1080000 0x0 0x1000>;
4585 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4589 + ifc: ifc@1530000 {
4590 + compatible = "fsl,ifc", "simple-bus";
4591 + reg = <0x0 0x1530000 0x0 0x10000>;
4593 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4596 + qspi: quadspi@1550000 {
4597 + compatible = "fsl,ls1021a-qspi";
4598 + #address-cells = <1>;
4599 + #size-cells = <0>;
4600 + reg = <0x0 0x1550000 0x0 0x10000>,
4601 + <0x0 0x40000000 0x0 0x10000000>;
4602 + reg-names = "QuadSPI", "QuadSPI-memory";
4603 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4604 + clock-names = "qspi_en", "qspi";
4605 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4607 + fsl,qspi-has-second-chip;
4608 + status = "disabled";
4611 + esdhc: esdhc@1560000 {
4612 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4613 + reg = <0x0 0x1560000 0x0 0x10000>;
4614 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4615 + clocks = <&clockgen 2 1>;
4616 + voltage-ranges = <1800 1800 3300 3300>;
4622 + scfg: scfg@1570000 {
4623 + compatible = "fsl,ls1046a-scfg", "syscon";
4624 + reg = <0x0 0x1570000 0x0 0x10000>;
4628 + crypto: crypto@1700000 {
4629 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4631 + fsl,sec-era = <8>;
4632 + #address-cells = <1>;
4633 + #size-cells = <1>;
4634 + ranges = <0x0 0x00 0x1700000 0x100000>;
4635 + reg = <0x00 0x1700000 0x0 0x100000>;
4636 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4638 + sec_jr0: jr@10000 {
4639 + compatible = "fsl,sec-v5.4-job-ring",
4640 + "fsl,sec-v5.0-job-ring",
4641 + "fsl,sec-v4.0-job-ring";
4642 + reg = <0x10000 0x10000>;
4643 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4646 + sec_jr1: jr@20000 {
4647 + compatible = "fsl,sec-v5.4-job-ring",
4648 + "fsl,sec-v5.0-job-ring",
4649 + "fsl,sec-v4.0-job-ring";
4650 + reg = <0x20000 0x10000>;
4651 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4654 + sec_jr2: jr@30000 {
4655 + compatible = "fsl,sec-v5.4-job-ring",
4656 + "fsl,sec-v5.0-job-ring",
4657 + "fsl,sec-v4.0-job-ring";
4658 + reg = <0x30000 0x10000>;
4659 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4662 + sec_jr3: jr@40000 {
4663 + compatible = "fsl,sec-v5.4-job-ring",
4664 + "fsl,sec-v5.0-job-ring",
4665 + "fsl,sec-v4.0-job-ring";
4666 + reg = <0x40000 0x10000>;
4667 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4671 + qman: qman@1880000 {
4672 + compatible = "fsl,qman";
4673 + reg = <0x00 0x1880000 0x0 0x10000>;
4674 + interrupts = <0 45 0x4>;
4675 + memory-region = <&qman_fqd &qman_pfdr>;
4679 + bman: bman@1890000 {
4680 + compatible = "fsl,bman";
4681 + reg = <0x00 0x1890000 0x0 0x10000>;
4682 + interrupts = <0 45 0x4>;
4683 + memory-region = <&bman_fbpr>;
4687 + qportals: qman-portals@500000000 {
4688 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4691 + bportals: bman-portals@508000000 {
4692 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4695 + dcfg: dcfg@1ee0000 {
4696 + compatible = "fsl,ls1046a-dcfg", "syscon";
4697 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4701 + clockgen: clocking@1ee1000 {
4702 + compatible = "fsl,ls1046a-clockgen";
4703 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4704 + #clock-cells = <2>;
4705 + clocks = <&sysclk>;
4708 + tmu: tmu@1f00000 {
4709 + compatible = "fsl,qoriq-tmu";
4710 + reg = <0x0 0x1f00000 0x0 0x10000>;
4711 + interrupts = <0 33 0x4>;
4712 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4713 + fsl,tmu-calibration =
4714 + /* Calibration data group 1 */
4715 + <0x00000000 0x00000026
4716 + 0x00000001 0x0000002d
4717 + 0x00000002 0x00000032
4718 + 0x00000003 0x00000039
4719 + 0x00000004 0x0000003f
4720 + 0x00000005 0x00000046
4721 + 0x00000006 0x0000004d
4722 + 0x00000007 0x00000054
4723 + 0x00000008 0x0000005a
4724 + 0x00000009 0x00000061
4725 + 0x0000000a 0x0000006a
4726 + 0x0000000b 0x00000071
4727 + /* Calibration data group 2 */
4728 + 0x00010000 0x00000025
4729 + 0x00010001 0x0000002c
4730 + 0x00010002 0x00000035
4731 + 0x00010003 0x0000003d
4732 + 0x00010004 0x00000045
4733 + 0x00010005 0x0000004e
4734 + 0x00010006 0x00000057
4735 + 0x00010007 0x00000061
4736 + 0x00010008 0x0000006b
4737 + 0x00010009 0x00000076
4738 + /* Calibration data group 3 */
4739 + 0x00020000 0x00000029
4740 + 0x00020001 0x00000033
4741 + 0x00020002 0x0000003d
4742 + 0x00020003 0x00000049
4743 + 0x00020004 0x00000056
4744 + 0x00020005 0x00000061
4745 + 0x00020006 0x0000006d
4746 + /* Calibration data group 4 */
4747 + 0x00030000 0x00000021
4748 + 0x00030001 0x0000002a
4749 + 0x00030002 0x0000003c
4750 + 0x00030003 0x0000004e>;
4752 + #thermal-sensor-cells = <1>;
4756 + cpu_thermal: cpu-thermal {
4757 + polling-delay-passive = <1000>;
4758 + polling-delay = <5000>;
4759 + thermal-sensors = <&tmu 3>;
4762 + cpu_alert: cpu-alert {
4763 + temperature = <85000>;
4764 + hysteresis = <2000>;
4768 + cpu_crit: cpu-crit {
4769 + temperature = <95000>;
4770 + hysteresis = <2000>;
4771 + type = "critical";
4777 + trip = <&cpu_alert>;
4779 + <&cpu0 THERMAL_NO_LIMIT
4780 + THERMAL_NO_LIMIT>;
4786 + dspi: dspi@2100000 {
4787 + compatible = "fsl,ls1021a-v1.0-dspi";
4788 + #address-cells = <1>;
4789 + #size-cells = <0>;
4790 + reg = <0x0 0x2100000 0x0 0x10000>;
4791 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4792 + clock-names = "dspi";
4793 + clocks = <&clockgen 4 1>;
4794 + spi-num-chipselects = <5>;
4796 + status = "disabled";
4799 + i2c0: i2c@2180000 {
4800 + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
4801 + #address-cells = <1>;
4802 + #size-cells = <0>;
4803 + reg = <0x0 0x2180000 0x0 0x10000>;
4804 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4805 + clocks = <&clockgen 4 1>;
4806 + dmas = <&edma0 1 39>,
4808 + dma-names = "tx", "rx";
4809 + fsl-scl-gpio = <&gpio3 12 0>;
4810 + status = "disabled";
4813 + i2c1: i2c@2190000 {
4814 + compatible = "fsl,vf610-i2c";
4815 + #address-cells = <1>;
4816 + #size-cells = <0>;
4817 + reg = <0x0 0x2190000 0x0 0x10000>;
4818 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4819 + clocks = <&clockgen 4 1>;
4820 + status = "disabled";
4823 + i2c2: i2c@21a0000 {
4824 + compatible = "fsl,vf610-i2c";
4825 + #address-cells = <1>;
4826 + #size-cells = <0>;
4827 + reg = <0x0 0x21a0000 0x0 0x10000>;
4828 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4829 + clocks = <&clockgen 4 1>;
4830 + status = "disabled";
4833 + i2c3: i2c@21b0000 {
4834 + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
4835 + #address-cells = <1>;
4836 + #size-cells = <0>;
4837 + reg = <0x0 0x21b0000 0x0 0x10000>;
4838 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4839 + clocks = <&clockgen 4 1>;
4840 + fsl-scl-gpio = <&gpio3 12 0>;
4841 + status = "disabled";
4844 + duart0: serial@21c0500 {
4845 + compatible = "fsl,ns16550", "ns16550a";
4846 + reg = <0x00 0x21c0500 0x0 0x100>;
4847 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4848 + clocks = <&clockgen 4 1>;
4851 + duart1: serial@21c0600 {
4852 + compatible = "fsl,ns16550", "ns16550a";
4853 + reg = <0x00 0x21c0600 0x0 0x100>;
4854 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4855 + clocks = <&clockgen 4 1>;
4858 + duart2: serial@21d0500 {
4859 + compatible = "fsl,ns16550", "ns16550a";
4860 + reg = <0x0 0x21d0500 0x0 0x100>;
4861 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4862 + clocks = <&clockgen 4 1>;
4865 + duart3: serial@21d0600 {
4866 + compatible = "fsl,ns16550", "ns16550a";
4867 + reg = <0x0 0x21d0600 0x0 0x100>;
4868 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4869 + clocks = <&clockgen 4 1>;
4872 + gpio0: gpio@2300000 {
4873 + compatible = "fsl,qoriq-gpio";
4874 + reg = <0x0 0x2300000 0x0 0x10000>;
4875 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4877 + #gpio-cells = <2>;
4878 + interrupt-controller;
4879 + #interrupt-cells = <2>;
4882 + gpio1: gpio@2310000 {
4883 + compatible = "fsl,qoriq-gpio";
4884 + reg = <0x0 0x2310000 0x0 0x10000>;
4885 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4887 + #gpio-cells = <2>;
4888 + interrupt-controller;
4889 + #interrupt-cells = <2>;
4892 + gpio2: gpio@2320000 {
4893 + compatible = "fsl,qoriq-gpio";
4894 + reg = <0x0 0x2320000 0x0 0x10000>;
4895 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4897 + #gpio-cells = <2>;
4898 + interrupt-controller;
4899 + #interrupt-cells = <2>;
4902 + gpio3: gpio@2330000 {
4903 + compatible = "fsl,qoriq-gpio";
4904 + reg = <0x0 0x2330000 0x0 0x10000>;
4905 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4907 + #gpio-cells = <2>;
4908 + interrupt-controller;
4909 + #interrupt-cells = <2>;
4912 + lpuart0: serial@2950000 {
4913 + compatible = "fsl,ls1021a-lpuart";
4914 + reg = <0x0 0x2950000 0x0 0x1000>;
4915 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4916 + clocks = <&clockgen 4 0>;
4917 + clock-names = "ipg";
4918 + status = "disabled";
4921 + lpuart1: serial@2960000 {
4922 + compatible = "fsl,ls1021a-lpuart";
4923 + reg = <0x0 0x2960000 0x0 0x1000>;
4924 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4925 + clocks = <&clockgen 4 1>;
4926 + clock-names = "ipg";
4927 + status = "disabled";
4930 + lpuart2: serial@2970000 {
4931 + compatible = "fsl,ls1021a-lpuart";
4932 + reg = <0x0 0x2970000 0x0 0x1000>;
4933 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4934 + clocks = <&clockgen 4 1>;
4935 + clock-names = "ipg";
4936 + status = "disabled";
4939 + lpuart3: serial@2980000 {
4940 + compatible = "fsl,ls1021a-lpuart";
4941 + reg = <0x0 0x2980000 0x0 0x1000>;
4942 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4943 + clocks = <&clockgen 4 1>;
4944 + clock-names = "ipg";
4945 + status = "disabled";
4948 + lpuart4: serial@2990000 {
4949 + compatible = "fsl,ls1021a-lpuart";
4950 + reg = <0x0 0x2990000 0x0 0x1000>;
4951 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4952 + clocks = <&clockgen 4 1>;
4953 + clock-names = "ipg";
4954 + status = "disabled";
4957 + lpuart5: serial@29a0000 {
4958 + compatible = "fsl,ls1021a-lpuart";
4959 + reg = <0x0 0x29a0000 0x0 0x1000>;
4960 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4961 + clocks = <&clockgen 4 1>;
4962 + clock-names = "ipg";
4963 + status = "disabled";
4966 + ftm0: ftm0@29d0000 {
4967 + compatible = "fsl,ls1046a-ftm";
4968 + reg = <0x0 0x29d0000 0x0 0x10000>,
4969 + <0x0 0x1ee2140 0x0 0x4>;
4970 + reg-names = "ftm", "FlexTimer1";
4971 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4975 + wdog0: watchdog@2ad0000 {
4976 + compatible = "fsl,imx21-wdt";
4977 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4978 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4979 + clocks = <&clockgen 4 1>;
4983 + edma0: edma@2c00000 {
4985 + compatible = "fsl,vf610-edma";
4986 + reg = <0x0 0x2c00000 0x0 0x10000>,
4987 + <0x0 0x2c10000 0x0 0x10000>,
4988 + <0x0 0x2c20000 0x0 0x10000>;
4989 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4990 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4991 + interrupt-names = "edma-tx", "edma-err";
4992 + dma-channels = <32>;
4994 + clock-names = "dmamux0", "dmamux1";
4995 + clocks = <&clockgen 4 1>,
4999 + usb0: usb@2f00000 {
5000 + compatible = "snps,dwc3";
5001 + reg = <0x0 0x2f00000 0x0 0x10000>;
5002 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
5004 + snps,quirk-frame-length-adjustment = <0x20>;
5005 + snps,dis_rxdet_inp3_quirk;
5007 + snps,dis-u1u2-when-u3-quirk;
5010 + usb1: usb@3000000 {
5011 + compatible = "snps,dwc3";
5012 + reg = <0x0 0x3000000 0x0 0x10000>;
5013 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
5015 + snps,quirk-frame-length-adjustment = <0x20>;
5016 + snps,dis_rxdet_inp3_quirk;
5018 + snps,dis-u1u2-when-u3-quirk;
5021 + usb2: usb@3100000 {
5022 + compatible = "snps,dwc3";
5023 + reg = <0x0 0x3100000 0x0 0x10000>;
5024 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
5026 + snps,quirk-frame-length-adjustment = <0x20>;
5027 + snps,dis_rxdet_inp3_quirk;
5029 + snps,dis-u1u2-when-u3-quirk;
5032 + sata: sata@3200000 {
5033 + compatible = "fsl,ls1046a-ahci";
5034 + reg = <0x0 0x3200000 0x0 0x10000>,
5035 + <0x0 0x20140520 0x0 0x4>;
5036 + reg-names = "ahci", "sata-ecc";
5037 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
5038 + clocks = <&clockgen 4 1>;
5042 + qdma: qdma@8380000 {
5043 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
5044 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
5045 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
5046 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
5047 + interrupts = <0 153 0x4>,
5049 + interrupt-names = "qdma-error", "qdma-queue";
5052 + status-sizes = <64>;
5053 + queue-sizes = <64 64>;
5057 + msi1: msi-controller@1580000 {
5058 + compatible = "fsl,ls1046a-msi";
5060 + reg = <0x0 0x1580000 0x0 0x10000>;
5061 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5062 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5063 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5064 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
5067 + msi2: msi-controller@1590000 {
5068 + compatible = "fsl,ls1046a-msi";
5070 + reg = <0x0 0x1590000 0x0 0x10000>;
5071 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
5072 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
5073 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
5074 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
5077 + msi3: msi-controller@15a0000 {
5078 + compatible = "fsl,ls1046a-msi";
5080 + reg = <0x0 0x15a0000 0x0 0x10000>;
5081 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
5082 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
5083 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
5084 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
5088 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
5089 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
5090 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
5091 + reg-names = "regs", "config";
5092 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
5093 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5094 + interrupt-names = "pme", "aer";
5095 + #address-cells = <3>;
5096 + #size-cells = <2>;
5097 + device_type = "pci";
5100 + bus-range = <0x0 0xff>;
5101 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
5102 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5103 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
5104 + #interrupt-cells = <1>;
5105 + interrupt-map-mask = <0 0 0 7>;
5106 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5107 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5108 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5109 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
5113 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
5114 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
5115 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
5116 + reg-names = "regs", "config";
5117 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
5118 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
5119 + interrupt-names = "pme", "aer";
5120 + #address-cells = <3>;
5121 + #size-cells = <2>;
5122 + device_type = "pci";
5125 + bus-range = <0x0 0xff>;
5126 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
5127 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5128 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
5129 + #interrupt-cells = <1>;
5130 + interrupt-map-mask = <0 0 0 7>;
5131 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
5132 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
5133 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
5134 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
5138 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
5139 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
5140 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
5141 + reg-names = "regs", "config";
5142 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
5143 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
5144 + interrupt-names = "pme", "aer";
5145 + #address-cells = <3>;
5146 + #size-cells = <2>;
5147 + device_type = "pci";
5150 + bus-range = <0x0 0xff>;
5151 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
5152 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5153 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
5154 + #interrupt-cells = <1>;
5155 + interrupt-map-mask = <0 0 0 7>;
5156 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
5157 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
5158 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
5159 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
5165 + #address-cells = <2>;
5166 + #size-cells = <2>;
5169 + bman_fbpr: bman-fbpr {
5170 + compatible = "shared-dma-pool";
5171 + size = <0 0x1000000>;
5172 + alignment = <0 0x1000000>;
5175 + qman_fqd: qman-fqd {
5176 + compatible = "shared-dma-pool";
5177 + size = <0 0x800000>;
5178 + alignment = <0 0x800000>;
5181 + qman_pfdr: qman-pfdr {
5182 + compatible = "shared-dma-pool";
5183 + size = <0 0x2000000>;
5184 + alignment = <0 0x2000000>;
5191 + compatible = "linaro,optee-tz";
5197 +#include "qoriq-qman-portals.dtsi"
5198 +#include "qoriq-bman-portals.dtsi"
5200 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
5202 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5204 + * Device Tree file for NXP LS1088A QDS Board.
5206 + * Copyright 2017 NXP
5208 + * Harninder Rai <harninder.rai@nxp.com>
5214 +#include "fsl-ls1088a.dtsi"
5217 + model = "LS1088A QDS Board";
5218 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
5225 + compatible = "nxp,pca9547";
5227 + #address-cells = <1>;
5228 + #size-cells = <0>;
5231 + #address-cells = <1>;
5232 + #size-cells = <0>;
5236 + compatible = "ti,ina220";
5238 + shunt-resistor = <1000>;
5242 + compatible = "ti,ina220";
5244 + shunt-resistor = <1000>;
5249 + #address-cells = <1>;
5250 + #size-cells = <0>;
5254 + compatible = "adi,adt7461a";
5259 + compatible = "nxp,pcf2129";
5262 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5266 + compatible = "atmel,24c512";
5271 + compatible = "atmel,24c512";
5280 + qflash0: s25fs512s@0 {
5281 + compatible = "spansion,m25p80";
5282 + #address-cells = <1>;
5283 + #size-cells = <1>;
5284 + spi-max-frequency = <20000000>;
5289 + qflash1: s25fs512s@1 {
5290 + compatible = "spansion,m25p80";
5291 + #address-cells = <1>;
5292 + #size-cells = <1>;
5293 + spi-max-frequency = <20000000>;
5302 + ranges = <0 0 0x5 0x80000000 0x08000000
5303 + 2 0 0x5 0x30000000 0x00010000
5304 + 3 0 0x5 0x20000000 0x00010000>;
5307 + compatible = "cfi-flash";
5308 + reg = <0x0 0x0 0x8000000>;
5310 + device-width = <1>;
5314 + compatible = "fsl,ifc-nand";
5315 + reg = <0x2 0x0 0x10000>;
5318 + fpga: board-control@3,0 {
5319 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
5320 + reg = <0x3 0x0 0x0000100>;
5340 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
5342 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5344 + * Device Tree file for NXP LS1088A RDB Board.
5346 + * Copyright 2017 NXP
5348 + * Harninder Rai <harninder.rai@nxp.com>
5354 +#include "fsl-ls1088a.dtsi"
5357 + model = "L1088A RDB Board";
5358 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
5365 + compatible = "nxp,pca9547";
5367 + #address-cells = <1>;
5368 + #size-cells = <0>;
5371 + #address-cells = <1>;
5372 + #size-cells = <0>;
5376 + compatible = "ti,ina220";
5378 + shunt-resistor = <1000>;
5383 + #address-cells = <1>;
5384 + #size-cells = <0>;
5388 + compatible = "adi,adt7461a";
5393 + compatible = "nxp,pcf2129";
5396 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5404 + qflash0: s25fs512s@0 {
5405 + compatible = "spansion,m25p80";
5406 + #address-cells = <1>;
5407 + #size-cells = <1>;
5409 + spi-max-frequency = <20000000>;
5413 + qflash1: s25fs512s@1 {
5414 + compatible = "spansion,m25p80";
5415 + #address-cells = <1>;
5416 + #size-cells = <1>;
5418 + spi-max-frequency = <20000000>;
5426 + ranges = <0 0 0x5 0x30000000 0x00010000
5427 + 2 0 0x5 0x20000000 0x00010000>;
5430 + compatible = "fsl,ifc-nand";
5431 + reg = <0x0 0x0 0x10000>;
5434 + fpga: board-control@2,0 {
5435 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
5436 + reg = <0x2 0x0 0x0000100>;
5465 + /* Freescale F104 PHY1 */
5466 + mdio1_phy1: emdio1_phy@1 {
5468 + phy-connection-type = "qsgmii";
5470 + mdio1_phy2: emdio1_phy@2 {
5472 + phy-connection-type = "qsgmii";
5474 + mdio1_phy3: emdio1_phy@3 {
5476 + phy-connection-type = "qsgmii";
5478 + mdio1_phy4: emdio1_phy@4 {
5480 + phy-connection-type = "qsgmii";
5483 + mdio1_phy5: emdio1_phy@5 {
5485 + phy-connection-type = "qsgmii";
5487 + mdio1_phy6: emdio1_phy@6 {
5489 + phy-connection-type = "qsgmii";
5491 + mdio1_phy7: emdio1_phy@7 {
5493 + phy-connection-type = "qsgmii";
5495 + mdio1_phy8: emdio1_phy@8 {
5497 + phy-connection-type = "qsgmii";
5502 + /* Aquantia AQR105 10G PHY */
5503 + mdio2_phy1: emdio2_phy@1 {
5504 + compatible = "ethernet-phy-ieee802.3-c45";
5505 + interrupts = <0 2 0x4>;
5507 + phy-connection-type = "xfi";
5511 +/* DPMAC connections to external PHYs
5512 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5514 +/* DPMAC1 is 10G SFP+, fixed link */
5516 + phy-handle = <&mdio2_phy1>;
5519 + phy-handle = <&mdio1_phy5>;
5522 + phy-handle = <&mdio1_phy6>;
5525 + phy-handle = <&mdio1_phy7>;
5528 + phy-handle = <&mdio1_phy8>;
5531 + phy-handle = <&mdio1_phy1>;
5534 + phy-handle = <&mdio1_phy2>;
5537 + phy-handle = <&mdio1_phy3>;
5540 + phy-handle = <&mdio1_phy4>;
5543 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5545 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5547 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5549 + * Copyright 2017 NXP
5551 + * Harninder Rai <harninder.rai@nxp.com>
5554 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5555 +#include <dt-bindings/thermal/thermal.h>
5558 + compatible = "fsl,ls1088a";
5559 + interrupt-parent = <&gic>;
5560 + #address-cells = <2>;
5561 + #size-cells = <2>;
5568 + #address-cells = <1>;
5569 + #size-cells = <0>;
5571 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5573 + device_type = "cpu";
5574 + compatible = "arm,cortex-a53";
5576 + clocks = <&clockgen 1 0>;
5577 + #cooling-cells = <2>;
5578 + cpu-idle-states = <&CPU_PH20>;
5582 + device_type = "cpu";
5583 + compatible = "arm,cortex-a53";
5585 + clocks = <&clockgen 1 0>;
5586 + cpu-idle-states = <&CPU_PH20>;
5590 + device_type = "cpu";
5591 + compatible = "arm,cortex-a53";
5593 + clocks = <&clockgen 1 0>;
5594 + cpu-idle-states = <&CPU_PH20>;
5598 + device_type = "cpu";
5599 + compatible = "arm,cortex-a53";
5601 + clocks = <&clockgen 1 0>;
5602 + cpu-idle-states = <&CPU_PH20>;
5606 + device_type = "cpu";
5607 + compatible = "arm,cortex-a53";
5609 + clocks = <&clockgen 1 1>;
5610 + #cooling-cells = <2>;
5611 + cpu-idle-states = <&CPU_PH20>;
5615 + device_type = "cpu";
5616 + compatible = "arm,cortex-a53";
5618 + clocks = <&clockgen 1 1>;
5619 + cpu-idle-states = <&CPU_PH20>;
5623 + device_type = "cpu";
5624 + compatible = "arm,cortex-a53";
5626 + clocks = <&clockgen 1 1>;
5627 + cpu-idle-states = <&CPU_PH20>;
5631 + device_type = "cpu";
5632 + compatible = "arm,cortex-a53";
5634 + clocks = <&clockgen 1 1>;
5635 + cpu-idle-states = <&CPU_PH20>;
5641 + * PSCI node is not added default, U-boot will add missing
5642 + * parts if it determines to use PSCI.
5644 + entry-method = "arm,psci";
5646 + CPU_PH20: cpu-ph20 {
5647 + compatible = "arm,idle-state";
5648 + idle-state-name = "PH20";
5649 + arm,psci-suspend-param = <0x0>;
5650 + entry-latency-us = <1000>;
5651 + exit-latency-us = <1000>;
5652 + min-residency-us = <3000>;
5656 + gic: interrupt-controller@6000000 {
5657 + compatible = "arm,gic-v3";
5658 + #interrupt-cells = <3>;
5659 + #address-cells = <2>;
5660 + #size-cells = <2>;
5662 + interrupt-controller;
5663 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5664 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5665 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5666 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5667 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5668 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5670 + its: gic-its@6020000 {
5671 + compatible = "arm,gic-v3-its";
5673 + reg = <0x0 0x6020000 0 0x20000>;
5678 + compatible = "arm,armv8-timer";
5679 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5680 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5681 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5682 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5686 + compatible = "fixed-clock";
5687 + #clock-cells = <0>;
5688 + clock-frequency = <100000000>;
5689 + clock-output-names = "sysclk";
5692 + dcfg: dcfg@1e00000 {
5693 + compatible = "fsl,ls1088a-dcfg", "syscon";
5694 + reg = <0x0 0x1e00000 0x0 0x10000>;
5698 + rstcr: syscon@1e60000 {
5699 + compatible = "fsl,ls1088a-rstcr", "syscon";
5700 + reg = <0x0 0x1e60000 0x0 0x4>;
5704 + compatible = "syscon-reboot";
5705 + regmap = <&rstcr>;
5712 + compatible = "simple-bus";
5713 + #address-cells = <2>;
5714 + #size-cells = <2>;
5716 + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
5718 + clockgen: clocking@1300000 {
5719 + compatible = "fsl,ls1088a-clockgen";
5720 + reg = <0 0x1300000 0 0xa0000>;
5721 + #clock-cells = <2>;
5722 + clocks = <&sysclk>;
5725 + tmu: tmu@1f80000 {
5726 + compatible = "fsl,qoriq-tmu";
5727 + reg = <0x0 0x1f80000 0x0 0x10000>;
5728 + interrupts = <0 23 0x4>;
5729 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5730 + fsl,tmu-calibration =
5731 + /* Calibration data group 1 */
5732 + <0x00000000 0x00000026
5733 + 0x00000001 0x0000002d
5734 + 0x00000002 0x00000032
5735 + 0x00000003 0x00000039
5736 + 0x00000004 0x0000003f
5737 + 0x00000005 0x00000046
5738 + 0x00000006 0x0000004d
5739 + 0x00000007 0x00000054
5740 + 0x00000008 0x0000005a
5741 + 0x00000009 0x00000061
5742 + 0x0000000a 0x0000006a
5743 + 0x0000000b 0x00000071
5744 + /* Calibration data group 2 */
5745 + 0x00010000 0x00000025
5746 + 0x00010001 0x0000002c
5747 + 0x00010002 0x00000035
5748 + 0x00010003 0x0000003d
5749 + 0x00010004 0x00000045
5750 + 0x00010005 0x0000004e
5751 + 0x00010006 0x00000057
5752 + 0x00010007 0x00000061
5753 + 0x00010008 0x0000006b
5754 + 0x00010009 0x00000076
5755 + /* Calibration data group 3 */
5756 + 0x00020000 0x00000029
5757 + 0x00020001 0x00000033
5758 + 0x00020002 0x0000003d
5759 + 0x00020003 0x00000049
5760 + 0x00020004 0x00000056
5761 + 0x00020005 0x00000061
5762 + 0x00020006 0x0000006d
5763 + /* Calibration data group 4 */
5764 + 0x00030000 0x00000021
5765 + 0x00030001 0x0000002a
5766 + 0x00030002 0x0000003c
5767 + 0x00030003 0x0000004e>;
5769 + #thermal-sensor-cells = <1>;
5773 + cpu_thermal: cpu-thermal {
5774 + polling-delay-passive = <1000>;
5775 + polling-delay = <5000>;
5776 + thermal-sensors = <&tmu 0>;
5779 + cpu_alert: cpu-alert {
5780 + temperature = <85000>;
5781 + hysteresis = <2000>;
5785 + cpu_crit: cpu-crit {
5786 + temperature = <95000>;
5787 + hysteresis = <2000>;
5788 + type = "critical";
5794 + trip = <&cpu_alert>;
5796 + <&cpu0 THERMAL_NO_LIMIT
5797 + THERMAL_NO_LIMIT>;
5800 + trip = <&cpu_alert>;
5802 + <&cpu4 THERMAL_NO_LIMIT
5803 + THERMAL_NO_LIMIT>;
5809 + duart0: serial@21c0500 {
5810 + compatible = "fsl,ns16550", "ns16550a";
5811 + reg = <0x0 0x21c0500 0x0 0x100>;
5812 + clocks = <&clockgen 4 3>;
5813 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5814 + status = "disabled";
5817 + duart1: serial@21c0600 {
5818 + compatible = "fsl,ns16550", "ns16550a";
5819 + reg = <0x0 0x21c0600 0x0 0x100>;
5820 + clocks = <&clockgen 4 3>;
5821 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5822 + status = "disabled";
5825 + cluster1_core0_watchdog: wdt@c000000 {
5826 + compatible = "arm,sp805-wdt", "arm,primecell";
5827 + reg = <0x0 0xc000000 0x0 0x1000>;
5828 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5829 + clock-names = "apb_pclk", "wdog_clk";
5832 + cluster1_core1_watchdog: wdt@c010000 {
5833 + compatible = "arm,sp805-wdt", "arm,primecell";
5834 + reg = <0x0 0xc010000 0x0 0x1000>;
5835 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5836 + clock-names = "apb_pclk", "wdog_clk";
5839 + cluster1_core2_watchdog: wdt@c020000 {
5840 + compatible = "arm,sp805-wdt", "arm,primecell";
5841 + reg = <0x0 0xc020000 0x0 0x1000>;
5842 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5843 + clock-names = "apb_pclk", "wdog_clk";
5846 + cluster1_core3_watchdog: wdt@c030000 {
5847 + compatible = "arm,sp805-wdt", "arm,primecell";
5848 + reg = <0x0 0xc030000 0x0 0x1000>;
5849 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5850 + clock-names = "apb_pclk", "wdog_clk";
5853 + cluster2_core0_watchdog: wdt@c100000 {
5854 + compatible = "arm,sp805-wdt", "arm,primecell";
5855 + reg = <0x0 0xc100000 0x0 0x1000>;
5856 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5857 + clock-names = "apb_pclk", "wdog_clk";
5860 + cluster2_core1_watchdog: wdt@c110000 {
5861 + compatible = "arm,sp805-wdt", "arm,primecell";
5862 + reg = <0x0 0xc110000 0x0 0x1000>;
5863 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5864 + clock-names = "apb_pclk", "wdog_clk";
5867 + cluster2_core2_watchdog: wdt@c120000 {
5868 + compatible = "arm,sp805-wdt", "arm,primecell";
5869 + reg = <0x0 0xc120000 0x0 0x1000>;
5870 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5871 + clock-names = "apb_pclk", "wdog_clk";
5874 + cluster2_core3_watchdog: wdt@c130000 {
5875 + compatible = "arm,sp805-wdt", "arm,primecell";
5876 + reg = <0x0 0xc130000 0x0 0x1000>;
5877 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5878 + clock-names = "apb_pclk", "wdog_clk";
5881 + gpio0: gpio@2300000 {
5882 + compatible = "fsl,qoriq-gpio";
5883 + reg = <0x0 0x2300000 0x0 0x10000>;
5884 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5886 + #gpio-cells = <2>;
5887 + interrupt-controller;
5888 + #interrupt-cells = <2>;
5891 + gpio1: gpio@2310000 {
5892 + compatible = "fsl,qoriq-gpio";
5893 + reg = <0x0 0x2310000 0x0 0x10000>;
5894 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5896 + #gpio-cells = <2>;
5897 + interrupt-controller;
5898 + #interrupt-cells = <2>;
5901 + gpio2: gpio@2320000 {
5902 + compatible = "fsl,qoriq-gpio";
5903 + reg = <0x0 0x2320000 0x0 0x10000>;
5904 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5906 + #gpio-cells = <2>;
5907 + interrupt-controller;
5908 + #interrupt-cells = <2>;
5911 + gpio3: gpio@2330000 {
5912 + compatible = "fsl,qoriq-gpio";
5913 + reg = <0x0 0x2330000 0x0 0x10000>;
5914 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5916 + #gpio-cells = <2>;
5917 + interrupt-controller;
5918 + #interrupt-cells = <2>;
5921 + /* TODO: WRIOP (CCSR?) */
5922 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5923 + * E-MDIO1: 0x1_6000
5925 + compatible = "fsl,fman-memac-mdio";
5926 + reg = <0x0 0x8B96000 0x0 0x1000>;
5927 + device_type = "mdio";
5928 + little-endian; /* force the driver in LE mode */
5930 + /* Not necessary on the QDS, but needed on the RDB */
5931 + #address-cells = <1>;
5932 + #size-cells = <0>;
5935 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5936 + * E-MDIO2: 0x1_7000
5938 + compatible = "fsl,fman-memac-mdio";
5939 + reg = <0x0 0x8B97000 0x0 0x1000>;
5940 + device_type = "mdio";
5941 + little-endian; /* force the driver in LE mode */
5943 + #address-cells = <1>;
5944 + #size-cells = <0>;
5947 + ifc: ifc@2240000 {
5948 + compatible = "fsl,ifc", "simple-bus";
5949 + reg = <0x0 0x2240000 0x0 0x20000>;
5950 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5952 + #address-cells = <2>;
5953 + #size-cells = <1>;
5957 + ftm0: ftm0@2800000 {
5958 + compatible = "fsl,ls1088a-ftm";
5959 + reg = <0x0 0x2800000 0x0 0x10000>,
5960 + <0x0 0x1e34050 0x0 0x4>;
5961 + interrupts = <0 44 4>;
5962 + reg-names = "ftm", "FlexTimer1";
5965 + i2c0: i2c@2000000 {
5966 + compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
5967 + #address-cells = <1>;
5968 + #size-cells = <0>;
5969 + reg = <0x0 0x2000000 0x0 0x10000>;
5970 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5971 + clocks = <&clockgen 4 7>;
5972 + fsl-scl-gpio = <&gpio3 30 0>;
5973 + status = "disabled";
5976 + i2c1: i2c@2010000 {
5977 + compatible = "fsl,vf610-i2c";
5978 + #address-cells = <1>;
5979 + #size-cells = <0>;
5980 + reg = <0x0 0x2010000 0x0 0x10000>;
5981 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5982 + clocks = <&clockgen 4 7>;
5983 + status = "disabled";
5986 + i2c2: i2c@2020000 {
5987 + compatible = "fsl,vf610-i2c";
5988 + #address-cells = <1>;
5989 + #size-cells = <0>;
5990 + reg = <0x0 0x2020000 0x0 0x10000>;
5991 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5992 + clocks = <&clockgen 4 7>;
5993 + status = "disabled";
5996 + i2c3: i2c@2030000 {
5997 + compatible = "fsl,vf610-i2c";
5998 + #address-cells = <1>;
5999 + #size-cells = <0>;
6000 + reg = <0x0 0x2030000 0x0 0x10000>;
6001 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
6002 + clocks = <&clockgen 4 7>;
6003 + status = "disabled";
6006 + qspi: quadspi@20c0000 {
6007 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
6008 + #address-cells = <1>;
6009 + #size-cells = <0>;
6010 + reg = <0x0 0x20c0000 0x0 0x10000>,
6011 + <0x0 0x20000000 0x0 0x10000000>;
6012 + reg-names = "QuadSPI", "QuadSPI-memory";
6013 + interrupts = <0 25 0x4>; /* Level high type */
6014 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6015 + clock-names = "qspi_en", "qspi";
6016 + fsl,qspi-has-second-chip;
6019 + esdhc: esdhc@2140000 {
6020 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
6021 + reg = <0x0 0x2140000 0x0 0x10000>;
6022 + interrupts = <0 28 0x4>; /* Level high type */
6023 + clock-frequency = <0>;
6024 + voltage-ranges = <1800 1800 3300 3300>;
6028 + status = "disabled";
6031 + usb0: usb3@3100000 {
6032 + compatible = "snps,dwc3";
6033 + reg = <0x0 0x3100000 0x0 0x10000>;
6034 + interrupts = <0 80 0x4>; /* Level high type */
6037 + snps,dis_rxdet_inp3_quirk;
6040 + usb1: usb3@3110000 {
6041 + compatible = "snps,dwc3";
6042 + reg = <0x0 0x3110000 0x0 0x10000>;
6043 + interrupts = <0 81 0x4>; /* Level high type */
6046 + snps,dis_rxdet_inp3_quirk;
6049 + sata: sata@3200000 {
6050 + compatible = "fsl,ls1088a-ahci";
6051 + reg = <0x0 0x3200000 0x0 0x10000>,
6052 + <0x7 0x100520 0x0 0x4>;
6053 + reg-names = "ahci", "sata-ecc";
6054 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
6055 + clocks = <&clockgen 4 3>;
6057 + status = "disabled";
6061 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6063 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
6064 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
6065 + reg-names = "regs", "config";
6066 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6067 + interrupt-names = "aer";
6068 + #address-cells = <3>;
6069 + #size-cells = <2>;
6070 + device_type = "pci";
6073 + bus-range = <0x0 0xff>;
6074 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
6075 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6076 + msi-parent = <&its>;
6077 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6078 + #interrupt-cells = <1>;
6079 + interrupt-map-mask = <0 0 0 7>;
6080 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
6081 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
6082 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
6083 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
6087 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6089 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
6090 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
6091 + reg-names = "regs", "config";
6092 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6093 + interrupt-names = "aer";
6094 + #address-cells = <3>;
6095 + #size-cells = <2>;
6096 + device_type = "pci";
6099 + bus-range = <0x0 0xff>;
6100 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
6101 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6102 + msi-parent = <&its>;
6103 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6104 + #interrupt-cells = <1>;
6105 + interrupt-map-mask = <0 0 0 7>;
6106 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
6107 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
6108 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
6109 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
6113 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
6115 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
6116 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
6117 + reg-names = "regs", "config";
6118 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
6119 + interrupt-names = "aer";
6120 + #address-cells = <3>;
6121 + #size-cells = <2>;
6122 + device_type = "pci";
6125 + bus-range = <0x0 0xff>;
6126 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
6127 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6128 + msi-parent = <&its>;
6129 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
6130 + #interrupt-cells = <1>;
6131 + interrupt-map-mask = <0 0 0 7>;
6132 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
6133 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
6134 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
6135 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
6138 + fsl_mc: fsl-mc@80c000000 {
6139 + compatible = "fsl,qoriq-mc";
6140 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6141 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6142 + msi-parent = <&its>;
6143 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
6145 + #address-cells = <3>;
6146 + #size-cells = <1>;
6149 + * Region type 0x0 - MC portals
6150 + * Region type 0x1 - QBMAN portals
6152 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6153 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6156 + #address-cells = <1>;
6157 + #size-cells = <0>;
6160 + compatible = "fsl,qoriq-mc-dpmac";
6165 + compatible = "fsl,qoriq-mc-dpmac";
6170 + compatible = "fsl,qoriq-mc-dpmac";
6175 + compatible = "fsl,qoriq-mc-dpmac";
6180 + compatible = "fsl,qoriq-mc-dpmac";
6185 + compatible = "fsl,qoriq-mc-dpmac";
6190 + compatible = "fsl,qoriq-mc-dpmac";
6195 + compatible = "fsl,qoriq-mc-dpmac";
6200 + compatible = "fsl,qoriq-mc-dpmac";
6204 + dpmac10: dpmac@a {
6205 + compatible = "fsl,qoriq-mc-dpmac";
6211 + smmu: iommu@5000000 {
6212 + compatible = "arm,mmu-500";
6213 + reg = <0 0x5000000 0 0x800000>;
6214 + #global-interrupts = <12>;
6215 + #iommu-cells = <1>;
6216 + stream-match-mask = <0x7C00>;
6217 + interrupts = <0 13 4>, /* global secure fault */
6218 + <0 14 4>, /* combined secure interrupt */
6219 + <0 15 4>, /* global non-secure fault */
6220 + <0 16 4>, /* combined non-secure interrupt */
6221 + /* performance counter interrupts 0-7 */
6230 + /* per context interrupt, 64 interrupts */
6297 + crypto: crypto@8000000 {
6298 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
6299 + fsl,sec-era = <8>;
6300 + #address-cells = <1>;
6301 + #size-cells = <1>;
6302 + ranges = <0x0 0x00 0x8000000 0x100000>;
6303 + reg = <0x00 0x8000000 0x0 0x100000>;
6304 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6307 + sec_jr0: jr@10000 {
6308 + compatible = "fsl,sec-v5.0-job-ring",
6309 + "fsl,sec-v4.0-job-ring";
6310 + reg = <0x10000 0x10000>;
6311 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
6314 + sec_jr1: jr@20000 {
6315 + compatible = "fsl,sec-v5.0-job-ring",
6316 + "fsl,sec-v4.0-job-ring";
6317 + reg = <0x20000 0x10000>;
6318 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
6321 + sec_jr2: jr@30000 {
6322 + compatible = "fsl,sec-v5.0-job-ring",
6323 + "fsl,sec-v4.0-job-ring";
6324 + reg = <0x30000 0x10000>;
6325 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
6328 + sec_jr3: jr@40000 {
6329 + compatible = "fsl,sec-v5.0-job-ring",
6330 + "fsl,sec-v4.0-job-ring";
6331 + reg = <0x40000 0x10000>;
6332 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
6339 + compatible = "linaro,optee-tz";
6345 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6346 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6348 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6350 * Device Tree file for Freescale LS2080a QDS Board.
6352 - * Copyright (C) 2015, Freescale Semiconductor
6353 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
6354 + * Copyright 2017 NXP
6356 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6357 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6359 - * This file is dual-licensed: you can use it either under the terms
6360 - * of the GPLv2 or the X11 license, at your option. Note that this dual
6361 - * licensing only applies to this file, and not this project as a
6364 - * a) This library is free software; you can redistribute it and/or
6365 - * modify it under the terms of the GNU General Public License as
6366 - * published by the Free Software Foundation; either version 2 of the
6367 - * License, or (at your option) any later version.
6369 - * This library is distributed in the hope that it will be useful,
6370 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6371 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6372 - * GNU General Public License for more details.
6374 - * Or, alternatively,
6376 - * b) Permission is hereby granted, free of charge, to any person
6377 - * obtaining a copy of this software and associated documentation
6378 - * files (the "Software"), to deal in the Software without
6379 - * restriction, including without limitation the rights to use,
6380 - * copy, modify, merge, publish, distribute, sublicense, and/or
6381 - * sell copies of the Software, and to permit persons to whom the
6382 - * Software is furnished to do so, subject to the following
6385 - * The above copyright notice and this permission notice shall be
6386 - * included in all copies or substantial portions of the Software.
6388 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
6389 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
6390 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
6391 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
6392 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
6393 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
6394 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
6395 - * OTHER DEALINGS IN THE SOFTWARE.
6400 -/include/ "fsl-ls2080a.dtsi"
6401 +#include "fsl-ls2080a.dtsi"
6402 +#include "fsl-ls208xa-qds.dtsi"
6405 model = "Freescale Layerscape 2080a QDS Board";
6406 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
6409 - serial0 = &serial0;
6410 - serial1 = &serial1;
6414 stdout-path = "serial0:115200n8";
6424 - #address-cells = <2>;
6425 - #size-cells = <1>;
6426 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6427 - 0x2 0x0 0x5 0x30000000 0x00010000
6428 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6431 + boardctrl: board-control@3,0 {
6432 #address-cells = <1>;
6434 - compatible = "cfi-flash";
6435 - reg = <0x0 0x0 0x8000000>;
6437 - device-width = <1>;
6441 - compatible = "fsl,ifc-nand";
6442 - reg = <0x2 0x0 0x10000>;
6444 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
6445 + reg = <3 0 0x300>; /* TODO check address */
6446 + ranges = <0 3 0 0x300>;
6449 - reg = <0x3 0x0 0x10000>;
6450 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6457 - compatible = "nxp,pca9547";
6459 - #address-cells = <1>;
6460 - #size-cells = <0>;
6462 - #address-cells = <1>;
6463 - #size-cells = <0>;
6466 - compatible = "dallas,ds3232";
6472 - #address-cells = <1>;
6473 - #size-cells = <0>;
6477 - compatible = "ti,ina220";
6479 - shunt-resistor = <500>;
6483 - compatible = "ti,ina220";
6485 - shunt-resistor = <1000>;
6489 + compatible = "mdio-mux-mmioreg", "mdio-mux";
6490 + mdio-parent-bus = <&emdio1>;
6491 + reg = <0x54 1>; /* BRDCFG4 */
6492 + mux-mask = <0xe0>; /* EMI1_MDIO */
6495 - #address-cells = <1>;
6496 + #address-cells=<1>;
6501 - compatible = "adi,adt7461";
6503 + /* Child MDIO buses, one for each riser card:
6504 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6505 + * VSC8234 PHYs on the riser cards.
6508 + mdio_mux3: mdio@60 {
6510 + #address-cells = <1>;
6511 + #size-cells = <0>;
6513 + mdio0_phy12: mdio_phy0@1c {
6515 + phy-connection-type = "sgmii";
6517 + mdio0_phy13: mdio_phy1@1d {
6519 + phy-connection-type = "sgmii";
6521 + mdio0_phy14: mdio_phy2@1e {
6523 + phy-connection-type = "sgmii";
6525 + mdio0_phy15: mdio_phy3@1f {
6527 + phy-connection-type = "sgmii";
6535 - status = "disabled";
6536 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6538 + phy-handle = <&mdio0_phy12>;
6542 - status = "disabled";
6546 - status = "disabled";
6551 - dflash0: n25q128a {
6552 - #address-cells = <1>;
6553 - #size-cells = <1>;
6554 - compatible = "st,m25p80";
6555 - spi-max-frequency = <3000000>;
6558 - dflash1: sst25wf040b {
6559 - #address-cells = <1>;
6560 - #size-cells = <1>;
6561 - compatible = "st,m25p80";
6562 - spi-max-frequency = <3000000>;
6565 - dflash2: en25s64 {
6566 - #address-cells = <1>;
6567 - #size-cells = <1>;
6568 - compatible = "st,m25p80";
6569 - spi-max-frequency = <3000000>;
6573 + phy-handle = <&mdio0_phy13>;
6578 - flash0: s25fl256s1@0 {
6579 - #address-cells = <1>;
6580 - #size-cells = <1>;
6581 - compatible = "st,m25p80";
6582 - spi-max-frequency = <20000000>;
6585 - flash2: s25fl256s1@2 {
6586 - #address-cells = <1>;
6587 - #size-cells = <1>;
6588 - compatible = "st,m25p80";
6589 - spi-max-frequency = <20000000>;
6593 + phy-handle = <&mdio0_phy14>;
6611 + phy-handle = <&mdio0_phy15>;
6613 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6614 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6616 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6618 * Device Tree file for Freescale LS2080a RDB Board.
6620 - * Copyright (C) 2015, Freescale Semiconductor
6621 + * Copyright 2016 Freescale Semiconductor, Inc.
6622 + * Copyright 2017 NXP
6624 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6625 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6627 - * This file is dual-licensed: you can use it either under the terms
6628 - * of the GPLv2 or the X11 license, at your option. Note that this dual
6629 - * licensing only applies to this file, and not this project as a
6632 - * a) This library is free software; you can redistribute it and/or
6633 - * modify it under the terms of the GNU General Public License as
6634 - * published by the Free Software Foundation; either version 2 of the
6635 - * License, or (at your option) any later version.
6637 - * This library is distributed in the hope that it will be useful,
6638 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6639 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6640 - * GNU General Public License for more details.
6642 - * Or, alternatively,
6644 - * b) Permission is hereby granted, free of charge, to any person
6645 - * obtaining a copy of this software and associated documentation
6646 - * files (the "Software"), to deal in the Software without
6647 - * restriction, including without limitation the rights to use,
6648 - * copy, modify, merge, publish, distribute, sublicense, and/or
6649 - * sell copies of the Software, and to permit persons to whom the
6650 - * Software is furnished to do so, subject to the following
6653 - * The above copyright notice and this permission notice shall be
6654 - * included in all copies or substantial portions of the Software.
6656 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
6657 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
6658 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
6659 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
6660 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
6661 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
6662 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
6663 - * OTHER DEALINGS IN THE SOFTWARE.
6668 -/include/ "fsl-ls2080a.dtsi"
6669 +#include "fsl-ls2080a.dtsi"
6670 +#include "fsl-ls208xa-rdb.dtsi"
6673 model = "Freescale Layerscape 2080a RDB Board";
6674 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6677 - serial0 = &serial0;
6678 - serial1 = &serial1;
6682 stdout-path = "serial1:115200n8";
6692 - #address-cells = <2>;
6693 - #size-cells = <1>;
6694 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6695 - 0x2 0x0 0x5 0x30000000 0x00010000
6696 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6699 - #address-cells = <1>;
6700 - #size-cells = <1>;
6701 - compatible = "cfi-flash";
6702 - reg = <0x0 0x0 0x8000000>;
6704 - device-width = <1>;
6708 - compatible = "fsl,ifc-nand";
6709 - reg = <0x2 0x0 0x10000>;
6713 - reg = <0x3 0x0 0x10000>;
6714 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6722 - compatible = "nxp,pca9547";
6724 - #address-cells = <1>;
6725 - #size-cells = <0>;
6726 - status = "disabled";
6728 - #address-cells = <1>;
6729 - #size-cells = <0>;
6732 - compatible = "dallas,ds3232";
6738 - #address-cells = <1>;
6739 - #size-cells = <0>;
6743 - compatible = "adi,adt7461";
6751 - status = "disabled";
6755 - status = "disabled";
6760 status = "disabled";
6762 + mdio1_phy1: emdio1_phy@1 {
6764 + phy-connection-type = "xfi";
6766 + mdio1_phy2: emdio1_phy@2 {
6768 + phy-connection-type = "xfi";
6770 + mdio1_phy3: emdio1_phy@3 {
6772 + phy-connection-type = "xfi";
6774 + mdio1_phy4: emdio1_phy@4 {
6776 + phy-connection-type = "xfi";
6782 - dflash0: n25q512a {
6783 - #address-cells = <1>;
6784 - #size-cells = <1>;
6785 - compatible = "st,m25p80";
6786 - spi-max-frequency = <3000000>;
6790 + mdio2_phy1: emdio2_phy@1 {
6791 + compatible = "ethernet-phy-ieee802.3-c45";
6792 + interrupts = <0 1 0x4>; /* Level high type */
6794 + phy-connection-type = "xfi";
6796 + mdio2_phy2: emdio2_phy@2 {
6797 + compatible = "ethernet-phy-ieee802.3-c45";
6798 + interrupts = <0 2 0x4>; /* Level high type */
6800 + phy-connection-type = "xfi";
6802 + mdio2_phy3: emdio2_phy@3 {
6803 + compatible = "ethernet-phy-ieee802.3-c45";
6804 + interrupts = <0 4 0x4>; /* Level high type */
6806 + phy-connection-type = "xfi";
6808 + mdio2_phy4: emdio2_phy@4 {
6809 + compatible = "ethernet-phy-ieee802.3-c45";
6810 + interrupts = <0 5 0x4>; /* Level high type */
6812 + phy-connection-type = "xfi";
6817 - status = "disabled";
6819 +/* Update DPMAC connections to external PHYs, under the assumption of
6820 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6822 +/* Leave Cortina nodes commented out until driver is integrated
6824 + * phy-handle = <&mdio1_phy1>;
6827 + * phy-handle = <&mdio1_phy2>;
6830 + * phy-handle = <&mdio1_phy3>;
6833 + * phy-handle = <&mdio1_phy4>;
6840 + phy-handle = <&mdio2_phy1>;
6846 + phy-handle = <&mdio2_phy2>;
6852 + phy-handle = <&mdio2_phy3>;
6858 + phy-handle = <&mdio2_phy4>;
6860 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6861 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6863 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6865 * Device Tree file for Freescale LS2080a software Simulator model
6867 - * Copyright (C) 2014-2015, Freescale Semiconductor
6868 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6870 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6872 - * This file is dual-licensed: you can use it either under the terms
6873 - * of the GPL or the X11 license, at your option. Note that this dual
6874 - * licensing only applies to this file, and not this project as a
6877 - * a) This library is free software; you can redistribute it and/or
6878 - * modify it under the terms of the GNU General Public License as
6879 - * published by the Free Software Foundation; either version 2 of the
6880 - * License, or (at your option) any later version.
6882 - * This library is distributed in the hope that it will be useful,
6883 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6884 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6885 - * GNU General Public License for more details.
6887 - * Or, alternatively,
6889 - * b) Permission is hereby granted, free of charge, to any person
6890 - * obtaining a copy of this software and associated documentation
6891 - * files (the "Software"), to deal in the Software without
6892 - * restriction, including without limitation the rights to use,
6893 - * copy, modify, merge, publish, distribute, sublicense, and/or
6894 - * sell copies of the Software, and to permit persons to whom the
6895 - * Software is furnished to do so, subject to the following
6898 - * The above copyright notice and this permission notice shall be
6899 - * included in all copies or substantial portions of the Software.
6901 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
6902 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
6903 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
6904 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
6905 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
6906 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
6907 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
6908 - * OTHER DEALINGS IN THE SOFTWARE.
6913 -/include/ "fsl-ls2080a.dtsi"
6914 +#include "fsl-ls2080a.dtsi"
6917 model = "Freescale Layerscape 2080a software Simulator model";
6918 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6921 - serial0 = &serial0;
6922 - serial1 = &serial1;
6926 compatible = "smsc,lan91c111";
6927 reg = <0x0 0x2210000 0x0 0x100>;
6928 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6929 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6931 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6933 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6935 - * Copyright (C) 2014-2015, Freescale Semiconductor
6936 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6938 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6939 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6941 - * This file is dual-licensed: you can use it either under the terms
6942 - * of the GPLv2 or the X11 license, at your option. Note that this dual
6943 - * licensing only applies to this file, and not this project as a
6946 - * a) This library is free software; you can redistribute it and/or
6947 - * modify it under the terms of the GNU General Public License as
6948 - * published by the Free Software Foundation; either version 2 of the
6949 - * License, or (at your option) any later version.
6951 - * This library is distributed in the hope that it will be useful,
6952 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6953 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6954 - * GNU General Public License for more details.
6956 - * Or, alternatively,
6958 - * b) Permission is hereby granted, free of charge, to any person
6959 - * obtaining a copy of this software and associated documentation
6960 - * files (the "Software"), to deal in the Software without
6961 - * restriction, including without limitation the rights to use,
6962 - * copy, modify, merge, publish, distribute, sublicense, and/or
6963 - * sell copies of the Software, and to permit persons to whom the
6964 - * Software is furnished to do so, subject to the following
6967 - * The above copyright notice and this permission notice shall be
6968 - * included in all copies or substantial portions of the Software.
6970 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
6971 - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
6972 - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
6973 - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
6974 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
6975 - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
6976 - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
6977 - * OTHER DEALINGS IN THE SOFTWARE.
6981 - compatible = "fsl,ls2080a";
6982 - interrupt-parent = <&gic>;
6983 - #address-cells = <2>;
6984 - #size-cells = <2>;
6987 - #address-cells = <1>;
6988 - #size-cells = <0>;
6991 - * We expect the enable-method for cpu's to be "psci", but this
6992 - * is dependent on the SoC FW, which will fill this in.
6994 - * Currently supported enable-method is psci v0.2
6997 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6999 - device_type = "cpu";
7000 - compatible = "arm,cortex-a57";
7002 - clocks = <&clockgen 1 0>;
7003 - next-level-cache = <&cluster0_l2>;
7007 - device_type = "cpu";
7008 - compatible = "arm,cortex-a57";
7010 - clocks = <&clockgen 1 0>;
7011 - next-level-cache = <&cluster0_l2>;
7015 - device_type = "cpu";
7016 - compatible = "arm,cortex-a57";
7018 - clocks = <&clockgen 1 1>;
7019 - next-level-cache = <&cluster1_l2>;
7023 - device_type = "cpu";
7024 - compatible = "arm,cortex-a57";
7026 - clocks = <&clockgen 1 1>;
7027 - next-level-cache = <&cluster1_l2>;
7031 - device_type = "cpu";
7032 - compatible = "arm,cortex-a57";
7034 - clocks = <&clockgen 1 2>;
7035 - next-level-cache = <&cluster2_l2>;
7039 - device_type = "cpu";
7040 - compatible = "arm,cortex-a57";
7042 - clocks = <&clockgen 1 2>;
7043 - next-level-cache = <&cluster2_l2>;
7047 - device_type = "cpu";
7048 - compatible = "arm,cortex-a57";
7050 - clocks = <&clockgen 1 3>;
7051 - next-level-cache = <&cluster3_l2>;
7055 - device_type = "cpu";
7056 - compatible = "arm,cortex-a57";
7058 - clocks = <&clockgen 1 3>;
7059 - next-level-cache = <&cluster3_l2>;
7062 - cluster0_l2: l2-cache0 {
7063 - compatible = "cache";
7066 - cluster1_l2: l2-cache1 {
7067 - compatible = "cache";
7070 - cluster2_l2: l2-cache2 {
7071 - compatible = "cache";
7074 - cluster3_l2: l2-cache3 {
7075 - compatible = "cache";
7080 - device_type = "memory";
7081 - reg = <0x00000000 0x80000000 0 0x80000000>;
7082 - /* DRAM space - 1, size : 2 GB DRAM */
7086 - compatible = "fixed-clock";
7087 - #clock-cells = <0>;
7088 - clock-frequency = <100000000>;
7089 - clock-output-names = "sysclk";
7092 - gic: interrupt-controller@6000000 {
7093 - compatible = "arm,gic-v3";
7094 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
7095 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
7096 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
7097 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
7098 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
7099 - #interrupt-cells = <3>;
7100 - #address-cells = <2>;
7101 - #size-cells = <2>;
7103 - interrupt-controller;
7104 - interrupts = <1 9 0x4>;
7106 - its: gic-its@6020000 {
7107 - compatible = "arm,gic-v3-its";
7109 - reg = <0x0 0x6020000 0 0x20000>;
7113 - rstcr: syscon@1e60000 {
7114 - compatible = "fsl,ls2080a-rstcr", "syscon";
7115 - reg = <0x0 0x1e60000 0x0 0x4>;
7119 - compatible ="syscon-reboot";
7120 - regmap = <&rstcr>;
7126 - compatible = "arm,armv8-timer";
7127 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
7128 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
7129 - <1 11 4>, /* Virtual PPI, active-low */
7130 - <1 10 4>; /* Hypervisor PPI, active-low */
7131 - fsl,erratum-a008585;
7135 - compatible = "arm,armv8-pmuv3";
7136 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
7140 - compatible = "simple-bus";
7141 - #address-cells = <2>;
7142 - #size-cells = <2>;
7145 - clockgen: clocking@1300000 {
7146 - compatible = "fsl,ls2080a-clockgen";
7147 - reg = <0 0x1300000 0 0xa0000>;
7148 - #clock-cells = <2>;
7149 - clocks = <&sysclk>;
7152 - serial0: serial@21c0500 {
7153 - compatible = "fsl,ns16550", "ns16550a";
7154 - reg = <0x0 0x21c0500 0x0 0x100>;
7155 - clocks = <&clockgen 4 3>;
7156 - interrupts = <0 32 0x4>; /* Level high type */
7159 - serial1: serial@21c0600 {
7160 - compatible = "fsl,ns16550", "ns16550a";
7161 - reg = <0x0 0x21c0600 0x0 0x100>;
7162 - clocks = <&clockgen 4 3>;
7163 - interrupts = <0 32 0x4>; /* Level high type */
7166 - cluster1_core0_watchdog: wdt@c000000 {
7167 - compatible = "arm,sp805-wdt", "arm,primecell";
7168 - reg = <0x0 0xc000000 0x0 0x1000>;
7169 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7170 - clock-names = "apb_pclk", "wdog_clk";
7173 - cluster1_core1_watchdog: wdt@c010000 {
7174 - compatible = "arm,sp805-wdt", "arm,primecell";
7175 - reg = <0x0 0xc010000 0x0 0x1000>;
7176 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7177 - clock-names = "apb_pclk", "wdog_clk";
7180 - cluster2_core0_watchdog: wdt@c100000 {
7181 - compatible = "arm,sp805-wdt", "arm,primecell";
7182 - reg = <0x0 0xc100000 0x0 0x1000>;
7183 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7184 - clock-names = "apb_pclk", "wdog_clk";
7187 - cluster2_core1_watchdog: wdt@c110000 {
7188 - compatible = "arm,sp805-wdt", "arm,primecell";
7189 - reg = <0x0 0xc110000 0x0 0x1000>;
7190 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7191 - clock-names = "apb_pclk", "wdog_clk";
7194 - cluster3_core0_watchdog: wdt@c200000 {
7195 - compatible = "arm,sp805-wdt", "arm,primecell";
7196 - reg = <0x0 0xc200000 0x0 0x1000>;
7197 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7198 - clock-names = "apb_pclk", "wdog_clk";
7201 - cluster3_core1_watchdog: wdt@c210000 {
7202 - compatible = "arm,sp805-wdt", "arm,primecell";
7203 - reg = <0x0 0xc210000 0x0 0x1000>;
7204 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7205 - clock-names = "apb_pclk", "wdog_clk";
7208 - cluster4_core0_watchdog: wdt@c300000 {
7209 - compatible = "arm,sp805-wdt", "arm,primecell";
7210 - reg = <0x0 0xc300000 0x0 0x1000>;
7211 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7212 - clock-names = "apb_pclk", "wdog_clk";
7215 - cluster4_core1_watchdog: wdt@c310000 {
7216 - compatible = "arm,sp805-wdt", "arm,primecell";
7217 - reg = <0x0 0xc310000 0x0 0x1000>;
7218 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7219 - clock-names = "apb_pclk", "wdog_clk";
7222 - fsl_mc: fsl-mc@80c000000 {
7223 - compatible = "fsl,qoriq-mc";
7224 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
7225 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
7226 - msi-parent = <&its>;
7227 - #address-cells = <3>;
7228 - #size-cells = <1>;
7231 - * Region type 0x0 - MC portals
7232 - * Region type 0x1 - QBMAN portals
7234 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
7235 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
7238 - * Define the maximum number of MACs present on the SoC.
7241 - #address-cells = <1>;
7242 - #size-cells = <0>;
7245 - compatible = "fsl,qoriq-mc-dpmac";
7250 - compatible = "fsl,qoriq-mc-dpmac";
7255 - compatible = "fsl,qoriq-mc-dpmac";
7260 - compatible = "fsl,qoriq-mc-dpmac";
7265 - compatible = "fsl,qoriq-mc-dpmac";
7270 - compatible = "fsl,qoriq-mc-dpmac";
7275 - compatible = "fsl,qoriq-mc-dpmac";
7280 - compatible = "fsl,qoriq-mc-dpmac";
7285 - compatible = "fsl,qoriq-mc-dpmac";
7289 - dpmac10: dpmac@a {
7290 - compatible = "fsl,qoriq-mc-dpmac";
7294 - dpmac11: dpmac@b {
7295 - compatible = "fsl,qoriq-mc-dpmac";
7299 - dpmac12: dpmac@c {
7300 - compatible = "fsl,qoriq-mc-dpmac";
7304 - dpmac13: dpmac@d {
7305 - compatible = "fsl,qoriq-mc-dpmac";
7309 - dpmac14: dpmac@e {
7310 - compatible = "fsl,qoriq-mc-dpmac";
7314 - dpmac15: dpmac@f {
7315 - compatible = "fsl,qoriq-mc-dpmac";
7319 - dpmac16: dpmac@10 {
7320 - compatible = "fsl,qoriq-mc-dpmac";
7326 - smmu: iommu@5000000 {
7327 - compatible = "arm,mmu-500";
7328 - reg = <0 0x5000000 0 0x800000>;
7329 - #global-interrupts = <12>;
7330 - interrupts = <0 13 4>, /* global secure fault */
7331 - <0 14 4>, /* combined secure interrupt */
7332 - <0 15 4>, /* global non-secure fault */
7333 - <0 16 4>, /* combined non-secure interrupt */
7334 - /* performance counter interrupts 0-7 */
7335 - <0 211 4>, <0 212 4>,
7336 - <0 213 4>, <0 214 4>,
7337 - <0 215 4>, <0 216 4>,
7338 - <0 217 4>, <0 218 4>,
7339 - /* per context interrupt, 64 interrupts */
7340 - <0 146 4>, <0 147 4>,
7341 - <0 148 4>, <0 149 4>,
7342 - <0 150 4>, <0 151 4>,
7343 - <0 152 4>, <0 153 4>,
7344 - <0 154 4>, <0 155 4>,
7345 - <0 156 4>, <0 157 4>,
7346 - <0 158 4>, <0 159 4>,
7347 - <0 160 4>, <0 161 4>,
7348 - <0 162 4>, <0 163 4>,
7349 - <0 164 4>, <0 165 4>,
7350 - <0 166 4>, <0 167 4>,
7351 - <0 168 4>, <0 169 4>,
7352 - <0 170 4>, <0 171 4>,
7353 - <0 172 4>, <0 173 4>,
7354 - <0 174 4>, <0 175 4>,
7355 - <0 176 4>, <0 177 4>,
7356 - <0 178 4>, <0 179 4>,
7357 - <0 180 4>, <0 181 4>,
7358 - <0 182 4>, <0 183 4>,
7359 - <0 184 4>, <0 185 4>,
7360 - <0 186 4>, <0 187 4>,
7361 - <0 188 4>, <0 189 4>,
7362 - <0 190 4>, <0 191 4>,
7363 - <0 192 4>, <0 193 4>,
7364 - <0 194 4>, <0 195 4>,
7365 - <0 196 4>, <0 197 4>,
7366 - <0 198 4>, <0 199 4>,
7367 - <0 200 4>, <0 201 4>,
7368 - <0 202 4>, <0 203 4>,
7369 - <0 204 4>, <0 205 4>,
7370 - <0 206 4>, <0 207 4>,
7371 - <0 208 4>, <0 209 4>;
7372 - mmu-masters = <&fsl_mc 0x300 0>;
7375 - dspi: dspi@2100000 {
7376 - status = "disabled";
7377 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
7378 - #address-cells = <1>;
7379 - #size-cells = <0>;
7380 - reg = <0x0 0x2100000 0x0 0x10000>;
7381 - interrupts = <0 26 0x4>; /* Level high type */
7382 - clocks = <&clockgen 4 3>;
7383 - clock-names = "dspi";
7384 - spi-num-chipselects = <5>;
7388 - esdhc: esdhc@2140000 {
7389 - status = "disabled";
7390 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
7391 - reg = <0x0 0x2140000 0x0 0x10000>;
7392 - interrupts = <0 28 0x4>; /* Level high type */
7393 - clock-frequency = <0>; /* Updated by bootloader */
7394 - voltage-ranges = <1800 1800 3300 3300>;
7400 - gpio0: gpio@2300000 {
7401 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7402 - reg = <0x0 0x2300000 0x0 0x10000>;
7403 - interrupts = <0 36 0x4>; /* Level high type */
7406 - #gpio-cells = <2>;
7407 - interrupt-controller;
7408 - #interrupt-cells = <2>;
7411 - gpio1: gpio@2310000 {
7412 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7413 - reg = <0x0 0x2310000 0x0 0x10000>;
7414 - interrupts = <0 36 0x4>; /* Level high type */
7417 - #gpio-cells = <2>;
7418 - interrupt-controller;
7419 - #interrupt-cells = <2>;
7422 - gpio2: gpio@2320000 {
7423 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7424 - reg = <0x0 0x2320000 0x0 0x10000>;
7425 - interrupts = <0 37 0x4>; /* Level high type */
7428 - #gpio-cells = <2>;
7429 - interrupt-controller;
7430 - #interrupt-cells = <2>;
7433 - gpio3: gpio@2330000 {
7434 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7435 - reg = <0x0 0x2330000 0x0 0x10000>;
7436 - interrupts = <0 37 0x4>; /* Level high type */
7439 - #gpio-cells = <2>;
7440 - interrupt-controller;
7441 - #interrupt-cells = <2>;
7444 - i2c0: i2c@2000000 {
7445 - status = "disabled";
7446 - compatible = "fsl,vf610-i2c";
7447 - #address-cells = <1>;
7448 - #size-cells = <0>;
7449 - reg = <0x0 0x2000000 0x0 0x10000>;
7450 - interrupts = <0 34 0x4>; /* Level high type */
7451 - clock-names = "i2c";
7452 - clocks = <&clockgen 4 3>;
7455 - i2c1: i2c@2010000 {
7456 - status = "disabled";
7457 - compatible = "fsl,vf610-i2c";
7458 - #address-cells = <1>;
7459 - #size-cells = <0>;
7460 - reg = <0x0 0x2010000 0x0 0x10000>;
7461 - interrupts = <0 34 0x4>; /* Level high type */
7462 - clock-names = "i2c";
7463 - clocks = <&clockgen 4 3>;
7466 - i2c2: i2c@2020000 {
7467 - status = "disabled";
7468 - compatible = "fsl,vf610-i2c";
7469 - #address-cells = <1>;
7470 - #size-cells = <0>;
7471 - reg = <0x0 0x2020000 0x0 0x10000>;
7472 - interrupts = <0 35 0x4>; /* Level high type */
7473 - clock-names = "i2c";
7474 - clocks = <&clockgen 4 3>;
7477 - i2c3: i2c@2030000 {
7478 - status = "disabled";
7479 - compatible = "fsl,vf610-i2c";
7480 - #address-cells = <1>;
7481 - #size-cells = <0>;
7482 - reg = <0x0 0x2030000 0x0 0x10000>;
7483 - interrupts = <0 35 0x4>; /* Level high type */
7484 - clock-names = "i2c";
7485 - clocks = <&clockgen 4 3>;
7488 - ifc: ifc@2240000 {
7489 - compatible = "fsl,ifc", "simple-bus";
7490 - reg = <0x0 0x2240000 0x0 0x20000>;
7491 - interrupts = <0 21 0x4>; /* Level high type */
7493 - #address-cells = <2>;
7494 - #size-cells = <1>;
7496 - ranges = <0 0 0x5 0x80000000 0x08000000
7497 - 2 0 0x5 0x30000000 0x00010000
7498 - 3 0 0x5 0x20000000 0x00010000>;
7501 - qspi: quadspi@20c0000 {
7502 - status = "disabled";
7503 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
7504 - #address-cells = <1>;
7505 - #size-cells = <0>;
7506 - reg = <0x0 0x20c0000 0x0 0x10000>,
7507 - <0x0 0x20000000 0x0 0x10000000>;
7508 - reg-names = "QuadSPI", "QuadSPI-memory";
7509 - interrupts = <0 25 0x4>; /* Level high type */
7510 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7511 - clock-names = "qspi_en", "qspi";
7515 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7517 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7518 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7519 - reg-names = "regs", "config";
7520 - interrupts = <0 108 0x4>; /* Level high type */
7521 - interrupt-names = "intr";
7522 - #address-cells = <3>;
7523 - #size-cells = <2>;
7524 - device_type = "pci";
7527 - bus-range = <0x0 0xff>;
7528 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7529 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7530 - msi-parent = <&its>;
7531 - #interrupt-cells = <1>;
7532 - interrupt-map-mask = <0 0 0 7>;
7533 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
7534 - <0000 0 0 2 &gic 0 0 0 110 4>,
7535 - <0000 0 0 3 &gic 0 0 0 111 4>,
7536 - <0000 0 0 4 &gic 0 0 0 112 4>;
7540 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7542 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7543 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7544 - reg-names = "regs", "config";
7545 - interrupts = <0 113 0x4>; /* Level high type */
7546 - interrupt-names = "intr";
7547 - #address-cells = <3>;
7548 - #size-cells = <2>;
7549 - device_type = "pci";
7552 - bus-range = <0x0 0xff>;
7553 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7554 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7555 - msi-parent = <&its>;
7556 - #interrupt-cells = <1>;
7557 - interrupt-map-mask = <0 0 0 7>;
7558 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7559 - <0000 0 0 2 &gic 0 0 0 115 4>,
7560 - <0000 0 0 3 &gic 0 0 0 116 4>,
7561 - <0000 0 0 4 &gic 0 0 0 117 4>;
7565 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7567 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7568 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7569 - reg-names = "regs", "config";
7570 - interrupts = <0 118 0x4>; /* Level high type */
7571 - interrupt-names = "intr";
7572 - #address-cells = <3>;
7573 - #size-cells = <2>;
7574 - device_type = "pci";
7577 - bus-range = <0x0 0xff>;
7578 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7579 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7580 - msi-parent = <&its>;
7581 - #interrupt-cells = <1>;
7582 - interrupt-map-mask = <0 0 0 7>;
7583 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7584 - <0000 0 0 2 &gic 0 0 0 120 4>,
7585 - <0000 0 0 3 &gic 0 0 0 121 4>,
7586 - <0000 0 0 4 &gic 0 0 0 122 4>;
7590 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7592 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7593 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7594 - reg-names = "regs", "config";
7595 - interrupts = <0 123 0x4>; /* Level high type */
7596 - interrupt-names = "intr";
7597 - #address-cells = <3>;
7598 - #size-cells = <2>;
7599 - device_type = "pci";
7602 - bus-range = <0x0 0xff>;
7603 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7604 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7605 - msi-parent = <&its>;
7606 - #interrupt-cells = <1>;
7607 - interrupt-map-mask = <0 0 0 7>;
7608 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7609 - <0000 0 0 2 &gic 0 0 0 125 4>,
7610 - <0000 0 0 3 &gic 0 0 0 126 4>,
7611 - <0000 0 0 4 &gic 0 0 0 127 4>;
7614 - sata0: sata@3200000 {
7615 - status = "disabled";
7616 - compatible = "fsl,ls2080a-ahci";
7617 - reg = <0x0 0x3200000 0x0 0x10000>;
7618 - interrupts = <0 133 0x4>; /* Level high type */
7619 - clocks = <&clockgen 4 3>;
7623 - sata1: sata@3210000 {
7624 - status = "disabled";
7625 - compatible = "fsl,ls2080a-ahci";
7626 - reg = <0x0 0x3210000 0x0 0x10000>;
7627 - interrupts = <0 136 0x4>; /* Level high type */
7628 - clocks = <&clockgen 4 3>;
7632 - usb0: usb3@3100000 {
7633 - status = "disabled";
7634 - compatible = "snps,dwc3";
7635 - reg = <0x0 0x3100000 0x0 0x10000>;
7636 - interrupts = <0 80 0x4>; /* Level high type */
7638 - snps,quirk-frame-length-adjustment = <0x20>;
7639 - snps,dis_rxdet_inp3_quirk;
7642 - usb1: usb3@3110000 {
7643 - status = "disabled";
7644 - compatible = "snps,dwc3";
7645 - reg = <0x0 0x3110000 0x0 0x10000>;
7646 - interrupts = <0 81 0x4>; /* Level high type */
7648 - snps,quirk-frame-length-adjustment = <0x20>;
7649 - snps,dis_rxdet_inp3_quirk;
7653 - compatible = "arm,ccn-504";
7654 - reg = <0x0 0x04000000 0x0 0x01000000>;
7655 - interrupts = <0 12 4>;
7659 - ddr1: memory-controller@1080000 {
7660 - compatible = "fsl,qoriq-memory-controller";
7661 - reg = <0x0 0x1080000 0x0 0x1000>;
7662 - interrupts = <0 17 0x4>;
7666 - ddr2: memory-controller@1090000 {
7667 - compatible = "fsl,qoriq-memory-controller";
7668 - reg = <0x0 0x1090000 0x0 0x1000>;
7669 - interrupts = <0 18 0x4>;
7671 +#include "fsl-ls208xa.dtsi"
7675 + device_type = "cpu";
7676 + compatible = "arm,cortex-a57";
7678 + clocks = <&clockgen 1 0>;
7679 + next-level-cache = <&cluster0_l2>;
7680 + #cooling-cells = <2>;
7684 + device_type = "cpu";
7685 + compatible = "arm,cortex-a57";
7687 + clocks = <&clockgen 1 0>;
7688 + next-level-cache = <&cluster0_l2>;
7692 + device_type = "cpu";
7693 + compatible = "arm,cortex-a57";
7695 + clocks = <&clockgen 1 1>;
7696 + next-level-cache = <&cluster1_l2>;
7697 + #cooling-cells = <2>;
7701 + device_type = "cpu";
7702 + compatible = "arm,cortex-a57";
7704 + clocks = <&clockgen 1 1>;
7705 + next-level-cache = <&cluster1_l2>;
7709 + device_type = "cpu";
7710 + compatible = "arm,cortex-a57";
7712 + clocks = <&clockgen 1 2>;
7713 + next-level-cache = <&cluster2_l2>;
7714 + #cooling-cells = <2>;
7718 + device_type = "cpu";
7719 + compatible = "arm,cortex-a57";
7721 + clocks = <&clockgen 1 2>;
7722 + next-level-cache = <&cluster2_l2>;
7726 + device_type = "cpu";
7727 + compatible = "arm,cortex-a57";
7729 + clocks = <&clockgen 1 3>;
7730 + next-level-cache = <&cluster3_l2>;
7731 + #cooling-cells = <2>;
7735 + device_type = "cpu";
7736 + compatible = "arm,cortex-a57";
7738 + clocks = <&clockgen 1 3>;
7739 + next-level-cache = <&cluster3_l2>;
7742 + cluster0_l2: l2-cache0 {
7743 + compatible = "cache";
7746 + cluster1_l2: l2-cache1 {
7747 + compatible = "cache";
7750 + cluster2_l2: l2-cache2 {
7751 + compatible = "cache";
7754 + cluster3_l2: l2-cache3 {
7755 + compatible = "cache";
7760 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7761 + snps,dma-snooping;
7765 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7766 + snps,dma-snooping;
7770 + fsl,erratum-a008585;
7774 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7775 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7777 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7778 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7782 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7783 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7785 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7786 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7790 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7791 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7793 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7794 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7798 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7799 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7801 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7802 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7805 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7808 + * Device Tree file for NXP LS2081A RDB Board.
7810 + * Copyright 2017 NXP
7812 + * Priyanka Jain <priyanka.jain@nxp.com>
7814 + * This file is dual-licensed: you can use it either under the terms
7815 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7816 + * licensing only applies to this file, and not this project as a
7819 + * a) This library is free software; you can redistribute it and/or
7820 + * modify it under the terms of the GNU General Public License as
7821 + * published by the Free Software Foundation; either version 2 of the
7822 + * License, or (at your option) any later version.
7824 + * This library is distributed in the hope that it will be useful,
7825 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7826 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7827 + * GNU General Public License for more details.
7829 + * Or, alternatively,
7831 + * b) Permission is hereby granted, free of charge, to any person
7832 + * obtaining a copy of this software and associated documentation
7833 + * files (the "Software"), to deal in the Software without
7834 + * restriction, including without limitation the rights to use,
7835 + * copy, modify, merge, publish, distribute, sublicense, and/or
7836 + * sell copies of the Software, and to permit persons to whom the
7837 + * Software is furnished to do so, subject to the following
7840 + * The above copyright notice and this permission notice shall be
7841 + * included in all copies or substantial portions of the Software.
7843 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7844 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7845 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7846 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7847 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7848 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7849 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7850 + * OTHER DEALINGS IN THE SOFTWARE.
7855 +#include "fsl-ls2088a.dtsi"
7858 + model = "NXP Layerscape 2081A RDB Board";
7859 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7862 + serial0 = &serial0;
7863 + serial1 = &serial1;
7867 + stdout-path = "serial1:115200n8";
7876 + status = "disabled";
7882 + compatible = "nxp,pca9547";
7884 + #address-cells = <1>;
7885 + #size-cells = <0>;
7887 + #address-cells = <1>;
7888 + #size-cells = <0>;
7891 + compatible = "nxp,pcf2129";
7897 + #address-cells = <1>;
7898 + #size-cells = <0>;
7902 + compatible = "ti,ina220";
7904 + shunt-resistor = <500>;
7909 + #address-cells = <1>;
7910 + #size-cells = <0>;
7914 + compatible = "adi,adt7461";
7923 + dflash0: n25q512a {
7924 + #address-cells = <1>;
7925 + #size-cells = <1>;
7926 + compatible = "st,m25p80";
7927 + spi-max-frequency = <3000000>;
7934 + fsl,qspi-has-second-chip;
7935 + flash0: s25fs512s@0 {
7936 + #address-cells = <1>;
7937 + #size-cells = <1>;
7938 + compatible = "spansion,m25p80";
7940 + spi-max-frequency = <20000000>;
7943 + flash1: s25fs512s@1 {
7944 + #address-cells = <1>;
7945 + #size-cells = <1>;
7946 + compatible = "spansion,m25p80";
7948 + spi-max-frequency = <20000000>;
7969 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7971 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7973 + * Device Tree file for Freescale LS2088A QDS Board.
7975 + * Copyright 2016 Freescale Semiconductor, Inc.
7976 + * Copyright 2017 NXP
7978 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7984 +#include "fsl-ls2088a.dtsi"
7985 +#include "fsl-ls208xa-qds.dtsi"
7988 + model = "Freescale Layerscape 2088A QDS Board";
7989 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7992 + stdout-path = "serial0:115200n8";
7997 + boardctrl: board-control@3,0 {
7998 + #address-cells = <1>;
7999 + #size-cells = <1>;
8000 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
8001 + reg = <3 0 0x300>; /* TODO check address */
8002 + ranges = <0 3 0 0x300>;
8005 + compatible = "mdio-mux-mmioreg", "mdio-mux";
8006 + mdio-parent-bus = <&emdio1>;
8007 + reg = <0x54 1>; /* BRDCFG4 */
8008 + mux-mask = <0xe0>; /* EMI1_MDIO */
8010 + #address-cells=<1>;
8011 + #size-cells = <0>;
8013 + /* Child MDIO buses, one for each riser card:
8014 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
8015 + * VSC8234 PHYs on the riser cards.
8018 + mdio_mux3: mdio@60 {
8020 + #address-cells = <1>;
8021 + #size-cells = <0>;
8023 + mdio0_phy12: mdio_phy0@1c {
8025 + phy-connection-type = "sgmii";
8027 + mdio0_phy13: mdio_phy1@1d {
8029 + phy-connection-type = "sgmii";
8031 + mdio0_phy14: mdio_phy2@1e {
8033 + phy-connection-type = "sgmii";
8035 + mdio0_phy15: mdio_phy3@1f {
8037 + phy-connection-type = "sgmii";
8045 + pcs_phy1: ethernet-phy@0 {
8046 + backplane-mode = "10gbase-kr";
8047 + compatible = "ethernet-phy-ieee802.3-c45";
8049 + fsl,lane-handle = <&serdes1>;
8050 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
8055 + pcs_phy2: ethernet-phy@0 {
8056 + backplane-mode = "10gbase-kr";
8057 + compatible = "ethernet-phy-ieee802.3-c45";
8059 + fsl,lane-handle = <&serdes1>;
8060 + fsl,lane-reg = <0x980 0x40>;/* lane G */
8065 + pcs_phy3: ethernet-phy@0 {
8066 + backplane-mode = "10gbase-kr";
8067 + compatible = "ethernet-phy-ieee802.3-c45";
8069 + fsl,lane-handle = <&serdes1>;
8070 + fsl,lane-reg = <0x940 0x40>;/* lane F */
8075 + pcs_phy4: ethernet-phy@0 {
8076 + backplane-mode = "10gbase-kr";
8077 + compatible = "ethernet-phy-ieee802.3-c45";
8079 + fsl,lane-handle = <&serdes1>;
8080 + fsl,lane-reg = <0x900 0x40>;/* lane E */
8084 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
8086 + phy-handle = <&mdio0_phy12>;
8089 + phy-handle = <&mdio0_phy13>;
8092 + phy-handle = <&mdio0_phy14>;
8095 + phy-handle = <&mdio0_phy15>;
8098 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
8100 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8102 + * Device Tree file for Freescale LS2088A RDB Board.
8104 + * Copyright 2016 Freescale Semiconductor, Inc.
8105 + * Copyright 2017 NXP
8107 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8113 +#include "fsl-ls2088a.dtsi"
8114 +#include "fsl-ls208xa-rdb.dtsi"
8117 + model = "Freescale Layerscape 2088A RDB Board";
8118 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
8121 + stdout-path = "serial1:115200n8";
8126 + status = "disabled";
8128 + mdio1_phy1: emdio1_phy@1 {
8130 + phy-connection-type = "xfi";
8132 + mdio1_phy2: emdio1_phy@2 {
8134 + phy-connection-type = "xfi";
8136 + mdio1_phy3: emdio1_phy@3 {
8138 + phy-connection-type = "xfi";
8140 + mdio1_phy4: emdio1_phy@4 {
8142 + phy-connection-type = "xfi";
8148 + mdio2_phy1: emdio2_phy@1 {
8149 + compatible = "ethernet-phy-ieee802.3-c45";
8150 + interrupts = <0 1 0x4>; /* Level high type */
8152 + phy-connection-type = "xfi";
8154 + mdio2_phy2: emdio2_phy@2 {
8155 + compatible = "ethernet-phy-ieee802.3-c45";
8156 + interrupts = <0 2 0x4>; /* Level high type */
8158 + phy-connection-type = "xfi";
8160 + mdio2_phy3: emdio2_phy@3 {
8161 + compatible = "ethernet-phy-ieee802.3-c45";
8162 + interrupts = <0 4 0x4>; /* Level high type */
8164 + phy-connection-type = "xfi";
8166 + mdio2_phy4: emdio2_phy@4 {
8167 + compatible = "ethernet-phy-ieee802.3-c45";
8168 + interrupts = <0 5 0x4>; /* Level high type */
8170 + phy-connection-type = "xfi";
8174 +/* Update DPMAC connections to external PHYs, under the assumption of
8175 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
8177 +/* Leave Cortina PHYs commented out until proper driver is integrated
8179 + * phy-handle = <&mdio1_phy1>;
8182 + * phy-handle = <&mdio1_phy2>;
8185 + * phy-handle = <&mdio1_phy3>;
8188 + * phy-handle = <&mdio1_phy4>;
8193 + phy-handle = <&mdio2_phy1>;
8196 + phy-handle = <&mdio2_phy2>;
8199 + phy-handle = <&mdio2_phy3>;
8202 + phy-handle = <&mdio2_phy4>;
8205 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
8207 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8209 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
8211 + * Copyright 2016 Freescale Semiconductor, Inc.
8212 + * Copyright 2017 NXP
8214 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8218 +#include "fsl-ls208xa.dtsi"
8222 + device_type = "cpu";
8223 + compatible = "arm,cortex-a72";
8225 + clocks = <&clockgen 1 0>;
8226 + next-level-cache = <&cluster0_l2>;
8227 + #cooling-cells = <2>;
8228 + cpu-idle-states = <&CPU_PH20>;
8232 + device_type = "cpu";
8233 + compatible = "arm,cortex-a72";
8235 + clocks = <&clockgen 1 0>;
8236 + next-level-cache = <&cluster0_l2>;
8237 + cpu-idle-states = <&CPU_PH20>;
8241 + device_type = "cpu";
8242 + compatible = "arm,cortex-a72";
8244 + clocks = <&clockgen 1 1>;
8245 + next-level-cache = <&cluster1_l2>;
8246 + #cooling-cells = <2>;
8247 + cpu-idle-states = <&CPU_PH20>;
8251 + device_type = "cpu";
8252 + compatible = "arm,cortex-a72";
8254 + clocks = <&clockgen 1 1>;
8255 + next-level-cache = <&cluster1_l2>;
8256 + cpu-idle-states = <&CPU_PH20>;
8260 + device_type = "cpu";
8261 + compatible = "arm,cortex-a72";
8263 + clocks = <&clockgen 1 2>;
8264 + next-level-cache = <&cluster2_l2>;
8265 + #cooling-cells = <2>;
8266 + cpu-idle-states = <&CPU_PH20>;
8270 + device_type = "cpu";
8271 + compatible = "arm,cortex-a72";
8273 + clocks = <&clockgen 1 2>;
8274 + next-level-cache = <&cluster2_l2>;
8275 + cpu-idle-states = <&CPU_PH20>;
8279 + device_type = "cpu";
8280 + compatible = "arm,cortex-a72";
8282 + clocks = <&clockgen 1 3>;
8283 + next-level-cache = <&cluster3_l2>;
8284 + #cooling-cells = <2>;
8285 + cpu-idle-states = <&CPU_PH20>;
8289 + device_type = "cpu";
8290 + compatible = "arm,cortex-a72";
8292 + clocks = <&clockgen 1 3>;
8293 + next-level-cache = <&cluster3_l2>;
8294 + cpu-idle-states = <&CPU_PH20>;
8299 + * PSCI node is not added default, U-boot will add missing
8300 + * parts if it determines to use PSCI.
8302 + entry-method = "arm,psci";
8304 + CPU_PH20: cpu-ph20 {
8305 + compatible = "arm,idle-state";
8306 + idle-state-name = "PH20";
8307 + arm,psci-suspend-param = <0x0>;
8308 + entry-latency-us = <1000>;
8309 + exit-latency-us = <1000>;
8310 + min-residency-us = <3000>;
8314 + cluster0_l2: l2-cache0 {
8315 + compatible = "cache";
8318 + cluster1_l2: l2-cache1 {
8319 + compatible = "cache";
8322 + cluster2_l2: l2-cache2 {
8323 + compatible = "cache";
8326 + cluster3_l2: l2-cache3 {
8327 + compatible = "cache";
8332 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8333 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
8334 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
8336 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
8337 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
8341 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8342 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
8343 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
8345 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
8346 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
8350 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8351 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
8352 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
8354 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
8355 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
8359 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8360 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
8361 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
8363 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
8364 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
8367 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
8369 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8371 + * Device Tree file for Freescale LS2080A QDS Board.
8373 + * Copyright 2016 Freescale Semiconductor, Inc.
8374 + * Copyright 2017 NXP
8376 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8387 + #address-cells = <2>;
8388 + #size-cells = <1>;
8389 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8390 + 0x2 0x0 0x5 0x30000000 0x00010000
8391 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8394 + #address-cells = <1>;
8395 + #size-cells = <1>;
8396 + compatible = "cfi-flash";
8397 + reg = <0x0 0x0 0x8000000>;
8399 + device-width = <1>;
8403 + compatible = "fsl,ifc-nand";
8404 + reg = <0x2 0x0 0x10000>;
8408 + reg = <0x3 0x0 0x10000>;
8409 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8416 + compatible = "nxp,pca9547";
8418 + #address-cells = <1>;
8419 + #size-cells = <0>;
8421 + #address-cells = <1>;
8422 + #size-cells = <0>;
8425 + compatible = "dallas,ds3232";
8431 + #address-cells = <1>;
8432 + #size-cells = <0>;
8436 + compatible = "ti,ina220";
8438 + shunt-resistor = <500>;
8442 + compatible = "ti,ina220";
8444 + shunt-resistor = <1000>;
8449 + #address-cells = <1>;
8450 + #size-cells = <0>;
8454 + compatible = "adi,adt7461";
8462 + status = "disabled";
8466 + status = "disabled";
8470 + status = "disabled";
8475 + dflash0: n25q128a {
8476 + #address-cells = <1>;
8477 + #size-cells = <1>;
8478 + compatible = "st,m25p80";
8479 + spi-max-frequency = <3000000>;
8482 + dflash1: sst25wf040b {
8483 + #address-cells = <1>;
8484 + #size-cells = <1>;
8485 + compatible = "st,m25p80";
8486 + spi-max-frequency = <3000000>;
8489 + dflash2: en25s64 {
8490 + #address-cells = <1>;
8491 + #size-cells = <1>;
8492 + compatible = "st,m25p80";
8493 + spi-max-frequency = <3000000>;
8500 + flash0: s25fl256s1@0 {
8501 + #address-cells = <1>;
8502 + #size-cells = <1>;
8503 + compatible = "st,m25p80";
8504 + spi-max-frequency = <20000000>;
8507 + flash2: s25fl256s1@2 {
8508 + #address-cells = <1>;
8509 + #size-cells = <1>;
8510 + compatible = "st,m25p80";
8511 + spi-max-frequency = <20000000>;
8532 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8534 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8536 + * Device Tree file for Freescale LS2080A RDB Board.
8538 + * Copyright 2016 Freescale Semiconductor, Inc.
8539 + * Copyright 2017 NXP
8541 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8551 + #address-cells = <2>;
8552 + #size-cells = <1>;
8553 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8554 + 0x2 0x0 0x5 0x30000000 0x00010000
8555 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8558 + #address-cells = <1>;
8559 + #size-cells = <1>;
8560 + compatible = "cfi-flash";
8561 + reg = <0x0 0x0 0x8000000>;
8563 + device-width = <1>;
8567 + compatible = "fsl,ifc-nand";
8568 + reg = <0x2 0x0 0x10000>;
8572 + reg = <0x3 0x0 0x10000>;
8573 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8581 + compatible = "nxp,pca9547";
8583 + #address-cells = <1>;
8584 + #size-cells = <0>;
8585 + i2c-mux-never-disable;
8587 + #address-cells = <1>;
8588 + #size-cells = <0>;
8591 + compatible = "dallas,ds3232";
8597 + #address-cells = <1>;
8598 + #size-cells = <0>;
8601 + compatible = "ti,ina220";
8603 + shunt-resistor = <500>;
8608 + #address-cells = <1>;
8609 + #size-cells = <0>;
8613 + compatible = "adi,adt7461";
8621 + status = "disabled";
8625 + status = "disabled";
8629 + status = "disabled";
8634 + dflash0: n25q512a {
8635 + #address-cells = <1>;
8636 + #size-cells = <1>;
8637 + compatible = "st,m25p80";
8638 + spi-max-frequency = <3000000>;
8645 + flash0: s25fs512s@0 {
8646 + #address-cells = <1>;
8647 + #size-cells = <1>;
8648 + compatible = "spansion,m25p80";
8650 + spi-max-frequency = <20000000>;
8671 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8673 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8675 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8677 + * Copyright 2016 Freescale Semiconductor, Inc.
8678 + * Copyright 2017 NXP
8680 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8684 +#include <dt-bindings/thermal/thermal.h>
8685 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8688 + compatible = "fsl,ls2080a";
8689 + interrupt-parent = <&gic>;
8690 + #address-cells = <2>;
8691 + #size-cells = <2>;
8695 + serial0 = &serial0;
8696 + serial1 = &serial1;
8700 + #address-cells = <1>;
8701 + #size-cells = <0>;
8705 + device_type = "memory";
8706 + reg = <0x00000000 0x80000000 0 0x80000000>;
8707 + /* DRAM space - 1, size : 2 GB DRAM */
8711 + compatible = "fixed-clock";
8712 + #clock-cells = <0>;
8713 + clock-frequency = <100000000>;
8714 + clock-output-names = "sysclk";
8717 + gic: interrupt-controller@6000000 {
8718 + compatible = "arm,gic-v3";
8719 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8720 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8721 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8722 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8723 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8724 + #interrupt-cells = <3>;
8725 + #address-cells = <2>;
8726 + #size-cells = <2>;
8728 + interrupt-controller;
8729 + interrupts = <1 9 0x4>;
8731 + its: gic-its@6020000 {
8732 + compatible = "arm,gic-v3-its";
8734 + reg = <0x0 0x6020000 0 0x20000>;
8738 + rstcr: syscon@1e60000 {
8739 + compatible = "fsl,ls2080a-rstcr", "syscon";
8740 + reg = <0x0 0x1e60000 0x0 0x4>;
8744 + compatible ="syscon-reboot";
8745 + regmap = <&rstcr>;
8751 + compatible = "arm,armv8-timer";
8752 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8753 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8754 + <1 11 4>, /* Virtual PPI, active-low */
8755 + <1 10 4>; /* Hypervisor PPI, active-low */
8759 + compatible = "arm,armv8-pmuv3";
8760 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8764 + compatible = "simple-bus";
8765 + #address-cells = <2>;
8766 + #size-cells = <2>;
8768 + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
8770 + clockgen: clocking@1300000 {
8771 + compatible = "fsl,ls2080a-clockgen";
8772 + reg = <0 0x1300000 0 0xa0000>;
8773 + #clock-cells = <2>;
8774 + clocks = <&sysclk>;
8777 + dcfg: dcfg@1e00000 {
8778 + compatible = "fsl,ls2080a-dcfg", "syscon";
8779 + reg = <0x0 0x1e00000 0x0 0x10000>;
8783 + tmu: tmu@1f80000 {
8784 + compatible = "fsl,qoriq-tmu";
8785 + reg = <0x0 0x1f80000 0x0 0x10000>;
8786 + interrupts = <0 23 0x4>;
8787 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8788 + fsl,tmu-calibration = <0x00000000 0x00000026
8789 + 0x00000001 0x0000002d
8790 + 0x00000002 0x00000032
8791 + 0x00000003 0x00000039
8792 + 0x00000004 0x0000003f
8793 + 0x00000005 0x00000046
8794 + 0x00000006 0x0000004d
8795 + 0x00000007 0x00000054
8796 + 0x00000008 0x0000005a
8797 + 0x00000009 0x00000061
8798 + 0x0000000a 0x0000006a
8799 + 0x0000000b 0x00000071
8801 + 0x00010000 0x00000025
8802 + 0x00010001 0x0000002c
8803 + 0x00010002 0x00000035
8804 + 0x00010003 0x0000003d
8805 + 0x00010004 0x00000045
8806 + 0x00010005 0x0000004e
8807 + 0x00010006 0x00000057
8808 + 0x00010007 0x00000061
8809 + 0x00010008 0x0000006b
8810 + 0x00010009 0x00000076
8812 + 0x00020000 0x00000029
8813 + 0x00020001 0x00000033
8814 + 0x00020002 0x0000003d
8815 + 0x00020003 0x00000049
8816 + 0x00020004 0x00000056
8817 + 0x00020005 0x00000061
8818 + 0x00020006 0x0000006d
8820 + 0x00030000 0x00000021
8821 + 0x00030001 0x0000002a
8822 + 0x00030002 0x0000003c
8823 + 0x00030003 0x0000004e>;
8825 + #thermal-sensor-cells = <1>;
8829 + cpu_thermal: cpu-thermal {
8830 + polling-delay-passive = <1000>;
8831 + polling-delay = <5000>;
8833 + thermal-sensors = <&tmu 4>;
8836 + cpu_alert: cpu-alert {
8837 + temperature = <75000>;
8838 + hysteresis = <2000>;
8841 + cpu_crit: cpu-crit {
8842 + temperature = <85000>;
8843 + hysteresis = <2000>;
8844 + type = "critical";
8850 + trip = <&cpu_alert>;
8852 + <&cpu0 THERMAL_NO_LIMIT
8853 + THERMAL_NO_LIMIT>;
8856 + trip = <&cpu_alert>;
8858 + <&cpu2 THERMAL_NO_LIMIT
8859 + THERMAL_NO_LIMIT>;
8862 + trip = <&cpu_alert>;
8864 + <&cpu4 THERMAL_NO_LIMIT
8865 + THERMAL_NO_LIMIT>;
8868 + trip = <&cpu_alert>;
8870 + <&cpu6 THERMAL_NO_LIMIT
8871 + THERMAL_NO_LIMIT>;
8877 + serial0: serial@21c0500 {
8878 + compatible = "fsl,ns16550", "ns16550a";
8879 + reg = <0x0 0x21c0500 0x0 0x100>;
8880 + clocks = <&clockgen 4 3>;
8881 + interrupts = <0 32 0x4>; /* Level high type */
8884 + serial1: serial@21c0600 {
8885 + compatible = "fsl,ns16550", "ns16550a";
8886 + reg = <0x0 0x21c0600 0x0 0x100>;
8887 + clocks = <&clockgen 4 3>;
8888 + interrupts = <0 32 0x4>; /* Level high type */
8891 + cluster1_core0_watchdog: wdt@c000000 {
8892 + compatible = "arm,sp805-wdt", "arm,primecell";
8893 + reg = <0x0 0xc000000 0x0 0x1000>;
8894 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8895 + clock-names = "apb_pclk", "wdog_clk";
8898 + cluster1_core1_watchdog: wdt@c010000 {
8899 + compatible = "arm,sp805-wdt", "arm,primecell";
8900 + reg = <0x0 0xc010000 0x0 0x1000>;
8901 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8902 + clock-names = "apb_pclk", "wdog_clk";
8905 + cluster2_core0_watchdog: wdt@c100000 {
8906 + compatible = "arm,sp805-wdt", "arm,primecell";
8907 + reg = <0x0 0xc100000 0x0 0x1000>;
8908 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8909 + clock-names = "apb_pclk", "wdog_clk";
8912 + cluster2_core1_watchdog: wdt@c110000 {
8913 + compatible = "arm,sp805-wdt", "arm,primecell";
8914 + reg = <0x0 0xc110000 0x0 0x1000>;
8915 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8916 + clock-names = "apb_pclk", "wdog_clk";
8919 + cluster3_core0_watchdog: wdt@c200000 {
8920 + compatible = "arm,sp805-wdt", "arm,primecell";
8921 + reg = <0x0 0xc200000 0x0 0x1000>;
8922 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8923 + clock-names = "apb_pclk", "wdog_clk";
8926 + cluster3_core1_watchdog: wdt@c210000 {
8927 + compatible = "arm,sp805-wdt", "arm,primecell";
8928 + reg = <0x0 0xc210000 0x0 0x1000>;
8929 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8930 + clock-names = "apb_pclk", "wdog_clk";
8933 + cluster4_core0_watchdog: wdt@c300000 {
8934 + compatible = "arm,sp805-wdt", "arm,primecell";
8935 + reg = <0x0 0xc300000 0x0 0x1000>;
8936 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8937 + clock-names = "apb_pclk", "wdog_clk";
8940 + cluster4_core1_watchdog: wdt@c310000 {
8941 + compatible = "arm,sp805-wdt", "arm,primecell";
8942 + reg = <0x0 0xc310000 0x0 0x1000>;
8943 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8944 + clock-names = "apb_pclk", "wdog_clk";
8947 + crypto: crypto@8000000 {
8948 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8949 + fsl,sec-era = <8>;
8950 + #address-cells = <1>;
8951 + #size-cells = <1>;
8952 + ranges = <0x0 0x00 0x8000000 0x100000>;
8953 + reg = <0x00 0x8000000 0x0 0x100000>;
8954 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8957 + sec_jr0: jr@10000 {
8958 + compatible = "fsl,sec-v5.0-job-ring",
8959 + "fsl,sec-v4.0-job-ring";
8960 + reg = <0x10000 0x10000>;
8961 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8964 + sec_jr1: jr@20000 {
8965 + compatible = "fsl,sec-v5.0-job-ring",
8966 + "fsl,sec-v4.0-job-ring";
8967 + reg = <0x20000 0x10000>;
8968 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8971 + sec_jr2: jr@30000 {
8972 + compatible = "fsl,sec-v5.0-job-ring",
8973 + "fsl,sec-v4.0-job-ring";
8974 + reg = <0x30000 0x10000>;
8975 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8978 + sec_jr3: jr@40000 {
8979 + compatible = "fsl,sec-v5.0-job-ring",
8980 + "fsl,sec-v4.0-job-ring";
8981 + reg = <0x40000 0x10000>;
8982 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8986 + fsl_mc: fsl-mc@80c000000 {
8987 + compatible = "fsl,qoriq-mc";
8988 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8989 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8990 + msi-parent = <&its>;
8991 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8993 + #address-cells = <3>;
8994 + #size-cells = <1>;
8997 + * Region type 0x0 - MC portals
8998 + * Region type 0x1 - QBMAN portals
9000 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
9001 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
9004 + * Define the maximum number of MACs present on the SoC.
9007 + #address-cells = <1>;
9008 + #size-cells = <0>;
9011 + compatible = "fsl,qoriq-mc-dpmac";
9016 + compatible = "fsl,qoriq-mc-dpmac";
9021 + compatible = "fsl,qoriq-mc-dpmac";
9026 + compatible = "fsl,qoriq-mc-dpmac";
9031 + compatible = "fsl,qoriq-mc-dpmac";
9036 + compatible = "fsl,qoriq-mc-dpmac";
9041 + compatible = "fsl,qoriq-mc-dpmac";
9046 + compatible = "fsl,qoriq-mc-dpmac";
9051 + compatible = "fsl,qoriq-mc-dpmac";
9055 + dpmac10: dpmac@a {
9056 + compatible = "fsl,qoriq-mc-dpmac";
9060 + dpmac11: dpmac@b {
9061 + compatible = "fsl,qoriq-mc-dpmac";
9065 + dpmac12: dpmac@c {
9066 + compatible = "fsl,qoriq-mc-dpmac";
9070 + dpmac13: dpmac@d {
9071 + compatible = "fsl,qoriq-mc-dpmac";
9075 + dpmac14: dpmac@e {
9076 + compatible = "fsl,qoriq-mc-dpmac";
9080 + dpmac15: dpmac@f {
9081 + compatible = "fsl,qoriq-mc-dpmac";
9085 + dpmac16: dpmac@10 {
9086 + compatible = "fsl,qoriq-mc-dpmac";
9092 + smmu: iommu@5000000 {
9093 + compatible = "arm,mmu-500";
9094 + reg = <0 0x5000000 0 0x800000>;
9095 + #global-interrupts = <12>;
9096 + #iommu-cells = <1>;
9097 + stream-match-mask = <0x7C00>;
9098 + interrupts = <0 13 4>, /* global secure fault */
9099 + <0 14 4>, /* combined secure interrupt */
9100 + <0 15 4>, /* global non-secure fault */
9101 + <0 16 4>, /* combined non-secure interrupt */
9102 + /* performance counter interrupts 0-7 */
9103 + <0 211 4>, <0 212 4>,
9104 + <0 213 4>, <0 214 4>,
9105 + <0 215 4>, <0 216 4>,
9106 + <0 217 4>, <0 218 4>,
9107 + /* per context interrupt, 64 interrupts */
9108 + <0 146 4>, <0 147 4>,
9109 + <0 148 4>, <0 149 4>,
9110 + <0 150 4>, <0 151 4>,
9111 + <0 152 4>, <0 153 4>,
9112 + <0 154 4>, <0 155 4>,
9113 + <0 156 4>, <0 157 4>,
9114 + <0 158 4>, <0 159 4>,
9115 + <0 160 4>, <0 161 4>,
9116 + <0 162 4>, <0 163 4>,
9117 + <0 164 4>, <0 165 4>,
9118 + <0 166 4>, <0 167 4>,
9119 + <0 168 4>, <0 169 4>,
9120 + <0 170 4>, <0 171 4>,
9121 + <0 172 4>, <0 173 4>,
9122 + <0 174 4>, <0 175 4>,
9123 + <0 176 4>, <0 177 4>,
9124 + <0 178 4>, <0 179 4>,
9125 + <0 180 4>, <0 181 4>,
9126 + <0 182 4>, <0 183 4>,
9127 + <0 184 4>, <0 185 4>,
9128 + <0 186 4>, <0 187 4>,
9129 + <0 188 4>, <0 189 4>,
9130 + <0 190 4>, <0 191 4>,
9131 + <0 192 4>, <0 193 4>,
9132 + <0 194 4>, <0 195 4>,
9133 + <0 196 4>, <0 197 4>,
9134 + <0 198 4>, <0 199 4>,
9135 + <0 200 4>, <0 201 4>,
9136 + <0 202 4>, <0 203 4>,
9137 + <0 204 4>, <0 205 4>,
9138 + <0 206 4>, <0 207 4>,
9139 + <0 208 4>, <0 209 4>;
9142 + dspi: dspi@2100000 {
9143 + status = "disabled";
9144 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
9145 + #address-cells = <1>;
9146 + #size-cells = <0>;
9147 + reg = <0x0 0x2100000 0x0 0x10000>;
9148 + interrupts = <0 26 0x4>; /* Level high type */
9149 + clocks = <&clockgen 4 3>;
9150 + clock-names = "dspi";
9151 + spi-num-chipselects = <5>;
9155 + esdhc: esdhc@2140000 {
9156 + status = "disabled";
9157 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
9158 + reg = <0x0 0x2140000 0x0 0x10000>;
9159 + interrupts = <0 28 0x4>; /* Level high type */
9160 + clocks = <&clockgen 4 1>;
9161 + voltage-ranges = <1800 1800 3300 3300>;
9167 + gpio0: gpio@2300000 {
9168 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9169 + reg = <0x0 0x2300000 0x0 0x10000>;
9170 + interrupts = <0 36 0x4>; /* Level high type */
9173 + #gpio-cells = <2>;
9174 + interrupt-controller;
9175 + #interrupt-cells = <2>;
9178 + gpio1: gpio@2310000 {
9179 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9180 + reg = <0x0 0x2310000 0x0 0x10000>;
9181 + interrupts = <0 36 0x4>; /* Level high type */
9184 + #gpio-cells = <2>;
9185 + interrupt-controller;
9186 + #interrupt-cells = <2>;
9189 + gpio2: gpio@2320000 {
9190 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9191 + reg = <0x0 0x2320000 0x0 0x10000>;
9192 + interrupts = <0 37 0x4>; /* Level high type */
9195 + #gpio-cells = <2>;
9196 + interrupt-controller;
9197 + #interrupt-cells = <2>;
9200 + gpio3: gpio@2330000 {
9201 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
9202 + reg = <0x0 0x2330000 0x0 0x10000>;
9203 + interrupts = <0 37 0x4>; /* Level high type */
9206 + #gpio-cells = <2>;
9207 + interrupt-controller;
9208 + #interrupt-cells = <2>;
9211 + /* TODO: WRIOP (CCSR?) */
9212 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
9213 + * E-MDIO1: 0x1_6000
9215 + compatible = "fsl,fman-memac-mdio";
9216 + reg = <0x0 0x8B96000 0x0 0x1000>;
9217 + device_type = "mdio"; /* TODO: is this necessary? */
9218 + little-endian; /* force the driver in LE mode */
9220 + /* Not necessary on the QDS, but needed on the RDB */
9221 + #address-cells = <1>;
9222 + #size-cells = <0>;
9225 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
9226 + * E-MDIO2: 0x1_7000
9228 + compatible = "fsl,fman-memac-mdio";
9229 + reg = <0x0 0x8B97000 0x0 0x1000>;
9230 + device_type = "mdio"; /* TODO: is this necessary? */
9231 + little-endian; /* force the driver in LE mode */
9233 + #address-cells = <1>;
9234 + #size-cells = <0>;
9237 + pcs_mdio1: mdio@0x8c07000 {
9238 + compatible = "fsl,fman-memac-mdio";
9239 + reg = <0x0 0x8c07000 0x0 0x1000>;
9240 + device_type = "mdio";
9243 + #address-cells = <1>;
9244 + #size-cells = <0>;
9247 + pcs_mdio2: mdio@0x8c0b000 {
9248 + compatible = "fsl,fman-memac-mdio";
9249 + reg = <0x0 0x8c0b000 0x0 0x1000>;
9250 + device_type = "mdio";
9253 + #address-cells = <1>;
9254 + #size-cells = <0>;
9257 + pcs_mdio3: mdio@0x8c0f000 {
9258 + compatible = "fsl,fman-memac-mdio";
9259 + reg = <0x0 0x8c0f000 0x0 0x1000>;
9260 + device_type = "mdio";
9263 + #address-cells = <1>;
9264 + #size-cells = <0>;
9267 + pcs_mdio4: mdio@0x8c13000 {
9268 + compatible = "fsl,fman-memac-mdio";
9269 + reg = <0x0 0x8c13000 0x0 0x1000>;
9270 + device_type = "mdio";
9273 + #address-cells = <1>;
9274 + #size-cells = <0>;
9277 + pcs_mdio5: mdio@0x8c17000 {
9278 + status = "disabled";
9279 + compatible = "fsl,fman-memac-mdio";
9280 + reg = <0x0 0x8c17000 0x0 0x1000>;
9281 + device_type = "mdio";
9284 + #address-cells = <1>;
9285 + #size-cells = <0>;
9288 + pcs_mdio6: mdio@0x8c1b000 {
9289 + status = "disabled";
9290 + compatible = "fsl,fman-memac-mdio";
9291 + reg = <0x0 0x8c1b000 0x0 0x1000>;
9292 + device_type = "mdio";
9295 + #address-cells = <1>;
9296 + #size-cells = <0>;
9299 + pcs_mdio7: mdio@0x8c1f000 {
9300 + status = "disabled";
9301 + compatible = "fsl,fman-memac-mdio";
9302 + reg = <0x0 0x8c1f000 0x0 0x1000>;
9303 + device_type = "mdio";
9306 + #address-cells = <1>;
9307 + #size-cells = <0>;
9310 + pcs_mdio8: mdio@0x8c23000 {
9311 + status = "disabled";
9312 + compatible = "fsl,fman-memac-mdio";
9313 + reg = <0x0 0x8c23000 0x0 0x1000>;
9314 + device_type = "mdio";
9317 + #address-cells = <1>;
9318 + #size-cells = <0>;
9321 + i2c0: i2c@2000000 {
9322 + status = "disabled";
9323 + compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
9324 + #address-cells = <1>;
9325 + #size-cells = <0>;
9326 + reg = <0x0 0x2000000 0x0 0x10000>;
9327 + interrupts = <0 34 0x4>; /* Level high type */
9328 + clock-names = "i2c";
9329 + clocks = <&clockgen 4 1>;
9330 + fsl-scl-gpio = <&gpio3 10 0>;
9333 + i2c1: i2c@2010000 {
9334 + status = "disabled";
9335 + compatible = "fsl,vf610-i2c";
9336 + #address-cells = <1>;
9337 + #size-cells = <0>;
9338 + reg = <0x0 0x2010000 0x0 0x10000>;
9339 + interrupts = <0 34 0x4>; /* Level high type */
9340 + clock-names = "i2c";
9341 + clocks = <&clockgen 4 1>;
9344 + i2c2: i2c@2020000 {
9345 + status = "disabled";
9346 + compatible = "fsl,vf610-i2c";
9347 + #address-cells = <1>;
9348 + #size-cells = <0>;
9349 + reg = <0x0 0x2020000 0x0 0x10000>;
9350 + interrupts = <0 35 0x4>; /* Level high type */
9351 + clock-names = "i2c";
9352 + clocks = <&clockgen 4 1>;
9355 + i2c3: i2c@2030000 {
9356 + status = "disabled";
9357 + compatible = "fsl,vf610-i2c";
9358 + #address-cells = <1>;
9359 + #size-cells = <0>;
9360 + reg = <0x0 0x2030000 0x0 0x10000>;
9361 + interrupts = <0 35 0x4>; /* Level high type */
9362 + clock-names = "i2c";
9363 + clocks = <&clockgen 4 1>;
9366 + ifc: ifc@2240000 {
9367 + compatible = "fsl,ifc", "simple-bus";
9368 + reg = <0x0 0x2240000 0x0 0x20000>;
9369 + interrupts = <0 21 0x4>; /* Level high type */
9371 + #address-cells = <2>;
9372 + #size-cells = <1>;
9374 + ranges = <0 0 0x5 0x80000000 0x08000000
9375 + 2 0 0x5 0x30000000 0x00010000
9376 + 3 0 0x5 0x20000000 0x00010000>;
9379 + qspi: quadspi@20c0000 {
9380 + status = "disabled";
9381 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
9382 + #address-cells = <1>;
9383 + #size-cells = <0>;
9384 + reg = <0x0 0x20c0000 0x0 0x10000>,
9385 + <0x0 0x20000000 0x0 0x10000000>;
9386 + reg-names = "QuadSPI", "QuadSPI-memory";
9387 + interrupts = <0 25 0x4>; /* Level high type */
9388 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
9389 + clock-names = "qspi_en", "qspi";
9392 + pcie1: pcie@3400000 {
9393 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9395 + reg-names = "regs", "config";
9396 + interrupts = <0 108 0x4>; /* aer interrupt */
9397 + interrupt-names = "aer";
9398 + #address-cells = <3>;
9399 + #size-cells = <2>;
9400 + device_type = "pci";
9403 + bus-range = <0x0 0xff>;
9404 + msi-parent = <&its>;
9405 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9406 + #interrupt-cells = <1>;
9407 + interrupt-map-mask = <0 0 0 7>;
9408 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
9409 + <0000 0 0 2 &gic 0 0 0 110 4>,
9410 + <0000 0 0 3 &gic 0 0 0 111 4>,
9411 + <0000 0 0 4 &gic 0 0 0 112 4>;
9414 + pcie2: pcie@3500000 {
9415 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9417 + reg-names = "regs", "config";
9418 + interrupts = <0 113 0x4>; /* aer interrupt */
9419 + interrupt-names = "aer";
9420 + #address-cells = <3>;
9421 + #size-cells = <2>;
9422 + device_type = "pci";
9425 + bus-range = <0x0 0xff>;
9426 + msi-parent = <&its>;
9427 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9428 + #interrupt-cells = <1>;
9429 + interrupt-map-mask = <0 0 0 7>;
9430 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9431 + <0000 0 0 2 &gic 0 0 0 115 4>,
9432 + <0000 0 0 3 &gic 0 0 0 116 4>,
9433 + <0000 0 0 4 &gic 0 0 0 117 4>;
9436 + pcie3: pcie@3600000 {
9437 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9439 + reg-names = "regs", "config";
9440 + interrupts = <0 118 0x4>; /* aer interrupt */
9441 + interrupt-names = "aer";
9442 + #address-cells = <3>;
9443 + #size-cells = <2>;
9444 + device_type = "pci";
9447 + bus-range = <0x0 0xff>;
9448 + msi-parent = <&its>;
9449 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9450 + #interrupt-cells = <1>;
9451 + interrupt-map-mask = <0 0 0 7>;
9452 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9453 + <0000 0 0 2 &gic 0 0 0 120 4>,
9454 + <0000 0 0 3 &gic 0 0 0 121 4>,
9455 + <0000 0 0 4 &gic 0 0 0 122 4>;
9458 + pcie4: pcie@3700000 {
9459 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9461 + reg-names = "regs", "config";
9462 + interrupts = <0 123 0x4>; /* aer interrupt */
9463 + interrupt-names = "aer";
9464 + #address-cells = <3>;
9465 + #size-cells = <2>;
9466 + device_type = "pci";
9469 + bus-range = <0x0 0xff>;
9470 + msi-parent = <&its>;
9471 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9472 + #interrupt-cells = <1>;
9473 + interrupt-map-mask = <0 0 0 7>;
9474 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9475 + <0000 0 0 2 &gic 0 0 0 125 4>,
9476 + <0000 0 0 3 &gic 0 0 0 126 4>,
9477 + <0000 0 0 4 &gic 0 0 0 127 4>;
9480 + sata0: sata@3200000 {
9481 + status = "disabled";
9482 + compatible = "fsl,ls2080a-ahci";
9483 + reg = <0x0 0x3200000 0x0 0x10000>;
9484 + interrupts = <0 133 0x4>; /* Level high type */
9485 + clocks = <&clockgen 4 3>;
9489 + sata1: sata@3210000 {
9490 + status = "disabled";
9491 + compatible = "fsl,ls2080a-ahci";
9492 + reg = <0x0 0x3210000 0x0 0x10000>;
9493 + interrupts = <0 136 0x4>; /* Level high type */
9494 + clocks = <&clockgen 4 3>;
9498 + usb0: usb3@3100000 {
9499 + status = "disabled";
9500 + compatible = "snps,dwc3";
9501 + reg = <0x0 0x3100000 0x0 0x10000>;
9502 + interrupts = <0 80 0x4>; /* Level high type */
9504 + snps,quirk-frame-length-adjustment = <0x20>;
9505 + snps,dis_rxdet_inp3_quirk;
9508 + usb1: usb3@3110000 {
9509 + status = "disabled";
9510 + compatible = "snps,dwc3";
9511 + reg = <0x0 0x3110000 0x0 0x10000>;
9512 + interrupts = <0 81 0x4>; /* Level high type */
9514 + snps,quirk-frame-length-adjustment = <0x20>;
9515 + snps,dis_rxdet_inp3_quirk;
9518 + serdes1: serdes@1ea0000 {
9519 + reg = <0x0 0x1ea0000 0 0x00002000>;
9523 + compatible = "arm,ccn-504";
9524 + reg = <0x0 0x04000000 0x0 0x01000000>;
9525 + interrupts = <0 12 4>;
9528 + ftm0: ftm0@2800000 {
9529 + compatible = "fsl,ls208xa-ftm";
9530 + reg = <0x0 0x2800000 0x0 0x10000>,
9531 + <0x0 0x1e34050 0x0 0x4>;
9532 + interrupts = <0 44 4>;
9533 + reg-names = "ftm", "FlexTimer1";
9537 + ddr1: memory-controller@1080000 {
9538 + compatible = "fsl,qoriq-memory-controller";
9539 + reg = <0x0 0x1080000 0x0 0x1000>;
9540 + interrupts = <0 17 0x4>;
9544 + ddr2: memory-controller@1090000 {
9545 + compatible = "fsl,qoriq-memory-controller";
9546 + reg = <0x0 0x1090000 0x0 0x1000>;
9547 + interrupts = <0 18 0x4>;
9553 + compatible = "linaro,optee-tz";
9559 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
9562 + * QorIQ BMan SDK Portals device tree nodes
9564 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9565 + * Copyright 2017 NXP
9567 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9575 + bman-portal@10000 {
9579 + bman-portal@20000 {
9583 + bman-portal@30000 {
9587 + bman-portal@40000 {
9591 + bman-portal@50000 {
9595 + bman-portal@60000 {
9599 + bman-portal@70000 {
9603 + bman-portal@80000 {
9607 + bman-portal@90000 {
9612 + compatible = "fsl,bpid-range";
9613 + fsl,bpid-range = <32 32>;
9617 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
9619 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9621 + * QorIQ BMan Portals device tree
9623 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9628 + #address-cells = <1>;
9629 + #size-cells = <1>;
9630 + compatible = "simple-bus";
9634 + * bootloader fix-ups are expected to provide the
9635 + * "fsl,bman-portal-<hardware revision>" compatible
9637 + compatible = "fsl,bman-portal";
9638 + reg = <0x0 0x4000>, <0x4000000 0x4000>;
9639 + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
9642 + bman-portal@10000 {
9643 + compatible = "fsl,bman-portal";
9644 + reg = <0x10000 0x4000>, <0x4010000 0x4000>;
9645 + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
9648 + bman-portal@20000 {
9649 + compatible = "fsl,bman-portal";
9650 + reg = <0x20000 0x4000>, <0x4020000 0x4000>;
9651 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
9654 + bman-portal@30000 {
9655 + compatible = "fsl,bman-portal";
9656 + reg = <0x30000 0x4000>, <0x4030000 0x4000>;
9657 + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
9660 + bman-portal@40000 {
9661 + compatible = "fsl,bman-portal";
9662 + reg = <0x40000 0x4000>, <0x4040000 0x4000>;
9663 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
9666 + bman-portal@50000 {
9667 + compatible = "fsl,bman-portal";
9668 + reg = <0x50000 0x4000>, <0x4050000 0x4000>;
9669 + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
9672 + bman-portal@60000 {
9673 + compatible = "fsl,bman-portal";
9674 + reg = <0x60000 0x4000>, <0x4060000 0x4000>;
9675 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
9678 + bman-portal@70000 {
9679 + compatible = "fsl,bman-portal";
9680 + reg = <0x70000 0x4000>, <0x4070000 0x4000>;
9681 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
9684 + bman-portal@80000 {
9685 + compatible = "fsl,bman-portal";
9686 + reg = <0x80000 0x4000>, <0x4080000 0x4000>;
9687 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
9690 + bman-portal@90000 {
9691 + compatible = "fsl,bman-portal";
9692 + reg = <0x90000 0x4000>, <0x4090000 0x4000>;
9693 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
9697 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9700 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9702 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9704 + * Redistribution and use in source and binary forms, with or without
9705 + * modification, are permitted provided that the following conditions are met:
9706 + * * Redistributions of source code must retain the above copyright
9707 + * notice, this list of conditions and the following disclaimer.
9708 + * * Redistributions in binary form must reproduce the above copyright
9709 + * notice, this list of conditions and the following disclaimer in the
9710 + * documentation and/or other materials provided with the distribution.
9711 + * * Neither the name of Freescale Semiconductor nor the
9712 + * names of its contributors may be used to endorse or promote products
9713 + * derived from this software without specific prior written permission.
9716 + * ALTERNATIVELY, this software may be distributed under the terms of the
9717 + * GNU General Public License ("GPL") as published by the Free Software
9718 + * Foundation, either version 2 of that License or (at your option) any
9721 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9722 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9723 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9724 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9725 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9726 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9727 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9728 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9729 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9730 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9733 +fsldpaa: fsl,dpaa {
9734 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9736 + compatible = "fsl,dpa-ethernet";
9737 + fsl,fman-mac = <&enet0>;
9741 + compatible = "fsl,dpa-ethernet";
9742 + fsl,fman-mac = <&enet1>;
9746 + compatible = "fsl,dpa-ethernet";
9747 + fsl,fman-mac = <&enet2>;
9751 + compatible = "fsl,dpa-ethernet";
9752 + fsl,fman-mac = <&enet3>;
9756 + compatible = "fsl,dpa-ethernet";
9757 + fsl,fman-mac = <&enet4>;
9761 + compatible = "fsl,dpa-ethernet";
9762 + fsl,fman-mac = <&enet5>;
9766 + compatible = "fsl,dpa-ethernet";
9767 + fsl,fman-mac = <&enet6>;
9773 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9775 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9777 + * QorIQ FMan v3 10g port #0 device tree
9779 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9784 + fman0_rx_0x10: port@90000 {
9785 + cell-index = <0x10>;
9786 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9787 + reg = <0x90000 0x1000>;
9788 + fsl,fman-10g-port;
9791 + fman0_tx_0x30: port@b0000 {
9792 + cell-index = <0x30>;
9793 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9794 + reg = <0xb0000 0x1000>;
9795 + fsl,fman-10g-port;
9796 + fsl,qman-channel-id = <0x800>;
9800 + cell-index = <0x8>;
9801 + compatible = "fsl,fman-memac";
9802 + reg = <0xf0000 0x1000>;
9803 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9804 + pcsphy-handle = <&pcsphy6>;
9808 + #address-cells = <1>;
9809 + #size-cells = <0>;
9810 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9811 + reg = <0xf1000 0x1000>;
9813 + pcsphy6: ethernet-phy@0 {
9819 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9821 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9823 + * QorIQ FMan v3 10g port #1 device tree
9825 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9830 + fman0_rx_0x11: port@91000 {
9831 + cell-index = <0x11>;
9832 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9833 + reg = <0x91000 0x1000>;
9834 + fsl,fman-10g-port;
9837 + fman0_tx_0x31: port@b1000 {
9838 + cell-index = <0x31>;
9839 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9840 + reg = <0xb1000 0x1000>;
9841 + fsl,fman-10g-port;
9842 + fsl,qman-channel-id = <0x801>;
9846 + cell-index = <0x9>;
9847 + compatible = "fsl,fman-memac";
9848 + reg = <0xf2000 0x1000>;
9849 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9850 + pcsphy-handle = <&pcsphy7>;
9854 + #address-cells = <1>;
9855 + #size-cells = <0>;
9856 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9857 + reg = <0xf3000 0x1000>;
9859 + pcsphy7: ethernet-phy@0 {
9865 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9867 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9869 + * QorIQ FMan v3 1g port #0 device tree
9871 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9876 + fman0_rx_0x08: port@88000 {
9877 + cell-index = <0x8>;
9878 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9879 + reg = <0x88000 0x1000>;
9882 + fman0_tx_0x28: port@a8000 {
9883 + cell-index = <0x28>;
9884 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9885 + reg = <0xa8000 0x1000>;
9886 + fsl,qman-channel-id = <0x802>;
9891 + compatible = "fsl,fman-memac";
9892 + reg = <0xe0000 0x1000>;
9893 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9894 + ptp-timer = <&ptp_timer0>;
9895 + pcsphy-handle = <&pcsphy0>;
9899 + #address-cells = <1>;
9900 + #size-cells = <0>;
9901 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9902 + reg = <0xe1000 0x1000>;
9904 + pcsphy0: ethernet-phy@0 {
9910 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9912 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9914 + * QorIQ FMan v3 1g port #1 device tree
9916 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9921 + fman0_rx_0x09: port@89000 {
9922 + cell-index = <0x9>;
9923 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9924 + reg = <0x89000 0x1000>;
9927 + fman0_tx_0x29: port@a9000 {
9928 + cell-index = <0x29>;
9929 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9930 + reg = <0xa9000 0x1000>;
9931 + fsl,qman-channel-id = <0x803>;
9936 + compatible = "fsl,fman-memac";
9937 + reg = <0xe2000 0x1000>;
9938 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9939 + ptp-timer = <&ptp_timer0>;
9940 + pcsphy-handle = <&pcsphy1>;
9944 + #address-cells = <1>;
9945 + #size-cells = <0>;
9946 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9947 + reg = <0xe3000 0x1000>;
9949 + pcsphy1: ethernet-phy@0 {
9955 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9957 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9959 + * QorIQ FMan v3 1g port #2 device tree
9961 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9966 + fman0_rx_0x0a: port@8a000 {
9967 + cell-index = <0xa>;
9968 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9969 + reg = <0x8a000 0x1000>;
9972 + fman0_tx_0x2a: port@aa000 {
9973 + cell-index = <0x2a>;
9974 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9975 + reg = <0xaa000 0x1000>;
9976 + fsl,qman-channel-id = <0x804>;
9981 + compatible = "fsl,fman-memac";
9982 + reg = <0xe4000 0x1000>;
9983 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9984 + ptp-timer = <&ptp_timer0>;
9985 + pcsphy-handle = <&pcsphy2>;
9989 + #address-cells = <1>;
9990 + #size-cells = <0>;
9991 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9992 + reg = <0xe5000 0x1000>;
9994 + pcsphy2: ethernet-phy@0 {
10000 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
10002 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10004 + * QorIQ FMan v3 1g port #3 device tree
10006 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10011 + fman0_rx_0x0b: port@8b000 {
10012 + cell-index = <0xb>;
10013 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
10014 + reg = <0x8b000 0x1000>;
10017 + fman0_tx_0x2b: port@ab000 {
10018 + cell-index = <0x2b>;
10019 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
10020 + reg = <0xab000 0x1000>;
10021 + fsl,qman-channel-id = <0x805>;
10025 + cell-index = <3>;
10026 + compatible = "fsl,fman-memac";
10027 + reg = <0xe6000 0x1000>;
10028 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
10029 + ptp-timer = <&ptp_timer0>;
10030 + pcsphy-handle = <&pcsphy3>;
10034 + #address-cells = <1>;
10035 + #size-cells = <0>;
10036 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10037 + reg = <0xe7000 0x1000>;
10039 + pcsphy3: ethernet-phy@0 {
10045 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
10047 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10049 + * QorIQ FMan v3 1g port #4 device tree
10051 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10056 + fman0_rx_0x0c: port@8c000 {
10057 + cell-index = <0xc>;
10058 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
10059 + reg = <0x8c000 0x1000>;
10062 + fman0_tx_0x2c: port@ac000 {
10063 + cell-index = <0x2c>;
10064 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
10065 + reg = <0xac000 0x1000>;
10066 + fsl,qman-channel-id = <0x806>;
10070 + cell-index = <4>;
10071 + compatible = "fsl,fman-memac";
10072 + reg = <0xe8000 0x1000>;
10073 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
10074 + ptp-timer = <&ptp_timer0>;
10075 + pcsphy-handle = <&pcsphy4>;
10079 + #address-cells = <1>;
10080 + #size-cells = <0>;
10081 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10082 + reg = <0xe9000 0x1000>;
10084 + pcsphy4: ethernet-phy@0 {
10090 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
10092 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10094 + * QorIQ FMan v3 1g port #5 device tree
10096 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10101 + fman0_rx_0x0d: port@8d000 {
10102 + cell-index = <0xd>;
10103 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
10104 + reg = <0x8d000 0x1000>;
10107 + fman0_tx_0x2d: port@ad000 {
10108 + cell-index = <0x2d>;
10109 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
10110 + reg = <0xad000 0x1000>;
10111 + fsl,qman-channel-id = <0x807>;
10115 + cell-index = <5>;
10116 + compatible = "fsl,fman-memac";
10117 + reg = <0xea000 0x1000>;
10118 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
10119 + ptp-timer = <&ptp_timer0>;
10120 + pcsphy-handle = <&pcsphy5>;
10124 + #address-cells = <1>;
10125 + #size-cells = <0>;
10126 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10127 + reg = <0xeb000 0x1000>;
10129 + pcsphy5: ethernet-phy@0 {
10135 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
10138 + * QorIQ FMan v3 OH ports device tree
10140 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10142 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10147 + fman0_oh1: port@82000 {
10148 + cell-index = <0>;
10149 + compatible = "fsl,fman-port-oh";
10150 + reg = <0x82000 0x1000>;
10153 + fman0_oh2: port@83000 {
10154 + cell-index = <1>;
10155 + compatible = "fsl,fman-port-oh";
10156 + reg = <0x83000 0x1000>;
10159 + fman0_oh3: port@84000 {
10160 + cell-index = <2>;
10161 + compatible = "fsl,fman-port-oh";
10162 + reg = <0x84000 0x1000>;
10165 + fman0_oh4: port@85000 {
10166 + cell-index = <3>;
10167 + compatible = "fsl,fman-port-oh";
10168 + reg = <0x85000 0x1000>;
10171 + fman0_oh5: port@86000 {
10172 + cell-index = <4>;
10173 + compatible = "fsl,fman-port-oh";
10174 + reg = <0x86000 0x1000>;
10177 + fman0_oh6: port@87000 {
10178 + cell-index = <5>;
10179 + compatible = "fsl,fman-port-oh";
10180 + reg = <0x87000 0x1000>;
10185 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
10187 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10189 + * QorIQ FMan v3 device tree
10191 + * Copyright 2012-2015 Freescale Semiconductor Inc.
10195 +fman0: fman@1a00000 {
10196 + #address-cells = <1>;
10197 + #size-cells = <1>;
10198 + cell-index = <0>;
10199 + compatible = "fsl,fman";
10200 + ranges = <0x0 0x00 0x1a00000 0x100000>;
10201 + reg = <0x0 0x1a00000 0x0 0x100000>;
10202 + interrupts = <0 44 0x4>, <0 45 0x4>;
10203 + clocks = <&clockgen 3 0>;
10204 + clock-names = "fmanclk";
10205 + fsl,qman-channel-range = <0x800 0x10>;
10208 + compatible = "fsl,fman-cc";
10212 + compatible = "fsl,fman-muram";
10213 + reg = <0x0 0x60000>;
10217 + compatible = "fsl,fman-bmi";
10218 + reg = <0x80000 0x400>;
10222 + compatible = "fsl,fman-qmi";
10223 + reg = <0x80400 0x400>;
10226 + fman0_oh_0x2: port@82000 {
10227 + cell-index = <0x2>;
10228 + compatible = "fsl,fman-v3-port-oh";
10229 + reg = <0x82000 0x1000>;
10230 + fsl,qman-channel-id = <0x809>;
10233 + fman0_oh_0x3: port@83000 {
10234 + cell-index = <0x3>;
10235 + compatible = "fsl,fman-v3-port-oh";
10236 + reg = <0x83000 0x1000>;
10237 + fsl,qman-channel-id = <0x80a>;
10240 + fman0_oh_0x4: port@84000 {
10241 + cell-index = <0x4>;
10242 + compatible = "fsl,fman-v3-port-oh";
10243 + reg = <0x84000 0x1000>;
10244 + fsl,qman-channel-id = <0x80b>;
10247 + fman0_oh_0x5: port@85000 {
10248 + cell-index = <0x5>;
10249 + compatible = "fsl,fman-v3-port-oh";
10250 + reg = <0x85000 0x1000>;
10251 + fsl,qman-channel-id = <0x80c>;
10254 + fman0_oh_0x6: port@86000 {
10255 + cell-index = <0x6>;
10256 + compatible = "fsl,fman-v3-port-oh";
10257 + reg = <0x86000 0x1000>;
10258 + fsl,qman-channel-id = <0x80d>;
10261 + fman0_oh_0x7: port@87000 {
10262 + cell-index = <0x7>;
10263 + compatible = "fsl,fman-v3-port-oh";
10264 + reg = <0x87000 0x1000>;
10265 + fsl,qman-channel-id = <0x80e>;
10269 + compatible = "fsl,fman-policer";
10270 + reg = <0xc0000 0x1000>;
10274 + compatible = "fsl,fman-keygen";
10275 + reg = <0xc1000 0x1000>;
10279 + compatible = "fsl,fman-dma";
10280 + reg = <0xc2000 0x1000>;
10284 + compatible = "fsl,fman-fpm";
10285 + reg = <0xc3000 0x1000>;
10289 + compatible = "fsl,fman-parser";
10290 + reg = <0xc7000 0x1000>;
10294 + compatible = "fsl,fman-vsps";
10295 + reg = <0xdc000 0x1000>;
10298 + mdio0: mdio@fc000 {
10299 + #address-cells = <1>;
10300 + #size-cells = <0>;
10301 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10302 + reg = <0xfc000 0x1000>;
10305 + xmdio0: mdio@fd000 {
10306 + #address-cells = <1>;
10307 + #size-cells = <0>;
10308 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10309 + reg = <0xfd000 0x1000>;
10312 + ptp_timer0: ptp-timer@fe000 {
10313 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
10314 + reg = <0xfe000 0x1000>;
10318 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
10321 + * QorIQ QMan SDK Portals device tree nodes
10323 + * Copyright 2011-2016 Freescale Semiconductor Inc.
10324 + * Copyright 2017 NXP
10326 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10331 + compatible = "fsl,fqid-range";
10332 + fsl,fqid-range = <256 256>;
10336 + compatible = "fsl,fqid-range";
10337 + fsl,fqid-range = <32768 32768>;
10341 + compatible = "fsl,pool-channel-range";
10342 + fsl,pool-channel-range = <0x401 0xf>;
10346 + compatible = "fsl,cgrid-range";
10347 + fsl,cgrid-range = <0 256>;
10351 + compatible = "fsl,qman-ceetm";
10352 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
10353 + fsl,ceetm-sp-range = <0 16>;
10354 + fsl,ceetm-lni-range = <0 8>;
10355 + fsl,ceetm-channel-range = <0 32>;
10359 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
10361 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10363 + * QorIQ QMan Portals device tree
10365 + * Copyright 2011-2016 Freescale Semiconductor Inc.
10370 + #address-cells = <1>;
10371 + #size-cells = <1>;
10372 + compatible = "simple-bus";
10374 + qportal0: qman-portal@0 {
10376 + * bootloader fix-ups are expected to provide the
10377 + * "fsl,bman-portal-<hardware revision>" compatible
10379 + compatible = "fsl,qman-portal";
10380 + reg = <0x0 0x4000>, <0x4000000 0x4000>;
10381 + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
10382 + cell-index = <0>;
10385 + qportal1: qman-portal@10000 {
10386 + compatible = "fsl,qman-portal";
10387 + reg = <0x10000 0x4000>, <0x4010000 0x4000>;
10388 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
10389 + cell-index = <1>;
10392 + qportal2: qman-portal@20000 {
10393 + compatible = "fsl,qman-portal";
10394 + reg = <0x20000 0x4000>, <0x4020000 0x4000>;
10395 + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
10396 + cell-index = <2>;
10399 + qportal3: qman-portal@30000 {
10400 + compatible = "fsl,qman-portal";
10401 + reg = <0x30000 0x4000>, <0x4030000 0x4000>;
10402 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
10403 + cell-index = <3>;
10406 + qportal4: qman-portal@40000 {
10407 + compatible = "fsl,qman-portal";
10408 + reg = <0x40000 0x4000>, <0x4040000 0x4000>;
10409 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
10410 + cell-index = <4>;
10413 + qportal5: qman-portal@50000 {
10414 + compatible = "fsl,qman-portal";
10415 + reg = <0x50000 0x4000>, <0x4050000 0x4000>;
10416 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
10417 + cell-index = <5>;
10420 + qportal6: qman-portal@60000 {
10421 + compatible = "fsl,qman-portal";
10422 + reg = <0x60000 0x4000>, <0x4060000 0x4000>;
10423 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
10424 + cell-index = <6>;
10427 + qportal7: qman-portal@70000 {
10428 + compatible = "fsl,qman-portal";
10429 + reg = <0x70000 0x4000>, <0x4070000 0x4000>;
10430 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
10431 + cell-index = <7>;
10434 + qportal8: qman-portal@80000 {
10435 + compatible = "fsl,qman-portal";
10436 + reg = <0x80000 0x4000>, <0x4080000 0x4000>;
10437 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
10438 + cell-index = <8>;
10441 + qportal9: qman-portal@90000 {
10442 + compatible = "fsl,qman-portal";
10443 + reg = <0x90000 0x4000>, <0x4090000 0x4000>;
10444 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
10445 + cell-index = <9>;
10448 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10449 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10450 @@ -38,51 +38,61 @@
10451 compatible = "simple-bus";
10454 + cell-index = <0>;
10455 compatible = "fsl,bman-portal";
10456 reg = <0x0 0x4000>, <0x100000 0x1000>;
10457 interrupts = <105 2 0 0>;
10460 + cell-index = <1>;
10461 compatible = "fsl,bman-portal";
10462 reg = <0x4000 0x4000>, <0x101000 0x1000>;
10463 interrupts = <107 2 0 0>;
10466 + cell-index = <2>;
10467 compatible = "fsl,bman-portal";
10468 reg = <0x8000 0x4000>, <0x102000 0x1000>;
10469 interrupts = <109 2 0 0>;
10472 + cell-index = <3>;
10473 compatible = "fsl,bman-portal";
10474 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10475 interrupts = <111 2 0 0>;
10477 bman-portal@10000 {
10478 + cell-index = <4>;
10479 compatible = "fsl,bman-portal";
10480 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10481 interrupts = <113 2 0 0>;
10483 bman-portal@14000 {
10484 + cell-index = <5>;
10485 compatible = "fsl,bman-portal";
10486 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10487 interrupts = <115 2 0 0>;
10489 bman-portal@18000 {
10490 + cell-index = <6>;
10491 compatible = "fsl,bman-portal";
10492 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10493 interrupts = <117 2 0 0>;
10495 bman-portal@1c000 {
10496 + cell-index = <7>;
10497 compatible = "fsl,bman-portal";
10498 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10499 interrupts = <119 2 0 0>;
10501 bman-portal@20000 {
10502 + cell-index = <8>;
10503 compatible = "fsl,bman-portal";
10504 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10505 interrupts = <121 2 0 0>;
10507 bman-portal@24000 {
10508 + cell-index = <9>;
10509 compatible = "fsl,bman-portal";
10510 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10511 interrupts = <123 2 0 0>;
10512 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10513 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10514 @@ -35,14 +35,14 @@
10516 fman0_rx_0x10: port@90000 {
10517 cell-index = <0x10>;
10518 - compatible = "fsl,fman-v3-port-rx";
10519 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10520 reg = <0x90000 0x1000>;
10524 fman0_tx_0x30: port@b0000 {
10525 cell-index = <0x30>;
10526 - compatible = "fsl,fman-v3-port-tx";
10527 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10528 reg = <0xb0000 0x1000>;
10531 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10532 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10533 @@ -35,14 +35,14 @@
10535 fman0_rx_0x11: port@91000 {
10536 cell-index = <0x11>;
10537 - compatible = "fsl,fman-v3-port-rx";
10538 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10539 reg = <0x91000 0x1000>;
10543 fman0_tx_0x31: port@b1000 {
10544 cell-index = <0x31>;
10545 - compatible = "fsl,fman-v3-port-tx";
10546 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10547 reg = <0xb1000 0x1000>;