1 From f8daa8e984213554008e73cd155530dceec5a109 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 27 Sep 2017 10:34:07 +0800
4 Subject: [PATCH] usb: support layerscape
6 This is a integrated patch for layerscape usb support.
8 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
9 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
10 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
15 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
18 drivers/usb/common/common.c | 50 ++++++
19 drivers/usb/core/hub.c | 8 +
20 drivers/usb/dwc3/core.c | 235 ++++++++++++++++++++++++++-
21 drivers/usb/dwc3/core.h | 46 +++++-
22 drivers/usb/dwc3/host.c | 15 +-
23 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++---
24 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
25 drivers/usb/host/Kconfig | 2 +-
26 drivers/usb/host/ehci-fsl.c | 289 +++++++++++++++++++++++++++++++---
27 drivers/usb/host/ehci-fsl.h | 3 +
28 drivers/usb/host/ehci-hub.c | 2 +
29 drivers/usb/host/ehci.h | 5 +
30 drivers/usb/host/fsl-mph-dr-of.c | 12 ++
31 drivers/usb/phy/phy-fsl-usb.c | 59 +++++--
32 drivers/usb/phy/phy-fsl-usb.h | 8 +
33 include/linux/usb.h | 1 +
34 include/linux/usb/of.h | 2 +
35 17 files changed, 726 insertions(+), 73 deletions(-)
37 --- a/drivers/usb/common/common.c
38 +++ b/drivers/usb/common/common.c
39 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
40 [USB_DR_MODE_OTG] = "otg",
44 + * of_usb_get_dr_mode - Get dual role mode for given device_node
45 + * @np: Pointer to the given device_node
47 + * The function gets phy interface string from property 'dr_mode',
48 + * and returns the correspondig enum usb_dr_mode
50 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
52 + const char *dr_mode;
55 + err = of_property_read_string(np, "dr_mode", &dr_mode);
57 + return USB_DR_MODE_UNKNOWN;
59 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
60 + if (!strcmp(dr_mode, usb_dr_modes[i]))
63 + return USB_DR_MODE_UNKNOWN;
65 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
68 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
70 + * @np: Pointer to the given device_node
72 + * The function gets the maximum speed string from property "maximum-speed",
73 + * and returns the corresponding enum usb_device_speed.
75 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
77 + const char *maximum_speed;
81 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
83 + return USB_SPEED_UNKNOWN;
85 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
86 + if (strcmp(maximum_speed, speed_names[i]) == 0)
89 + return USB_SPEED_UNKNOWN;
91 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
93 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
96 --- a/drivers/usb/core/hub.c
97 +++ b/drivers/usb/core/hub.c
98 @@ -4412,6 +4412,14 @@ hub_port_init(struct usb_hub *hub, struc
100 speed = usb_speed_string(udev->speed);
102 +#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
103 +if (udev->speed != USB_SPEED_SUPER)
104 + dev_info(&udev->dev,
105 + "%s %s USB device number %d using %s\n",
106 + (udev->config) ? "reset" : "new", speed,
107 + devnum, udev->bus->controller->driver->name);
110 if (udev->speed < USB_SPEED_SUPER)
112 "%s %s USB device number %d using %s\n",
113 --- a/drivers/usb/dwc3/core.c
114 +++ b/drivers/usb/dwc3/core.c
115 @@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3
116 enum usb_dr_mode mode;
117 struct device *dev = dwc->dev;
118 unsigned int hw_mode;
119 + struct device_node *node = dev->of_node;
121 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
122 dwc->dr_mode = USB_DR_MODE_OTG;
123 @@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3
124 mode = USB_DR_MODE_HOST;
127 + /* Adjust Frame Length */
128 + if (dwc->configure_gfladj)
129 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
130 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
132 + /* Change burst beat and outstanding pipelined transfers requests */
133 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
134 + (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
135 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
136 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
138 + /* Enable Snooping */
139 + if (node && of_dma_is_coherent(node)) {
140 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
141 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
142 + dev_dbg(dev, "enabled snooping for usb\n");
145 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
146 mode = USB_DR_MODE_HOST;
147 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
148 @@ -213,8 +232,9 @@ static void dwc3_frame_length_adjustment
150 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
151 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
152 - if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
153 - "request value same as default, ignoring\n")) {
154 + if (dft == dwc->fladj) {
155 + dev_warn(dwc->dev, "request value same as default, ignoring\n");
157 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
158 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
159 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
160 @@ -579,6 +599,99 @@ static int dwc3_phy_setup(struct dwc3 *d
164 +/* set global soc bus configuration registers */
165 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
167 + struct device *dev = dwc->dev;
174 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
177 + * Handle property "snps,incr-burst-type-adjustment".
178 + * Get the number of value from this property:
179 + * result <= 0, means this property is not supported.
180 + * result = 1, means INCRx burst mode supported.
181 + * result > 1, means undefined length burst mode supported.
183 + ntype = device_property_read_u32_array(dev,
184 + "snps,incr-burst-type-adjustment", NULL, 0);
186 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
188 + dev_err(dev, "Error to get memory\n");
191 + /* Get INCR burst type, and parse it */
192 + ret = device_property_read_u32_array(dev,
193 + "snps,incr-burst-type-adjustment", vals, ntype);
195 + dev_err(dev, "Error to get property\n");
198 + *(dwc->incrx_type + 1) = vals[0];
200 + *dwc->incrx_type = 1;
201 + for (i = 1; i < ntype; i++) {
202 + if (vals[i] > *(dwc->incrx_type + 1))
203 + *(dwc->incrx_type + 1) = vals[i];
206 + *dwc->incrx_type = 0;
208 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
209 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
210 + if (*dwc->incrx_type)
211 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
212 + switch (*(dwc->incrx_type + 1)) {
214 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
217 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
220 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
223 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
226 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
229 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
232 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
237 + dev_err(dev, "Invalid property\n");
242 + /* Handle usb snooping */
243 + if (dwc->dma_snooping_quirk) {
244 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
245 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
246 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
247 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
248 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
251 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
257 static void dwc3_core_exit(struct dwc3 *dwc)
259 dwc3_event_buffers_cleanup(dwc);
260 @@ -721,6 +834,8 @@ static int dwc3_core_init(struct dwc3 *d
264 + dwc3_set_soc_bus_cfg(dwc);
266 /* Adjust Frame Length */
267 dwc3_frame_length_adjustment(dwc);
269 @@ -919,11 +1034,109 @@ static void dwc3_core_exit_mode(struct d
273 +static void dwc3_get_properties(struct dwc3 *dwc)
275 + struct device *dev = dwc->dev;
276 + struct device_node *node = dev->of_node;
277 + u8 lpm_nyet_threshold;
281 + /* default to highest possible threshold */
282 + lpm_nyet_threshold = 0xff;
284 + /* default to -3.5dB de-emphasis */
285 + tx_de_emphasis = 1;
288 + * default to assert utmi_sleep_n and use maximum allowed HIRD
289 + * threshold value of 0b1100
291 + hird_threshold = 12;
293 + dwc->maximum_speed = usb_get_maximum_speed(dev);
294 + dwc->dr_mode = usb_get_dr_mode(dev);
295 + dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
297 + dwc->sysdev_is_parent = device_property_read_bool(dev,
298 + "linux,sysdev_is_parent");
299 + if (dwc->sysdev_is_parent)
300 + dwc->sysdev = dwc->dev->parent;
302 + dwc->sysdev = dwc->dev;
304 + dwc->has_lpm_erratum = device_property_read_bool(dev,
305 + "snps,has-lpm-erratum");
306 + device_property_read_u8(dev, "snps,lpm-nyet-threshold",
307 + &lpm_nyet_threshold);
308 + dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
309 + "snps,is-utmi-l1-suspend");
310 + device_property_read_u8(dev, "snps,hird-threshold",
312 + dwc->usb3_lpm_capable = device_property_read_bool(dev,
313 + "snps,usb3_lpm_capable");
315 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
317 + dwc->configure_gfladj =
318 + of_property_read_bool(node, "configure-gfladj");
319 + dwc->dr_mode = usb_get_dr_mode(dev);
321 + dwc->disable_scramble_quirk = device_property_read_bool(dev,
322 + "snps,disable_scramble_quirk");
323 + dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
324 + "snps,u2exit_lfps_quirk");
325 + dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
326 + "snps,u2ss_inp3_quirk");
327 + dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
328 + "snps,req_p1p2p3_quirk");
329 + dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
330 + "snps,del_p1p2p3_quirk");
331 + dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
332 + "snps,del_phy_power_chg_quirk");
333 + dwc->lfps_filter_quirk = device_property_read_bool(dev,
334 + "snps,lfps_filter_quirk");
335 + dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
336 + "snps,rx_detect_poll_quirk");
337 + dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
338 + "snps,dis_u3_susphy_quirk");
339 + dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
340 + "snps,dis_u2_susphy_quirk");
341 + dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
342 + "snps,dis_enblslpm_quirk");
343 + dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
344 + "snps,dis_rxdet_inp3_quirk");
345 + dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
346 + "snps,dis-u2-freeclk-exists-quirk");
347 + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
348 + "snps,dis-del-phy-power-chg-quirk");
349 + dwc->dma_snooping_quirk = device_property_read_bool(dev,
350 + "snps,dma-snooping");
352 + dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
353 + "snps,tx_de_emphasis_quirk");
354 + device_property_read_u8(dev, "snps,tx_de_emphasis",
356 + device_property_read_string(dev, "snps,hsphy_interface",
357 + &dwc->hsphy_interface);
358 + device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
361 + dwc->lpm_nyet_threshold = lpm_nyet_threshold;
362 + dwc->tx_de_emphasis = tx_de_emphasis;
364 + dwc->hird_threshold = hird_threshold
365 + | (dwc->is_utmi_l1_suspend << 4);
367 + dwc->imod_interval = 0;
370 #define DWC3_ALIGN_MASK (16 - 1)
372 static int dwc3_probe(struct platform_device *pdev)
374 struct device *dev = &pdev->dev;
375 + struct device_node *node = dev->of_node;
376 struct resource *res;
378 u8 lpm_nyet_threshold;
379 @@ -955,6 +1168,11 @@ static int dwc3_probe(struct platform_de
380 dwc->xhci_resources[0].flags = res->flags;
381 dwc->xhci_resources[0].name = res->name;
384 + dwc->configure_gfladj =
385 + of_property_read_bool(node, "configure-gfladj");
388 res->start += DWC3_GLOBALS_REGS_START;
391 @@ -997,6 +1215,12 @@ static int dwc3_probe(struct platform_de
392 dwc->usb3_lpm_capable = device_property_read_bool(dev,
393 "snps,usb3_lpm_capable");
395 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
397 + dwc->configure_gfladj =
398 + of_property_read_bool(node, "configure-gfladj");
399 + dwc->dr_mode = of_usb_get_dr_mode(node);
401 dwc->disable_scramble_quirk = device_property_read_bool(dev,
402 "snps,disable_scramble_quirk");
403 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
404 @@ -1041,6 +1265,8 @@ static int dwc3_probe(struct platform_de
405 dwc->hird_threshold = hird_threshold
406 | (dwc->is_utmi_l1_suspend << 4);
408 + dwc3_get_properties(dwc);
410 platform_set_drvdata(pdev, dwc);
411 dwc3_cache_hwparams(dwc);
413 @@ -1064,6 +1290,11 @@ static int dwc3_probe(struct platform_de
417 + /* Adjust Frame Length */
418 + if (dwc->configure_gfladj)
419 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
420 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
422 pm_runtime_forbid(dev);
424 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
425 --- a/drivers/usb/dwc3/core.h
426 +++ b/drivers/usb/dwc3/core.h
428 #include <linux/dma-mapping.h>
429 #include <linux/mm.h>
430 #include <linux/debugfs.h>
431 +#include <linux/of_address.h>
433 #include <linux/usb/ch9.h>
434 #include <linux/usb/gadget.h>
439 +/* Global SoC Bus Configuration Register 0 */
440 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
441 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
442 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
443 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
444 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
445 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
446 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
447 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
448 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
449 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
450 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
451 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
452 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
453 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
454 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
455 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
456 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
457 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
458 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
459 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
461 +/* Global SoC Bus Configuration Register 1 */
462 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
463 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
465 /* Global Debug Queue/FIFO Space Available Register */
466 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
467 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
469 #define DWC3_GCTL_CLK_PIPE (1)
470 #define DWC3_GCTL_CLK_PIPEHALF (2)
471 #define DWC3_GCTL_CLK_MASK (3)
473 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
474 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
475 #define DWC3_GCTL_PRTCAP_HOST 1
477 /* Global Frame Length Adjustment Register */
478 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
479 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
480 +#define GFLADJ_30MHZ_REG_SEL (1 << 7)
481 +#define GFLADJ_30MHZ(n) ((n) & 0x3f)
482 +#define GFLADJ_30MHZ_DEFAULT 0x20
485 /* Global User Control Register 2 */
486 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14)
487 @@ -753,6 +783,7 @@ struct dwc3_scratchpad_array {
488 * @regs: base address for our registers
489 * @regs_size: address space size
490 * @fladj: frame length adjustment
491 + * @incrx_type: INCR burst type adjustment
492 * @irq_gadget: peripheral controller's IRQ number
493 * @nr_scratch: number of scratch buffers
494 * @u1u2: only used on revisions <1.83a for workaround
495 @@ -847,6 +878,7 @@ struct dwc3 {
499 + struct device *sysdev;
501 struct platform_device *xhci;
502 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
503 @@ -872,6 +904,12 @@ struct dwc3 {
504 enum usb_phy_interface hsphy_mode;
508 + * For INCR burst type.
509 + * First field: for undefined length INCR burst type enable.
510 + * Second field: for INCRx burst type enable
516 @@ -948,9 +986,12 @@ struct dwc3 {
517 unsigned ep0_bounced:1;
518 unsigned ep0_expect_in:1;
519 unsigned has_hibernation:1;
520 + unsigned sysdev_is_parent:1;
521 unsigned has_lpm_erratum:1;
522 unsigned is_utmi_l1_suspend:1;
524 + unsigned needs_fifo_resize:1;
525 + unsigned configure_gfladj:1;
526 unsigned pending_events:1;
527 unsigned pullups_connected:1;
528 unsigned setup_packet_pending:1;
529 @@ -971,9 +1012,12 @@ struct dwc3 {
530 unsigned dis_rxdet_inp3_quirk:1;
531 unsigned dis_u2_freeclk_exists_quirk:1;
532 unsigned dis_del_phy_power_chg_quirk:1;
533 + unsigned dma_snooping_quirk:1;
535 unsigned tx_de_emphasis_quirk:1;
536 unsigned tx_de_emphasis:2;
541 /* -------------------------------------------------------------------------- */
542 --- a/drivers/usb/dwc3/host.c
543 +++ b/drivers/usb/dwc3/host.c
546 #include <linux/platform_device.h>
548 +#include <linux/of_device.h>
552 int dwc3_host_init(struct dwc3 *dwc)
553 @@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
557 - dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
558 + if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
559 + of_dma_configure(&xhci->dev, dwc->dev->of_node);
561 + dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
563 - xhci->dev.parent = dwc->dev;
564 + xhci->dev.parent = dwc->dev;
565 xhci->dev.dma_mask = dwc->dev->dma_mask;
566 xhci->dev.dma_parms = dwc->dev->dma_parms;
568 + /* set DMA operations */
569 + if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
570 + xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
571 + dev_dbg(dwc->dev, "set dma_ops for usb\n");
576 ret = platform_device_add_resources(xhci, dwc->xhci_resources,
577 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
578 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
579 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
581 spin_unlock(&ep->udc->lock);
583 - usb_gadget_giveback_request(&ep->ep, &req->req);
584 + /* this complete() should a func implemented by gadget layer,
585 + * eg fsg->bulk_in_complete()
587 + if (req->req.complete)
588 + usb_gadget_giveback_request(&ep->ep, &req->req);
590 spin_lock(&ep->udc->lock);
591 ep->stopped = stopped;
592 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
593 if (udc->pdata->have_sysif_regs) {
594 if (udc->pdata->controller_ver) {
595 /* controller version 1.6 or above */
596 - ctrl = __raw_readl(&usb_sys_regs->control);
597 + ctrl = ioread32be(&usb_sys_regs->control);
598 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
599 ctrl |= USB_CTRL_USB_EN;
600 - __raw_writel(ctrl, &usb_sys_regs->control);
601 + iowrite32be(ctrl, &usb_sys_regs->control);
604 portctrl |= PORTSCX_PTS_ULPI;
605 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
606 portctrl |= PORTSCX_PTW_16BIT;
608 case FSL_USB2_PHY_UTMI:
609 + case FSL_USB2_PHY_UTMI_DUAL:
610 if (udc->pdata->have_sysif_regs) {
611 if (udc->pdata->controller_ver) {
612 /* controller version 1.6 or above */
613 - ctrl = __raw_readl(&usb_sys_regs->control);
614 + ctrl = ioread32be(&usb_sys_regs->control);
615 ctrl |= (USB_CTRL_UTMI_PHY_EN |
617 - __raw_writel(ctrl, &usb_sys_regs->control);
618 + iowrite32be(ctrl, &usb_sys_regs->control);
619 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
620 PHY CLK to become stable - 10ms*/
622 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
623 /* Config control enable i/o output, cpu endian register */
624 #ifndef CONFIG_ARCH_MXC
625 if (udc->pdata->have_sysif_regs) {
626 - ctrl = __raw_readl(&usb_sys_regs->control);
627 + ctrl = ioread32be(&usb_sys_regs->control);
628 ctrl |= USB_CTRL_IOENB;
629 - __raw_writel(ctrl, &usb_sys_regs->control);
630 + iowrite32be(ctrl, &usb_sys_regs->control);
634 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
635 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
636 /* Turn on cache snooping hardware, since some PowerPC platforms
637 * wholly rely on hardware to deal with cache coherent. */
639 if (udc->pdata->have_sysif_regs) {
640 /* Setup Snooping for all the 4GB space */
641 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
642 - __raw_writel(tmp, &usb_sys_regs->snoop1);
643 + iowrite32be(tmp, &usb_sys_regs->snoop1);
644 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
645 - __raw_writel(tmp, &usb_sys_regs->snoop2);
646 + iowrite32be(tmp, &usb_sys_regs->snoop2);
650 @@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb
651 struct ep_queue_head *qh;
653 ep = container_of(_ep, struct fsl_ep, ep);
654 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
655 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
658 udc = (struct fsl_udc *)ep->udc;
659 @@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc
660 struct fsl_req *curr_req)
662 struct ep_td_struct *curr_td;
663 - int td_complete, actual, remaining_length, j, tmp;
664 + int actual, remaining_length, j, tmp;
667 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
668 int direction = pipe % 2;
670 curr_td = curr_req->head;
672 actual = curr_req->req.length;
674 for (j = 0; j < curr_req->dtd_count; j++) {
675 @@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc
684 VDBG("dTD transmitted successful");
687 @@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_
688 curr_ep = get_ep_by_pipe(udc, i);
690 /* If the ep is configured */
691 - if (curr_ep->name == NULL) {
692 + if (strncmp(curr_ep->name, "ep", 2)) {
693 WARNING("Invalid EP?");
696 @@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform
697 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
700 +#ifdef CONFIG_ARCH_MXC
701 /* Initialize USB clocks */
702 ret = fsl_udc_clk_init(pdev);
704 goto err_iounmap_noclk;
707 /* Read Device Controller Capability Parameters register */
708 dccparams = fsl_readl(&dr_regs->dccparams);
709 @@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform
710 dr_controller_setup(udc_controller);
713 +#ifdef CONFIG_ARCH_MXC
714 ret = fsl_udc_clk_finalize(pdev);
719 /* Setup gadget structure */
720 udc_controller->gadget.ops = &fsl_gadget_ops;
721 @@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform
722 /* Setup gadget.dev and register with kernel */
723 dev_set_name(&udc_controller->gadget.dev, "gadget");
724 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
725 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
727 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
728 udc_controller->gadget.is_otg = 1;
729 @@ -2529,7 +2536,9 @@ err_free_irq:
733 +#ifdef CONFIG_ARCH_MXC
734 fsl_udc_clk_release();
738 err_release_mem_region:
739 @@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platfor
740 udc_controller->done = &done;
741 usb_del_gadget_udc(&udc_controller->gadget);
743 +#ifdef CONFIG_ARCH_MXC
744 fsl_udc_clk_release();
747 /* DR has been stopped in usb_gadget_unregister_driver() */
750 @@ -2570,7 +2580,7 @@ static int fsl_udc_remove(struct platfor
751 dma_pool_destroy(udc_controller->td_pool);
752 free_irq(udc_controller->irq, udc_controller);
754 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
755 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
756 release_mem_region(res->start, resource_size(res));
758 /* free udc --wait for the release() finished */
759 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
760 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
762 #define USB_MAX_CTRL_PAYLOAD 64
763 #define USB_DR_SYS_OFFSET 0x400
765 +#ifdef CONFIG_SOC_LS1021A
766 +#undef CONFIG_ARCH_MXC
769 /* USB DR device mode registers (Little Endian) */
770 struct usb_dr_device {
771 /* Capability register */
772 @@ -597,18 +601,6 @@ struct platform_device;
773 int fsl_udc_clk_init(struct platform_device *pdev);
774 int fsl_udc_clk_finalize(struct platform_device *pdev);
775 void fsl_udc_clk_release(void);
777 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
781 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
785 -static inline void fsl_udc_clk_release(void)
791 --- a/drivers/usb/host/Kconfig
792 +++ b/drivers/usb/host/Kconfig
793 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
796 tristate "Support for Freescale PPC on-chip EHCI USB controller"
798 + depends on USB_EHCI_HCD
799 select USB_EHCI_ROOT_HUB_TT
801 Variation of ARC USB block used in some Freescale chips.
802 --- a/drivers/usb/host/ehci-fsl.c
803 +++ b/drivers/usb/host/ehci-fsl.c
805 #include <linux/fsl_devices.h>
806 #include <linux/of_platform.h>
809 +#include <asm/fsl_pm.h>
810 +#include <linux/suspend.h>
814 #include "ehci-fsl.h"
816 +#define FSL_USB_PHY_ADDR 0xffe214000
818 +struct ccsr_usb_port_ctrl {
835 +struct ccsr_usb_phy {
837 + struct ccsr_usb_port_ctrl port1;
845 + struct ccsr_usb_port_ctrl port2;
849 #define DRIVER_DESC "Freescale EHCI Host controller driver"
850 #define DRV_NAME "ehci-fsl"
852 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
854 + /* store current hcd state for otg;
855 + * have_hcd is true when host drv al already part of otg framework,
857 + * hcd_add is true when otg framework wants to add host
858 + * drv as part of otg;flase when it wants to remove it
860 +unsigned have_hcd:1;
864 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
866 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
868 +return container_of(ehci, struct ehci_fsl, ehci);
871 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
872 +static void do_change_hcd(struct work_struct *work)
874 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
876 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
877 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
878 +void __iomem *non_ehci = hcd->regs;
881 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
882 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
883 + /* host, gadget and otg share same int line */
884 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
886 + ehci_fsl->have_hcd = 1;
887 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
888 + usb_remove_hcd(hcd);
889 + ehci_fsl->have_hcd = 0;
895 + struct ehci_hcd ehci;
898 +struct ehci_regs saved_regs;
899 +struct ccsr_usb_phy saved_phy_regs;
900 +/* Saved USB PHY settings, need to restore after deep sleep. */
904 + * store current hcd state for otg;
905 + * have_hcd is true when host drv al already part of otg framework,
907 + * hcd_add is true when otg framework wants to add host
908 + * drv as part of otg;flase when it wants to remove it
910 +unsigned have_hcd:1;
914 +static strut ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
916 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
918 +return container_of(ehci, struct ehci_fsl, ehci);
921 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
922 +static void do_change_hcd(struct work_struct *work)
924 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
926 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
927 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
928 +void __iomem *non_ehci = hcd->regs;
931 +if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
932 +writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
933 +/* host, gadget and otg share same int line */
934 +retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
936 +ehci_fsl->have_hcd = 1;
937 +} else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
938 + usb_remove_hcd(hcd);
939 +ehci_fsl->have_hcd = 0;
944 /* configure so an HC device and id are always provided */
945 /* always called with process context; sleeping is OK */
946 @@ -131,6 +259,12 @@ static int fsl_ehci_drv_probe(struct pla
947 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
948 CONTROL_REGISTER_W1C_MASK, 0x4);
950 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
951 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
952 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
953 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
957 * Enable UTMI phy and program PTS field in UTMI mode before asserting
958 * controller reset for USB Controller version 2.5
959 @@ -143,16 +277,20 @@ static int fsl_ehci_drv_probe(struct pla
961 /* Don't need to set host mode here. It will be done by tdi_reset() */
963 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
964 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
967 device_wakeup_enable(hcd->self.controller);
969 -#ifdef CONFIG_USB_OTG
970 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
971 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
972 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
973 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
975 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
977 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
979 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
980 hcd, ehci, hcd->usb_phy);
982 @@ -168,6 +306,11 @@ static int fsl_ehci_drv_probe(struct pla
987 + ehci_fsl->have_hcd = 1;
989 + dev_err(&pdev->dev, "wrong operating mode\n");
994 @@ -181,6 +324,18 @@ static int fsl_ehci_drv_probe(struct pla
998 +static bool usb_phy_clk_valid(struct usb_hcd *hcd,
999 + enum fsl_usb2_phy_modes phy_mode)
1001 + void __iomem *non_ehci = hcd->regs;
1004 + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
1010 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1011 enum fsl_usb2_phy_modes phy_mode,
1012 unsigned int port_offset)
1013 @@ -219,6 +374,21 @@ static int ehci_fsl_setup_phy(struct usb
1015 case FSL_USB2_PHY_UTMI:
1016 case FSL_USB2_PHY_UTMI_DUAL:
1017 + if (pdata->has_fsl_erratum_a006918) {
1018 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
1022 + /* PHY_CLK_VALID bit is de-featured from all controller
1023 + * versions below 2.4 and is to be checked only for
1024 + * internal UTMI phy
1026 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1027 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1028 + pr_err("fsl-ehci: USB PHY clock invalid\n");
1032 if (pdata->have_sysif_regs && pdata->controller_ver) {
1033 /* controller version 1.6 or above */
1034 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1035 @@ -292,14 +462,9 @@ static int ehci_fsl_usb_setup(struct ehc
1038 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1039 - unsigned int chip, rev, svr;
1041 - svr = mfspr(SPRN_SVR);
1043 - rev = (svr >> 4) & 0xf;
1045 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1046 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1047 + if (pdata->has_fsl_erratum_14 == 1)
1048 ehci->has_fsl_port_bug = 1;
1050 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1051 @@ -379,16 +544,57 @@ static int ehci_fsl_setup(struct usb_hcd
1056 - struct ehci_hcd ehci;
1059 - /* Saved USB PHY settings, need to restore after deep sleep. */
1063 +void __iomem *phy_reg;
1067 +/* save usb registers */
1068 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1070 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1071 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1072 + void __iomem *non_ehci = hcd->regs;
1073 + struct device *dev = hcd->self.controller;
1074 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1076 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1077 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1078 + sizeof(struct ccsr_usb_phy));
1079 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1080 + sizeof(struct ccsr_usb_phy));
1083 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1084 + sizeof(struct ehci_regs));
1085 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1090 +/*Restore usb registers */
1091 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1093 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1094 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1095 + void __iomem *non_ehci = hcd->regs;
1096 + struct device *dev = hcd->self.controller;
1097 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1099 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1101 + _memcpy_toio(phy_reg,
1102 + (void *)&ehci_fsl->saved_phy_regs,
1103 + sizeof(struct ccsr_usb_phy));
1106 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1107 + sizeof(struct ehci_regs));
1108 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1114 #ifdef CONFIG_PPC_MPC512x
1115 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1116 @@ -535,26 +741,43 @@ static inline int ehci_fsl_mpc512x_drv_r
1118 #endif /* CONFIG_PPC_MPC512x */
1120 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1122 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1124 - return container_of(ehci, struct ehci_fsl, ehci);
1127 static int ehci_fsl_drv_suspend(struct device *dev)
1129 struct usb_hcd *hcd = dev_get_drvdata(dev);
1130 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1131 void __iomem *non_ehci = hcd->regs;
1132 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1133 + struct usb_bus host = hcd->self;
1137 +suspend_state_t pm_state;
1138 +pm_state = pm_suspend_state();
1140 +if (pm_state == PM_SUSPEND_MEM)
1141 + ehci_fsl_save_context(hcd);
1144 if (of_device_is_compatible(dev->parent->of_node,
1145 "fsl,mpc5121-usb2-dr")) {
1146 return ehci_fsl_mpc512x_drv_suspend(dev);
1149 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1150 + if (host.is_otg) {
1151 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1154 + ehci_fsl->hcd_add = 0;
1155 + schedule_work(&ehci->change_hcd_work);
1161 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1162 device_may_wakeup(dev));
1164 if (!fsl_deep_sleep())
1167 @@ -568,12 +791,34 @@ static int ehci_fsl_drv_resume(struct de
1168 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1169 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1170 void __iomem *non_ehci = hcd->regs;
1171 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1172 + struct usb_bus host = hcd->self;
1176 +suspend_state_t pm_state;
1177 +pm_state = pm_suspend_state();
1179 +if (pm_state == PM_SUSPEND_MEM)
1180 + ehci_fsl_restore_context(hcd);
1183 if (of_device_is_compatible(dev->parent->of_node,
1184 "fsl,mpc5121-usb2-dr")) {
1185 return ehci_fsl_mpc512x_drv_resume(dev);
1188 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1189 + if (host.is_otg) {
1191 + ehci_fsl->hcd_add = 1;
1192 + schedule_work(&ehci->change_hcd_work);
1193 + usb_hcd_resume_root_hub(hcd);
1199 ehci_prepare_ports_for_controller_resume(ehci);
1200 if (!fsl_deep_sleep())
1202 --- a/drivers/usb/host/ehci-fsl.h
1203 +++ b/drivers/usb/host/ehci-fsl.h
1205 #define UTMI_PHY_EN (1<<9)
1206 #define ULPI_PHY_CLK_SEL (1<<10)
1207 #define PHY_CLK_VALID (1<<17)
1209 +/* Retry count for checking UTMI PHY CLK validity */
1210 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1211 #endif /* _EHCI_FSL_H */
1212 --- a/drivers/usb/host/ehci-hub.c
1213 +++ b/drivers/usb/host/ehci-hub.c
1214 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
1215 USB_PORT_STAT_HIGH_SPEED)
1216 fs_idle_delay = true;
1217 ehci_writel(ehci, t2, reg);
1218 + if (ehci_has_fsl_susp_errata(ehci))
1219 + usleep_range(10000, 20000);
1223 --- a/drivers/usb/host/ehci.h
1224 +++ b/drivers/usb/host/ehci.h
1225 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1226 unsigned periodic_count; /* periodic activity count */
1227 unsigned uframe_periodic_max; /* max periodic time per uframe */
1229 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1230 + struct work_struct change_hcd_work;
1233 /* list of itds & sitds completed while now_frame was still active */
1234 struct list_head cached_itd_list;
1235 @@ -706,8 +709,10 @@ ehci_port_speed(struct ehci_hcd *ehci, u
1236 * incoming packets get corrupted in HS mode
1238 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
1239 +#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
1241 #define ehci_has_fsl_hs_errata(e) (0)
1242 +#define ehci_has_fsl_susp_errata(e) (0)
1246 --- a/drivers/usb/host/fsl-mph-dr-of.c
1247 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1248 @@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
1249 of_property_read_bool(np, "fsl,usb-erratum-a007792");
1250 pdata->has_fsl_erratum_a005275 =
1251 of_property_read_bool(np, "fsl,usb-erratum-a005275");
1252 + pdata->has_fsl_erratum_a005697 =
1253 + of_property_read_bool(np, "fsl,usb_erratum-a005697");
1254 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1255 + pdata->has_fsl_erratum_a006918 = 1;
1257 + pdata->has_fsl_erratum_a006918 = 0;
1259 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1260 + pdata->has_fsl_erratum_14 = 1;
1262 + pdata->has_fsl_erratum_14 = 0;
1266 * Determine whether phy_clk_valid needs to be checked
1267 --- a/drivers/usb/phy/phy-fsl-usb.c
1268 +++ b/drivers/usb/phy/phy-fsl-usb.c
1271 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1272 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1274 * Author: Li Yang <LeoLi@freescale.com>
1275 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1276 @@ -463,6 +463,7 @@ void otg_reset_controller(void)
1277 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1279 struct usb_otg *otg = fsm->otg;
1280 + struct usb_bus *host = otg->host;
1282 struct fsl_otg *otg_dev =
1283 container_of(otg->usb_phy, struct fsl_otg, phy);
1284 @@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1285 otg_reset_controller();
1286 VDBG("host on......\n");
1287 if (dev->driver->pm && dev->driver->pm->resume) {
1289 retval = dev->driver->pm->resume(dev);
1292 @@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1294 VDBG("host off......\n");
1295 if (dev && dev->driver) {
1296 - if (dev->driver->pm && dev->driver->pm->suspend)
1297 + if (dev->driver->pm &&
1298 + dev->driver->pm->suspend) {
1300 retval = dev->driver->pm->suspend(dev);
1304 fsl_otg_drv_vbus(fsm, 0);
1305 @@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1306 dev = otg->gadget->dev.parent;
1309 - if (dev->driver->resume)
1310 + /* Delay gadget resume to synchronize between host and gadget
1311 + * drivers. Upon role-reversal host drv is shutdown by kernel
1312 + * worker thread. By the time host drv shuts down, controller
1313 + * gets programmed for gadget role. Shutting host drv after
1314 + * this results in controller getting reset, and it stops
1315 + * responding to otg events
1317 + if (dev->driver->resume) {
1319 dev->driver->resume(dev);
1322 if (dev->driver->suspend)
1323 dev->driver->suspend(dev, otg_suspend_state);
1324 @@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_st
1325 fsl_otg_start_host(fsm, 0);
1326 otg_drv_vbus(fsm, 0);
1327 fsl_otg_start_gadget(fsm, 1);
1329 + fsl_otg_start_gadget(fsm, 0);
1330 + otg_drv_vbus(fsm, 1);
1331 + fsl_otg_start_host(fsm, 1);
1335 @@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1337 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1338 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1339 + struct fsl_otg *otg_dev = dev_id;
1340 u32 otg_int_src, otg_sc;
1342 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1343 @@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1344 otg->gadget->is_a_peripheral = !fsm->id;
1345 VDBG("ID int (ID is %d)\n", fsm->id);
1347 - if (fsm->id) { /* switch to gadget */
1348 - schedule_delayed_work(
1349 - &((struct fsl_otg *)dev_id)->otg_event,
1351 - } else { /* switch to host */
1352 - cancel_delayed_work(&
1353 - ((struct fsl_otg *)dev_id)->
1355 - fsl_otg_start_gadget(fsm, 0);
1356 - otg_drv_vbus(fsm, 1);
1357 - fsl_otg_start_host(fsm, 1);
1359 + schedule_delayed_work(&otg_dev->otg_event, 100);
1364 @@ -923,12 +932,32 @@ int usb_otg_start(struct platform_device
1365 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1366 switch (pdata->phy_mode) {
1367 case FSL_USB2_PHY_ULPI:
1368 + if (pdata->controller_ver) {
1369 + /* controller version 1.6 or above */
1370 + setbits32(&p_otg->dr_mem_map->control,
1371 + USB_CTRL_ULPI_PHY_CLK_SEL);
1373 + * Due to controller issue of PHY_CLK_VALID in ULPI
1374 + * mode, we set USB_CTRL_USB_EN before checking
1375 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1377 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1378 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1380 temp |= PORTSC_PTS_ULPI;
1382 case FSL_USB2_PHY_UTMI_WIDE:
1383 temp |= PORTSC_PTW_16BIT;
1385 case FSL_USB2_PHY_UTMI:
1386 + if (pdata->controller_ver) {
1387 + /* controller version 1.6 or above */
1388 + setbits32(&p_otg->dr_mem_map->control,
1389 + USB_CTRL_UTMI_PHY_EN);
1390 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1391 + mdelay(FSL_UTMI_PHY_DLY);
1393 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1394 temp |= PORTSC_PTS_UTMI;
1397 --- a/drivers/usb/phy/phy-fsl-usb.h
1398 +++ b/drivers/usb/phy/phy-fsl-usb.h
1399 @@ -199,6 +199,14 @@
1400 /* control Register Bit Masks */
1401 #define USB_CTRL_IOENB (0x1<<2)
1402 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1403 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1404 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1405 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1406 +#define USB_CTRL_OTG_PORT (0x1<<5)
1407 +#define USB_CTRL_PLL_RESET (0x1<<8)
1408 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1409 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1410 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1413 #define BCSR5_INT_USB (0x02)
1414 --- a/include/linux/usb.h
1415 +++ b/include/linux/usb.h
1416 @@ -362,6 +362,7 @@ struct usb_bus {
1417 * for control transfers?
1419 u8 otg_port; /* 0, or number of OTG/HNP port */
1420 + unsigned is_otg:1; /* true when host is also otg */
1421 unsigned is_b_host:1; /* true during some HNP roleswitches */
1422 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1423 unsigned no_stop_on_short:1; /*
1424 --- a/include/linux/usb/of.h
1425 +++ b/include/linux/usb/of.h
1427 #include <linux/usb/otg.h>
1428 #include <linux/usb/phy.h>
1430 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1432 #if IS_ENABLED(CONFIG_OF)
1433 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1434 bool of_usb_host_tpl_support(struct device_node *np);