1 From 3724107421d95c5a46b19b950b04de2a05c1f757 Mon Sep 17 00:00:00 2001
2 From: Pankaj Bansal <pankaj.bansal@nxp.com>
3 Date: Wed, 8 May 2019 17:49:14 +0530
4 Subject: [PATCH] arm64: dts: fsl: ls1028a: add flexcan node
6 Add flexcan node in LS1028A SOC file as well as in QDS and RDB files.
7 The device tree bindings used can be referred from
8 Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
10 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
12 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 10 +++++++++-
13 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 18 +++++++++++++++++-
14 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 22 +++++++++++++++++++++-
15 3 files changed, 47 insertions(+), 3 deletions(-)
17 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
18 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
21 * Device Tree file for NXP LS1028A QDS Board.
23 - * Copyright 2018 NXP
24 + * Copyright 2018-2019 NXP
26 * Harninder Rai <harninder.rai@nxp.com>
43 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
44 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
47 * Device Tree file for NXP LS1028A RDB Board.
49 - * Copyright 2018 NXP
50 + * Copyright 2018-2019 NXP
52 * Harninder Rai <harninder.rai@nxp.com>
62 + max-bitrate = <5000000>;
70 + max-bitrate = <5000000>;
77 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
78 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
81 * Device Tree Include file for NXP Layerscape-1028A family SoC.
83 - * Copyright 2018 NXP
84 + * Copyright 2018-2019 NXP
86 * Harninder Rai <harninder.rai@nxp.com>
93 + compatible = "fsl,ls1028ar1-flexcan",
94 + "fsl,lx2160ar1-flexcan";
95 + reg = <0x0 0x2180000 0x0 0x10000>;
96 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
97 + clocks = <&sysclk>, <&clockgen 4 1>;
98 + clock-names = "ipg", "per";
99 + status = "disabled";
102 + can1: can@2190000 {
103 + compatible = "fsl,ls1028ar1-flexcan",
104 + "fsl,lx2160ar1-flexcan";
105 + reg = <0x0 0x2190000 0x0 0x10000>;
106 + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
107 + clocks = <&sysclk>, <&clockgen 4 1>;
108 + clock-names = "ipg", "per";
109 + status = "disabled";
112 duart0: serial@21c0500 {
113 compatible = "fsl,ns16550", "ns16550a";
114 reg = <0x00 0x21c0500 0x0 0x100>;