2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
12 #include "mt7622.dtsi"
13 #include "mt6380.dtsi"
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
36 sram-supply = <&mt6380_vm_reg>;
41 compatible = "gpio-keys";
46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
57 compatible = "gpio-leds";
60 label = "bpi-r64:pio:green";
61 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
62 default-state = "off";
66 label = "bpi-r64:pio:red";
67 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
73 reg = <0 0x40000000 0 0x40000000>;
76 reg_1p8v: regulator-1p8v {
77 compatible = "regulator-fixed";
78 regulator-name = "fixed-1.8V";
79 regulator-min-microvolt = <1800000>;
80 regulator-max-microvolt = <1800000>;
84 reg_3p3v: regulator-3p3v {
85 compatible = "regulator-fixed";
86 regulator-name = "fixed-3.3V";
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
93 reg_5v: regulator-5v {
94 compatible = "regulator-fixed";
95 regulator-name = "fixed-5V";
96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&irrx_pins>;
120 compatible = "mediatek,eth-mac";
122 phy-mode = "2500base-x";
132 compatible = "mediatek,eth-mac";
144 #address-cells = <1>;
148 compatible = "mediatek,mt7531";
150 reset-gpios = <&pio 54 0>;
153 #address-cells = <1>;
185 phy-mode = "2500base-x";
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c1_pins>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&i2c2_pins>;
212 pinctrl-names = "default", "state_uhs";
213 pinctrl-0 = <&emmc_pins_default>;
214 pinctrl-1 = <&emmc_pins_uhs>;
217 max-frequency = <50000000>;
220 vmmc-supply = <®_3p3v>;
221 vqmmc-supply = <®_1p8v>;
222 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
223 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
228 pinctrl-names = "default", "state_uhs";
229 pinctrl-0 = <&sd0_pins_default>;
230 pinctrl-1 = <&sd0_pins_uhs>;
233 max-frequency = <50000000>;
236 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
237 vmmc-supply = <®_3p3v>;
238 vqmmc-supply = <®_3p3v>;
239 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
240 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
244 pinctrl-names = "default";
245 pinctrl-0 = <¶llel_nand_pins>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&spi_nor_pins>;
255 compatible = "jedec,spi-nor";
261 pinctrl-names = "default";
262 pinctrl-0 = <&pcie0_pins>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pcie1_pins>;
273 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
274 * SATA functions. i.e. output-high: PCIe, output-low: SATA
278 gpios = <90 GPIO_ACTIVE_HIGH>;
282 /* eMMC is shared pin with parallel NAND */
283 emmc_pins_default: emmc-pins-default {
285 function = "emmc", "emmc_rst";
289 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
290 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
291 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
294 pins = "NDL0", "NDL1", "NDL2",
295 "NDL3", "NDL4", "NDL5",
296 "NDL6", "NDL7", "NRB";
307 emmc_pins_uhs: emmc-pins-uhs {
314 pins = "NDL0", "NDL1", "NDL2",
315 "NDL3", "NDL4", "NDL5",
316 "NDL6", "NDL7", "NRB";
318 drive-strength = <4>;
324 drive-strength = <4>;
332 groups = "mdc_mdio", "rgmii_via_gmac2";
336 i2c1_pins: i2c1-pins {
343 i2c2_pins: i2c2-pins {
350 i2s1_pins: i2s1-pins {
353 groups = "i2s_out_mclk_bclk_ws",
359 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
360 "I2S_WS", "I2S_MCLK";
361 drive-strength = <12>;
366 irrx_pins: irrx-pins {
373 irtx_pins: irtx-pins {
380 /* Parallel nand is shared pin with eMMC */
381 parallel_nand_pins: parallel-nand-pins {
388 pcie0_pins: pcie0-pins {
391 groups = "pcie0_pad_perst",
397 pcie1_pins: pcie1-pins {
400 groups = "pcie1_pad_perst",
406 pmic_bus_pins: pmic-bus-pins {
413 pwm7_pins: pwm1-2-pins {
416 groups = "pwm_ch7_2";
420 wled_pins: wled-pins {
427 sd0_pins_default: sd0-pins-default {
433 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
434 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
435 * DAT2, DAT3, CMD, CLK for SD respectively.
438 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
439 "I2S2_IN","I2S4_OUT";
441 drive-strength = <8>;
446 drive-strength = <12>;
455 sd0_pins_uhs: sd0-pins-uhs {
462 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
463 "I2S2_IN","I2S4_OUT";
474 /* Serial NAND is shared pin with SPI-NOR */
475 serial_nand_pins: serial-nand-pins {
482 spic0_pins: spic0-pins {
489 spic1_pins: spic1-pins {
496 /* SPI-NOR is shared pin with serial NAND */
497 spi_nor_pins: spi-nor-pins {
504 /* serial NAND is shared pin with SPI-NOR */
505 serial_nand_pins: serial-nand-pins {
512 uart0_pins: uart0-pins {
515 groups = "uart0_0_tx_rx" ;
519 uart2_pins: uart2-pins {
522 groups = "uart2_1_tx_rx" ;
526 watchdog_pins: watchdog-pins {
528 function = "watchdog";
535 pinctrl-names = "default";
536 pinctrl-0 = <&pwm7_pins>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&pmic_bus_pins>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&spic0_pins>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&spic1_pins>;
568 vusb33-supply = <®_3p3v>;
569 vbus-supply = <®_5v>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&uart0_pins>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&uart2_pins>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&watchdog_pins>;