1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
12 model = "ELECOM WRC-X3200GST3";
13 compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622";
17 led-boot = &led_power_green;
18 led-failsafe = &led_power_red;
19 led-running = &led_power_green;
20 led-upgrade = &led_power_green;
21 label-mac-device = &wan;
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
29 reg = <0 0x40000000 0 0x1f000000>;
33 compatible = "gpio-leds";
36 gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
37 color = <LED_COLOR_ID_RED>;
38 function = LED_FUNCTION_WPS;
41 led_power_red: led-1 {
42 gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
43 color = <LED_COLOR_ID_RED>;
44 function = LED_FUNCTION_POWER;
45 function-enumerator = <1>;
48 led_power_green: led-2 {
49 gpios = <&pio 49 GPIO_ACTIVE_HIGH>;
50 color = <LED_COLOR_ID_GREEN>;
51 function = LED_FUNCTION_POWER;
52 function-enumerator = <2>;
56 gpios = <&pio 50 GPIO_ACTIVE_HIGH>;
57 color = <LED_COLOR_ID_BLUE>;
58 function = LED_FUNCTION_POWER;
59 function-enumerator = <3>;
63 gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
64 color = <LED_COLOR_ID_WHITE>;
65 function = LED_FUNCTION_WLAN;
66 function-enumerator = <1>;
67 linux,default-trigger = "phy0tpt";
71 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
72 color = <LED_COLOR_ID_WHITE>;
73 function = LED_FUNCTION_WLAN;
74 function-enumerator = <2>;
75 linux,default-trigger = "phy1radio";
80 compatible = "gpio-keys";
84 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_RESTART>;
90 gpios = <&pio 42 GPIO_ACTIVE_LOW>;
92 linux,input-type = <EV_SW>;
97 gpios = <&pio 43 GPIO_ACTIVE_LOW>;
99 linux,input-type = <EV_SW>;
104 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
105 linux,code = <KEY_WPS_BUTTON>;
111 proc-supply = <&mt6380_vcpu_reg>;
112 sram-supply = <&mt6380_vm_reg>;
116 proc-supply = <&mt6380_vcpu_reg>;
117 sram-supply = <&mt6380_vm_reg>;
124 groups = "mdc_mdio", "rgmii_via_gmac2";
128 pcie0_pins: pcie0-pins {
131 groups = "pcie0_pad_perst",
137 pmic_bus_pins: pmic-bus-pins {
144 pwm7_pins: pwm1-2-pins {
147 groups = "pwm_ch7_2";
151 /* Serial NAND is shared pin with SPI-NOR */
152 serial_nand_pins: serial-nand-pins {
159 pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI",
160 "SPI_MISO", "SPI_CS";
161 drive-strength = <16>;
167 drive-strength = <16>;
172 uart0_pins: uart0-pins {
175 groups = "uart0_0_tx_rx" ;
179 watchdog_pins: watchdog-pins {
181 function = "watchdog";
188 pinctrl-names = "default";
189 pinctrl-0 = <ð_pins>;
193 compatible = "mediatek,eth-mac";
196 phy-connection-type = "2500base-x";
198 nvmem-cells = <&macaddr_factory_7fff4>;
199 nvmem-cell-names = "mac-address";
209 #address-cells = <1>;
213 compatible = "mediatek,mt7531";
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 interrupt-parent = <&pio>;
218 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
219 reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
222 #address-cells = <1>;
229 nvmem-cells = <&macaddr_factory_7fffa>;
230 nvmem-cell-names = "mac-address";
256 phy-mode = "2500base-x";
274 pinctrl-names = "default";
275 pinctrl-0 = <&serial_nand_pins>;
279 compatible = "spi-nand";
281 spi-tx-bus-width = <4>;
282 spi-rx-bus-width = <4>;
283 nand-ecc-engine = <&snfi>;
285 mediatek,bmt-table-size = <0x1000>;
286 mediatek,bmt-remap-range = <0x0 0x8c0000>,
287 <0x1bc0000 0x30c0000>;
290 compatible = "fixed-partitions";
291 #address-cells = <1>;
302 reg = <0x80000 0x40000>;
308 reg = <0xc0000 0x80000>;
313 label = "u-boot-env";
314 reg = <0x140000 0x80000>;
318 factory: partition@1c0000 {
320 reg = <0x1c0000 0x100000>;
324 compatible = "fixed-layout";
325 #address-cells = <1>;
328 macaddr_factory_4: macaddr@4 {
329 compatible = "mac-base";
331 #nvmem-cell-cells = <1>;
334 macaddr_factory_7fff4: macaddr@7fff4 {
338 macaddr_factory_7fffa: macaddr@7fffa {
346 reg = <0x2c0000 0x600000>;
351 reg = <0x8c0000 0x1300000>;
355 label = "tm_pattern";
356 reg = <0x1bc0000 0x500000>;
362 reg = <0x20c0000 0x100000>;
368 reg = <0x21c0000 0xf00000>;
374 reg = <0x30c0000 0x4f40000>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pcie0_pins>;
391 compatible = "mediatek,mt76";
392 reg = <0x0000 0 0 0 0>;
393 mediatek,mtd-eeprom = <&factory 0x5000>;
394 ieee80211-freq-limit = <5000000 6000000>;
395 nvmem-cells = <&macaddr_factory_4 1>;
396 nvmem-cell-names = "mac-address";
401 pinctrl-names = "default";
402 pinctrl-0 = <&pwm7_pins>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pmic_bus_pins>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart0_pins>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&watchdog_pins>;
431 mediatek,mtd-eeprom = <&factory 0x0>;