1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/pinctrl/mt65xx.h>
12 compatible = "linksys,e8450", "mediatek,mt7622";
16 led-boot = &led_power;
17 led-failsafe = &led_power;
18 led-running = &led_power;
19 led-upgrade = &led_power;
23 stdout-path = "serial0:115200n8";
24 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
29 proc-supply = <&mt6380_vcpu_reg>;
30 sram-supply = <&mt6380_vm_reg>;
34 proc-supply = <&mt6380_vcpu_reg>;
35 sram-supply = <&mt6380_vm_reg>;
40 compatible = "gpio-keys";
44 linux,code = <KEY_RESTART>;
45 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_WPS_BUTTON>;
51 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
56 compatible = "gpio-leds";
58 led_power: power_blue {
60 gpios = <&pio 95 GPIO_ACTIVE_LOW>;
65 label = "power:orange";
66 gpios = <&pio 96 GPIO_ACTIVE_LOW>;
67 default-state = "off";
72 gpios = <&pio 97 GPIO_ACTIVE_LOW>;
73 default-state = "off";
77 label = "inet:orange";
78 gpios = <&pio 98 GPIO_ACTIVE_LOW>;
79 default-state = "off";
84 reg = <0 0x40000000 0 0x40000000>;
87 reg_1p8v: regulator-1p8v {
88 compatible = "regulator-fixed";
89 regulator-name = "fixed-1.8V";
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
95 reg_3p3v: regulator-3p3v {
96 compatible = "regulator-fixed";
97 regulator-name = "fixed-3.3V";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
104 reg_5v: regulator-5v {
105 compatible = "regulator-fixed";
106 regulator-name = "fixed-5V";
107 regulator-min-microvolt = <5000000>;
108 regulator-max-microvolt = <5000000>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&irrx_pins>;
121 pinctrl-names = "default";
122 pinctrl-0 = <ð_pins>;
126 compatible = "mediatek,eth-mac";
128 phy-mode = "2500base-x";
138 #address-cells = <1>;
142 compatible = "mediatek,mt7531";
144 interrupt-controller;
145 #interrupt-cells = <1>;
146 interrupt-parent = <&pio>;
147 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
148 reset-gpios = <&pio 54 0>;
151 #address-cells = <1>;
182 phy-mode = "2500base-x";
197 pinctrl-names = "default";
198 pinctrl-0 = <&pcie0_pins>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pcie1_pins>;
212 groups = "mdc_mdio", "rgmii_via_gmac2";
216 irrx_pins: irrx-pins {
223 irtx_pins: irtx-pins {
230 pcie0_pins: pcie0-pins {
233 groups = "pcie0_pad_perst",
239 pcie1_pins: pcie1-pins {
242 groups = "pcie1_pad_perst",
248 pmic_bus_pins: pmic-bus-pins {
255 pwm7_pins: pwm1-2-pins {
258 groups = "pwm_ch7_2";
262 wled_pins: wled-pins {
269 /* Serial NAND is shared pin with SPI-NOR */
270 serial_nand_pins: serial-nand-pins {
278 drive-strength = <MTK_DRIVE_12mA>;
282 spic0_pins: spic0-pins {
289 spic1_pins: spic1-pins {
296 uart0_pins: uart0-pins {
299 groups = "uart0_0_tx_rx" ;
303 uart2_pins: uart2-pins {
306 groups = "uart2_1_tx_rx" ;
310 watchdog_pins: watchdog-pins {
312 function = "watchdog";
319 pinctrl-names = "default";
320 pinctrl-0 = <&pwm7_pins>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pmic_bus_pins>;
341 compatible = "mediatek,mt76";
342 reg = <0x0000 0 0 0 0>;
343 ieee80211-freq-limit = <5000000 6000000>;
344 mediatek,disable-radar-background;
353 pinctrl-names = "default";
354 pinctrl-0 = <&serial_nand_pins>;
358 compatible = "spi-nand";
360 spi-tx-bus-width = <4>;
361 spi-rx-bus-width = <4>;
362 nand-ecc-engine = <&snfi>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&spic0_pins>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&spic1_pins>;
379 vusb33-supply = <®_3p3v>;
380 vbus-supply = <®_5v>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart0_pins>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2_pins>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&watchdog_pins>;