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[openwrt/openwrt.git] / target / linux / mediatek / dts / mt7986a-bananapi-bpi-r3.dts
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
10
11 #include "mt7986a.dtsi"
12
13 / {
14 model = "Bananapi BPI-R3";
15 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
16
17 aliases {
18 serial0 = &uart0;
19 ethernet0 = &gmac0;
20 ethernet1 = &gmac1;
21 led-boot = &led_status_green;
22 led-failsafe = &led_status_green;
23 led-running = &led_status_green;
24 led-upgrade = &led_status_blue;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 };
30
31 memory@40000000 {
32 device_type = "memory";
33 reg = <0 0x40000000 0 0x40000000>;
34 };
35
36 reg_1p8v: regulator-1p8v {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-1.8V";
39 regulator-min-microvolt = <1800000>;
40 regulator-max-microvolt = <1800000>;
41 regulator-boot-on;
42 regulator-always-on;
43 };
44
45 reg_3p3v: regulator-3p3v {
46 compatible = "regulator-fixed";
47 regulator-name = "fixed-3.3V";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 regulator-boot-on;
51 regulator-always-on;
52 };
53
54 reg_5v: regulator-5v {
55 compatible = "regulator-fixed";
56 regulator-name = "fixed-5V";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
63 keys {
64 compatible = "gpio-keys";
65
66 /*
67 * RST button is also PCIe-CLKREQ signal, use WPS button as reset
68 * instead as RST button doesn't make sense and cannot be used.
69 *
70 * intended buttons:
71 factory {
72 label = "reset";
73 linux,code = <KEY_RESTART>;
74 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
75 };
76
77 wps {
78 label = "wps";
79 linux,code = <KEY_WPS_BUTTON>;
80 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
81 };
82 * actual setup:
83 */
84 wps {
85 label = "wps";
86 linux,code = <KEY_RESTART>;
87 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
88 };
89 };
90
91 leds {
92 compatible = "gpio-leds";
93
94 led_status_green: green {
95 label = "green:status";
96 gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
97 default-state = "on";
98 };
99
100 led_status_blue: blue {
101 label = "blue:status";
102 gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
103 };
104 };
105
106 /* SFP1 cage (WAN) */
107 i2c_sfp1: i2c-gpio-0 {
108 compatible = "i2c-gpio";
109 sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
110 scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
111 i2c-gpio,delay-us = <2>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
116 sfp1: sfp1 {
117 compatible = "sff,sfp";
118 i2c-bus = <&i2c_sfp1>;
119 los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
120 mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
121 tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
122 tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
123 };
124
125 /* SFP2 cage (LAN) */
126 i2c_sfp2: i2c-gpio-1 {
127 compatible = "i2c-gpio";
128 sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
129 scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
130 i2c-gpio,delay-us = <2>;
131 #address-cells = <1>;
132 #size-cells = <0>;
133 };
134
135 sfp2: sfp2 {
136 compatible = "sff,sfp";
137 i2c-bus = <&i2c_sfp2>;
138 los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
139 mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
140 tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
141 tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
142 };
143 };
144
145 &eth {
146 status = "okay";
147
148 gmac0: mac@0 {
149 compatible = "mediatek,eth-mac";
150 reg = <0>;
151 phy-mode = "2500base-x";
152
153 fixed-link {
154 speed = <2500>;
155 full-duplex;
156 pause;
157 };
158 };
159
160 gmac1: mac@1 {
161 compatible = "mediatek,eth-mac";
162 reg = <1>;
163 phy-mode = "2500base-x";
164 sfp = <&sfp1>;
165 managed = "in-band-status";
166 };
167
168 mdio: mdio-bus {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 };
172 };
173
174 &mdio {
175 switch: switch@0 {
176 compatible = "mediatek,mt7531";
177 reg = <31>;
178 reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 interrupt-parent = <&pio>;
182 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
183 };
184 };
185
186 &switch {
187 ports {
188 #address-cells = <1>;
189 #size-cells = <0>;
190
191 port@0 {
192 reg = <0>;
193 label = "wan";
194 };
195
196 port@1 {
197 reg = <1>;
198 label = "lan1";
199 };
200
201 port@2 {
202 reg = <2>;
203 label = "lan2";
204 };
205
206 port@3 {
207 reg = <3>;
208 label = "lan3";
209 };
210
211 port@4 {
212 reg = <4>;
213 label = "lan4";
214 };
215
216 port5: port@5 {
217 reg = <5>;
218 label = "sfp2";
219 phy-mode = "2500base-x";
220 sfp = <&sfp2>;
221 managed = "in-band-status";
222 };
223
224 port@6 {
225 reg = <6>;
226 label = "cpu";
227 ethernet = <&gmac0>;
228 phy-mode = "2500base-x";
229
230 fixed-link {
231 speed = <2500>;
232 full-duplex;
233 pause;
234 };
235 };
236 };
237 };
238
239 &crypto {
240 status = "okay";
241 };
242
243 &mmc0 {
244 //sdcard
245 pinctrl-names = "default", "state_uhs";
246 pinctrl-0 = <&mmc0_pins_default>;
247 pinctrl-1 = <&mmc0_pins_uhs>;
248 bus-width = <4>;
249 max-frequency = <52000000>;
250 cap-sd-highspeed;
251 vmmc-supply = <&reg_3p3v>;
252 vqmmc-supply = <&reg_1p8v>;
253 status = "okay";
254 };
255
256 &pcie {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pcie_pins>;
259 status = "okay";
260 };
261
262 &pcie_phy {
263 status = "okay";
264 };
265
266 &wmac {
267 status = "okay";
268 pinctrl-names = "default", "dbdc";
269 pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
270 pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
271 };
272
273 &pio {
274 /* don't mess around with GPIO 419, 450, 451, 498, 510 in sysfs system will freeze. */
275 mmc0_pins_default: mmc0-pins {
276 mux {
277 function = "emmc";
278 groups = "emmc_51";
279 };
280 conf-cmd-dat {
281 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
282 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
283 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
284 input-enable;
285 drive-strength = <4>;
286 mediatek,pull-up-adv = <1>; /* pull-up 10K */
287 };
288 conf-clk {
289 pins = "EMMC_CK";
290 drive-strength = <6>;
291 mediatek,pull-down-adv = <2>; /* pull-down 50K */
292 };
293 conf-ds {
294 pins = "EMMC_DSL";
295 mediatek,pull-down-adv = <2>; /* pull-down 50K */
296 };
297 conf-rst {
298 pins = "EMMC_RSTB";
299 drive-strength = <4>;
300 mediatek,pull-up-adv = <1>; /* pull-up 10K */
301 };
302 };
303
304 mmc0_pins_uhs: mmc0-uhs-pins {
305 mux {
306 function = "emmc";
307 groups = "emmc_51";
308 };
309 conf-cmd-dat {
310 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
311 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
312 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
313 input-enable;
314 drive-strength = <4>;
315 mediatek,pull-up-adv = <1>; /* pull-up 10K */
316 };
317 conf-clk {
318 pins = "EMMC_CK";
319 drive-strength = <6>;
320 mediatek,pull-down-adv = <2>; /* pull-down 50K */
321 };
322 conf-ds {
323 pins = "EMMC_DSL";
324 mediatek,pull-down-adv = <2>; /* pull-down 50K */
325 };
326 conf-rst {
327 pins = "EMMC_RSTB";
328 drive-strength = <4>;
329 mediatek,pull-up-adv = <1>; /* pull-up 10K */
330 };
331 };
332
333 pcie_pins: pcie-pins {
334 mux {
335 function = "pcie";
336 groups = "pcie_clk", "pcie_pereset"; //"pcie_wake" is unused
337 };
338 };
339
340 spi_flash_pins: spi-flash-pins {
341 mux {
342 function = "spi";
343 groups = "spi0", "spi0_wp_hold";
344 };
345 };
346
347 uart1_pins: uart1-pins {
348 mux {
349 function = "uart";
350 groups = "uart1";
351 };
352 };
353
354 i2c0_pins: i2c0-pins {
355 mux {
356 function = "i2c";
357 groups = "i2c";
358 };
359 };
360
361 pwm_pins: pwm-pins {
362 mux {
363 function = "pwm";
364 groups = "pwm0", "pwm1_0";
365 };
366 };
367
368 wf_led_pins: wf-led-pins {
369 mux {
370 function = "led";
371 groups = "wifi_led";
372 };
373 };
374
375 wf_2g_5g_pins: wf-2g-5g-pins {
376 mux {
377 function = "wifi";
378 groups = "wf_2g", "wf_5g";
379 };
380 conf {
381 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
382 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
383 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
384 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
385 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
386 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
387 "WF1_TOP_CLK", "WF1_TOP_DATA";
388 drive-strength = <4>;
389 };
390 };
391
392 wf_dbdc_pins: wf-dbdc-pins {
393 mux {
394 function = "wifi";
395 groups = "wf_dbdc";
396 };
397 conf {
398 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
399 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
400 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
401 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
402 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
403 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
404 "WF1_TOP_CLK", "WF1_TOP_DATA";
405 drive-strength = <4>;
406 };
407 };
408 };
409
410 &spi0 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&spi_flash_pins>;
413
414 status = "okay";
415 };
416
417 &ssusb {
418 vusb33-supply = <&reg_3p3v>;
419 vbus-supply = <&reg_5v>;
420 status = "okay";
421 };
422
423 &uart0 {
424 status = "okay";
425 };
426
427 &uart1 {
428 pinctrl-names = "default";
429 pinctrl-0 = <&uart1_pins>;
430 status = "okay";
431 };
432
433 &usb_phy {
434 status = "okay";
435 };
436
437 &i2c0 {
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c0_pins>;
440 status = "okay";
441 };
442
443 &pwm {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pwm_pins>;
446 status = "okay";
447 };
448
449 &fan {
450 pwms = <&pwm 0 500000 0>;
451 status = "okay";
452 };
453
454 &wmac {
455 mediatek,eeprom-data = <0x86790900 0xc4326 0x60000000 0x00 0x00 0x00 0x00 0x00
456 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
457 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000000
458 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
459 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
460 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
461 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
462 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
463 0x00 0x800 0x00 0x00 0x00 0x00 0x00 0x00
464 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
465 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
466 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
467 0x00 0x00 0x00 0x00 0x24649090 0x280000 0x5100000 0x00
468 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
469 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
470 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
471 0x21e00 0x21e0002 0x1e00021e 0x22800 0x2280002 0x28000228 0x00 0x00
472 0x00 0x00 0x00 0x00 0x00 0x00 0x8080 0x8080fdf7
473 0x903150d 0x80808080 0x80808080 0x5050d0d 0x1313c6c6 0xc3c3c200 0xc200c2 0x8182
474 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
475 0xc2000081 0x82858587 0x87c2c200 0x818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
476 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0xc3
477 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
478 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
479 0x222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
480 0xeeeeeecc 0xccccdddd 0xdddddddd 0x4a5662 0x4a 0x56620000 0x4a5662 0x4a
481 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
482 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00 0xf0f0cc00
483 0x00 0xaaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
484 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00 0xaaaa 0xaa000000 0xbbbbbbbb
485 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
486 0x00 0x00 0x00 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
487 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00 0xeeee 0xeeffffff 0xcccccccc
488 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
489 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
490 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
491 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
492 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051
493 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200
494 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e 0x516200 0x686e0051 0x6200686e
495 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
496 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
497 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
498 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
499 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
500 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
501 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
502 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
503 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
504 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
505 0x00 0x00 0x00 0x00 0x01 0x6000100 0x1050002 0xff0300
506 0xf900fe03 0x00 0x00 0x9b 0x6e370000 0x00 0xfc0009 0xa00fe00
507 0x60700fe 0x70800 0x5000b0a 0x00 0x00 0xe2 0x96460000 0x00
508 0x400f7 0xf8000300 0xfcfe0003 0xfbfc00 0xee00e3f2 0x00 0x00 0x11
509 0xbb550000 0x00 0x600f6 0xfc000300 0xfbfe0004 0xfafe00 0xf600ecf2 0x00
510 0x00 0x1f 0xbf580000 0x00 0x600f5 0xf6000400 0xf8f90004 0xf7f800
511 0xf700f0f4 0x00 0x00 0x24 0xbe570000 0x00 0x800f8 0xfe000600
512 0xf8fd0007 0xf9fe00 0xf500f0f4 0x00 0x00 0x2d 0xd6610000 0x00
513 0x400f7 0xfc000500 0xf7fc0005 0xf7fc00 0xf900f5f8 0x00 0x00 0x26
514 0xd96e0000 0x00 0x400f7 0xf9000600 0xf5f70005 0xf5f800 0xf900f4f7 0x00
515 0x00 0x1b 0xce690000 0x00 0x300f8 0xf8000600 0xf6f60004 0xf6f700
516 0xf900f4f7 0x00 0x00 0x18 0xd8720000 0x00 0x00 0x2404002
517 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
518 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
519 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
520 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
521 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
522 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
523 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
524 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
525 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
526 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
527 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
528 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
529 0x3fc140c1 0x41c040c0 0x00 0x00 0x41c741c7 0xc1c7c1c7 0x00 0x00
530 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
531 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
532 0xa0ce00 0x00 0xb6840000 0x00 0x00 0x00 0x18181818 0x18181818
533 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
534 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
535 0x4b5763 0x4b 0x57630000 0x4b5763 0x4b 0x57630000 0x88888888 0x8474759
536 0x69780849 0x49596d7a 0x849495a 0x6d790848 0x48596c78 0x8484858 0x6a780848 0x48586a78
537 0x8484858 0x6c78084a 0x4a5b6d79 0x8474759 0x697a0848 0x48596b79 0x8484859 0x6c7a0848
538 0x48586c79 0x8484857 0x68770848 0x48576877 0x8484857 0x6a77084a 0x4a5a6a77 0x8464659
539 0x69790848 0x48586b79 0x8484858 0x6c7a0848 0x48596c79 0x8484857 0x68770848 0x48576877
540 0x8494958 0x6d7a084b 0x4b5c6c77 0x847475a 0x6a7b0849 0x495a6e7c 0x849495a 0x6e7c0849
541 0x495b6e7c 0x8494959 0x6a7a0849 0x49596a7a 0x84a4a5a 0x6f7d084b 0x4b5c6e7b 0x00
542 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x85848484
543 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
544 0xc0c08282 0x83848686 0x88880000 0x00 0x00 0x00 0x00 0x00
545 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
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583 };
OpenWrt Source Repository