1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
8 #include "mt7986b.dtsi"
11 model = "Netgear WAX220";
12 compatible = "netgear,wax220", "mediatek,mt7986b";
16 led-boot = &led_power_blue;
17 led-failsafe = &led_power_amber;
18 led-running = &led_power_green;
19 led-upgrade = &led_power_amber;
23 compatible = "gpio-keys";
26 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
27 linux,code = <KEY_RESTART>;
33 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
40 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
41 label = "green:wlan5g";
44 led_power_amber: power_amber {
45 gpios = <&pio 15 GPIO_ACTIVE_LOW>;
46 label = "amber:power";
50 gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
51 label = "green:wlan2g";
54 led_power_blue: power_blue {
55 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
59 led_power_green: power_green {
60 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
61 label = "green:power";
65 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
66 label = "blue:wlan2g";
70 gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
75 gpios = <&pio 13 GPIO_ACTIVE_LOW>;
80 gpios = <&pio 2 GPIO_ACTIVE_LOW>;
81 label = "blue:wlan5g";
94 compatible = "mediatek,eth-mac";
97 phy-mode = "2500base-x";
101 #address-cells = <1>;
107 phy6: ethernet-phy@6 {
109 reset-assert-us = <100000>;
110 reset-deassert-us = <100000>;
111 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
114 interrupt-parent = <&pio>;
115 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
120 spi_flash_pins: spi-flash-pins-33-to-38 {
123 groups = "spi0", "spi0_wp_hold";
126 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
127 drive-strength = <8>;
128 mediatek,pull-up-adv = <0>; /* bias-disable */
131 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
132 drive-strength = <8>;
133 mediatek,pull-down-adv = <0>; /* bias-disable */
137 wf_2g_5g_pins: wf_2g_5g-pins {
140 groups = "wf_2g", "wf_5g";
143 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
144 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
145 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
146 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
147 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
148 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
149 "WF1_TOP_CLK", "WF1_TOP_DATA";
150 drive-strength = <4>;
154 wf_dbdc_pins: wf-dbdc-pins {
160 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
161 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
162 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
163 "WF0_TOP_CLK", "WF0_TOP_DATA";
164 drive-strength = <4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&spi_flash_pins>;
174 spi_nand_flash: flash@0 {
175 #address-cells = <1>;
177 compatible = "spi-nand";
180 spi-max-frequency = <20000000>;
181 spi-tx-buswidth = <4>;
182 spi-rx-buswidth = <4>;
185 mediatek,bmt-max-ratio = <1>;
186 mediatek,bmt-max-reserved-blocks = <256>;
187 mediatek,bmt-remap-range = <0x0 0x580000>;
189 partitions: partitions {
190 #address-cells = <0x1>;
192 compatible = "fixed-partitions";
197 reg = <0x0 0x100000>;
201 label = "u-boot-env";
202 reg = <0x100000 0x80000>;
205 factory: partition@180000 {
207 reg = <0x180000 0x200000>;
212 reg = <0x380000 0x200000>;
217 reg = <0x580000 0x5140000>;
222 reg = <0x56c0000 0x400000>;
227 reg = <0x5ac0000 0x100000>;
232 reg = <0x5bc0000 0x400000>;
237 reg = <0x5fc0000 0x200000>;
242 reg = <0x61c0000 0x100000>;
246 label = "NTGRcryptK";
247 reg = <0x62c0000 0x100000>;
251 label = "NTGRcryptD";
252 reg = <0x63c0000 0x500000>;
257 reg = <0x68c0000 0x100000>;
262 reg = <0x69c0000 0x640000>;
283 pinctrl-names = "default", "dbdc";
284 pinctrl-0 = <&wf_2g_5g_pins>;
285 pinctrl-1 = <&wf_dbdc_pins>;
287 mediatek,mtd-eeprom = <&factory 0x0>;